diff options
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 3 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index b1c4c783b7..396072448d 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -187,4 +187,12 @@ config ENABLE_RMT help Enable Rank Margining Tool. This option is intended for debugging and validation and should normally be disabled. + +config RMT_MEM_POR_FREQ + bool "Enforce Plan Of Record restrictions for DDR5 frequency and voltage" + default n + depends on ENABLE_RMT + help + When RMT is enabled. Select this option to enforce Intel Plan Of Record(POR) + restriction on DDR5 frequency & voltage settings. endif diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 2b377a4d6b..4cce21f249 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -279,7 +279,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.serialDebugMsgLvl = 0x3; mupd->FspmConfig.AllowedSocketsInParallel = 0x1; mupd->FspmConfig.EnforcePopulationPor = 0x1; - mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; + if (CONFIG(RMT_MEM_POR_FREQ)) + mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; } /* SPR-FSP has no UPD to disable HDA, so do it manually here... */ |