diff options
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 9 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/scs.asl | 16 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h | 2 |
4 files changed, 32 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cd8819d2cc..927409d281 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -235,6 +235,15 @@ config CBFS_SIZE hex default 0x200000 +config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE + bool + default n + help + Select this if the board has a SD_PWR_ENABLE pin connected to a + active high sensing load switch to turn on power to the card reader. + This will enable a workaround in ASL _PS3 and _PS0 methods to force + SD_PWR_ENABLE to stay low in D3. + choice prompt "Cache-as-ram implementation" default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 896fd77c19..1806e75e87 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -111,6 +111,11 @@ Scope (\_SB.PCI0) { /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) + +#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) + /* Change pad mode to Native */ + GPMO(SD_PWR_EN_PIN, 0x1) +#endif } Method (_PS3, 0, Serialized) @@ -120,6 +125,17 @@ Scope (\_SB.PCI0) { /* Set Power State to D3 */ Or (PMCR, 0x0003, PMCR) Store (PMCR, ^TEMP) + +#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) + /* Change pad mode to GPIO control */ + GPMO(SD_PWR_EN_PIN, 0x0) + + /* Enable Tx Buffer */ + GTXE(SD_PWR_EN_PIN, 0x1) + + /* Drive TX to zero */ + CTXS(SD_PWR_EN_PIN) +#endif } Device (CARD) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 17a014b97e..1ebde35e05 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -208,10 +208,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } dev = dev_find_slot(0, PCH_DEVFN_SDCARD); - if (!dev) + if (!dev) { params->ScsSdCardEnabled = 0; - else + } else { params->ScsSdCardEnabled = dev->enabled; + params->SdCardPowerEnableActiveHigh = + IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); + } dev = dev_find_slot(0, PCH_DEVFN_UFS); if (!dev) diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index 5d7c0e884c..03f431421f 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -352,4 +352,6 @@ #define NUM_GPIO_COM3_PADS (GPIO_RSVD_38 - HDA_BCLK + 1) #define TOTAL_PADS 275 + +#define SD_PWR_EN_PIN GPP_A17 #endif |