diff options
| -rw-r--r-- | src/arch/x86/include/arch/romstage.h | 2 | ||||
| -rw-r--r-- | src/arch/x86/postcar_loader.c | 14 | ||||
| -rw-r--r-- | src/cpu/intel/car/romstage.c | 4 | ||||
| -rw-r--r-- | src/drivers/amd/agesa/romstage.c | 3 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 3 |
5 files changed, 13 insertions, 13 deletions
diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 5951766a3c..d637d19b8a 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -43,7 +43,7 @@ void fill_postcar_frame(struct postcar_frame *pcf); * prepare_and_run_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -void prepare_and_run_postcar(struct postcar_frame *pcf); +void prepare_and_run_postcar(void); /* * Systems without a native coreboot cache-as-ram teardown may implement diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index b5bfe3e6c9..af8152d72b 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -21,6 +21,8 @@ static size_t var_mtrr_ctx_size(void) static int postcar_frame_init(struct postcar_frame *pcf) { + memset(pcf, 0, sizeof(*pcf)); + struct var_mtrr_context *ctx; ctx = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, var_mtrr_ctx_size()); @@ -61,16 +63,18 @@ static void run_postcar_phase(struct postcar_frame *pcf); /* prepare_and_run_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -void prepare_and_run_postcar(struct postcar_frame *pcf) +void prepare_and_run_postcar(void) { - if (postcar_frame_init(pcf)) + struct postcar_frame pcf; + + if (postcar_frame_init(&pcf)) die("Unable to initialize postcar frame.\n"); - fill_postcar_frame(pcf); + fill_postcar_frame(&pcf); - postcar_frame_common_mtrrs(pcf); + postcar_frame_common_mtrrs(&pcf); - run_postcar_phase(pcf); + run_postcar_phase(&pcf); /* We do not return here. */ } diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 85bc894afa..a307893c11 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -14,8 +14,6 @@ following as a guideline for acceptable stack usage. */ #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 -static struct postcar_frame early_mtrrs; - static void romstage_main(void) { int i; @@ -54,7 +52,7 @@ static void romstage_main(void) if (CONFIG(SMM_TSEG)) smm_list_regions(); - prepare_and_run_postcar(&early_mtrrs); + prepare_and_run_postcar(); /* We do not return here. */ } diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 9abcdd6110..35b2778e68 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -33,7 +33,6 @@ static void ap_romstage_main(void); static void romstage_main(void) { - struct postcar_frame pcf; struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; int cbmem_initted = 0; @@ -78,7 +77,7 @@ static void romstage_main(void) romstage_handoff_init(cb->s3resume); - prepare_and_run_postcar(&pcf); + prepare_and_run_postcar(); /* We do not return. */ } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index aa54aee266..b7731b0d8f 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -50,7 +50,6 @@ static void bsp_agesa_call(void) asmlinkage void car_stage_entry(void) { - struct postcar_frame pcf; msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; @@ -121,7 +120,7 @@ asmlinkage void car_stage_entry(void) smm_list_regions(); post_code(0x44); - prepare_and_run_postcar(&pcf); + prepare_and_run_postcar(); } void fill_postcar_frame(struct postcar_frame *pcf) |