diff options
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 18 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 38 |
2 files changed, 35 insertions, 21 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 78cfb9f004..5acad201c6 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> +#include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> @@ -86,14 +87,21 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; - + /* Check if IGD is present and fill Graphics init param accordingly */ dev = pcidev_path_on_root(SA_DEVFN_IGD); if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) params->PeiGraphicsPeimInit = 1; else params->PeiGraphicsPeimInit = 0; + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->SkipMpInit = 0; + } else { + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + } + params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = 0x09000000; @@ -144,7 +152,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->PcieRpAdvancedErrorReporting[i]; } /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { if (!xdci_can_enable()) dev->enabled = 0; @@ -159,7 +167,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; /* SATA */ - dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); + dev = pcidev_path_on_root(PCH_DEVFN_SATA); if (!dev) params->SataEnable = 0; else { @@ -173,7 +181,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* LAN */ - dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 993320054a..6056b4b0c1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -20,8 +20,17 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, uint32_t mask = 0; const struct device *dev; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (!dev || !dev->enabled) { + /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ + m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; + } else { + m_cfg->InternalGfx = 1; + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + } + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; @@ -60,22 +69,19 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; - /* UART Debug Log */ + /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : - DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB; - m_cfg->PcdIsaSerialUartBase = 0x0; - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } - /* - * Skip IGD initialization in FSP if device - * is disable in devicetree.cb. - */ - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) - m_cfg->InternalGfx = 0; - else - m_cfg->InternalGfx = 0x1; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); |