diff options
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 18 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chipset_pch_s.cb | 36 |
2 files changed, 53 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index c4de08f75c..f54cac2c42 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -36,12 +36,18 @@ enum soc_intel_alderlake_power_limits { ADL_S_882_35W_CORE, ADL_S_882_65W_CORE, ADL_S_882_125W_CORE, + ADL_S_882_150W_CORE, ADL_S_842_35W_CORE, ADL_S_842_65W_CORE, ADL_S_842_125W_CORE, ADL_S_642_125W_CORE, ADL_S_602_35W_CORE, ADL_S_602_65W_CORE, + ADL_S_402_60W_CORE, + ADL_S_402_58W_CORE, + ADL_S_402_35W_CORE, + ADL_S_202_46W_CORE, + ADL_S_202_35W_CORE, RPL_P_682_642_482_45W_CORE, RPL_P_682_482_282_28W_CORE, RPL_P_282_242_142_15W_CORE, @@ -57,8 +63,12 @@ enum soc_intel_alderlake_cpu_tdps { TDP_28W = 28, TDP_35W = 35, TDP_45W = 45, + TDP_46W = 46, + TDP_58W = 58, + TDP_60W = 60, TDP_65W = 65, - TDP_125W = 125 + TDP_125W = 125, + TDP_150W = 150 }; /* Mapping of different SKUs based on CPU ID and TDP values */ @@ -87,12 +97,18 @@ static const struct { { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W }, + { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_150W_CORE, TDP_150W }, { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_65W_CORE, TDP_65W }, { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_125W_CORE, TDP_125W }, { PCI_DID_INTEL_ADL_S_ID_8, ADL_S_642_125W_CORE, TDP_125W }, { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_65W_CORE, TDP_65W }, + { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_35W_CORE, TDP_35W }, + { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_58W_CORE, TDP_58W }, + { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W }, + { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, + { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index 2ade3816d0..a2337d6f36 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -20,6 +20,12 @@ chip soc/intel/alderlake .tdp_pl4 = 359, }" + register "power_limits_config[ADL_S_882_150W_CORE]" = "{ + .tdp_pl1_override = 150, + .tdp_pl2_override = 241, + .tdp_pl4 = 359, + }" + register "power_limits_config[ADL_S_842_35W_CORE]" = "{ .tdp_pl1_override = 35, .tdp_pl2_override = 99, @@ -56,6 +62,36 @@ chip soc/intel/alderlake .tdp_pl4 = 176, }" + register "power_limits_config[ADL_S_402_60W_CORE]" = "{ + .tdp_pl1_override = 60, + .tdp_pl2_override = 89, + .tdp_pl4 = 125, + }" + + register "power_limits_config[ADL_S_402_58W_CORE]" = "{ + .tdp_pl1_override = 58, + .tdp_pl2_override = 89, + .tdp_pl4 = 125, + }" + + register "power_limits_config[ADL_S_402_35W_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 69, + .tdp_pl4 = 98, + }" + + register "power_limits_config[ADL_S_202_46W_CORE]" = "{ + .tdp_pl1_override = 46, + .tdp_pl2_override = 46, + .tdp_pl4 = 57, + }" + + register "power_limits_config[ADL_S_202_35W_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 35, + .tdp_pl4 = 44, + }" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. |