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-rw-r--r--src/mainboard/asus/f2a85-m/Kconfig2
-rw-r--r--src/mainboard/asus/f2a85-m/agesawrapper.c7
-rw-r--r--src/mainboard/asus/f2a85-m/buildOpts.c1
-rw-r--r--src/mainboard/asus/f2a85-m/devicetree.cb32
-rw-r--r--src/mainboard/asus/f2a85-m/romstage.c16
5 files changed, 33 insertions, 25 deletions
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index c923b5bfb1..6dea246f98 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
- select SUPERIO_ITE_IT8712F
+ select SUPERIO_ITE_IT8728F
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c
index fdf7457550..7a25719214 100644
--- a/src/mainboard/asus/f2a85-m/agesawrapper.c
+++ b/src/mainboard/asus/f2a85-m/agesawrapper.c
@@ -132,8 +132,6 @@ agesawrapper_amdinitmmio (
{
AGESA_STATUS Status;
UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@@ -150,11 +148,6 @@ agesawrapper_amdinitmmio (
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
- /* For serial port */
- PciData = 0xFF03FFD5;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index cbd1071903..0c6b657add 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -306,6 +306,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 0014381a64..25fe5db5cd 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -60,7 +60,14 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
- chip superio/ite/it8712f
+ chip superio/ite/it8728f
+ register hwm_ctl_register = "0xc0"
+ register hwm_main_ctl_register = "0x33"
+ register hwm_adc_temp_chan_en_reg = "0x38"
+ register hwm_fan1_ctl_pwm = "0x00"
+ register hwm_fan2_ctl_pwm = "0x80"
+ register hwm_fan3_ctl_pwm = "0x00"
+
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
@@ -78,7 +85,11 @@ chip northbridge/amd/agesa/family15tn/root_complex
io 0x60 = 0x378
irq 0x70 = 7
end
- device pnp 2e.4 off end # EC
+ device pnp 2e.4 on # Env Controller
+ io 0x60 = 0x290
+ io 0x62 = 0x220
+ irq 0x70 = 0
+ end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
@@ -87,19 +98,16 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pnp 2e.6 off # Mouse
irq 0x70 = 12
end
- device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.9 off # GAME
- io 0x60 = 0x220
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x228 #SMI
+ io 0x62 = 0x300 #Simple I/O
+ io 0x64 = 0x238 #Phony resource IT8603E does not have it
+ irq 0x70 = 0
end
device pnp 2e.a off end # CIR
- end #superio/ite/it8712f
+ end #superio/ite/it8728f
end #device pci 14.3 # LPC
- device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
+ device pci 14.4 on end # PCI 0x4384
device pci 14.5 on end # USB 2
device pci 14.6 off end # Gec
# SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away)
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index ffd91bfd6e..3884e364d0 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -37,14 +37,15 @@
#include <stdint.h>
#include <string.h>
#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
+#include <superio/ite/it8728f/it8728f.h>
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
static void sbxxx_enable_48mhzout(void)
{
@@ -80,12 +81,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
- /* enable SIO decode */
+ /* enable SIO LPC decode */
dev = PCI_DEV(0, 0x14, 3);
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
post_code(0x30);
/* enable SB MMIO space */
@@ -94,9 +100,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable SIO clock */
sbxxx_enable_48mhzout();
- it8712f_kill_watchdog();
+ ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- it8712f_enable_3vsbsw();
+ ite_enable_3vsbsw(GPIO_DEV);
console_init();
/* turn on secondary smbus at b20 */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-22 06:21:16 +0000