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-rw-r--r--src/cpu/amd/model_lx/cpubug.c3
-rw-r--r--src/cpu/amd/model_lx/model_lx_init.c7
-rw-r--r--src/cpu/amd/model_lx/vsmsetup.c166
-rw-r--r--src/include/cpu/amd/lxdef.h117
-rw-r--r--src/northbridge/amd/lx/chipsetinit.c2
-rw-r--r--src/northbridge/amd/lx/grphinit.c32
-rw-r--r--src/northbridge/amd/lx/northbridge.c472
-rw-r--r--src/northbridge/amd/lx/northbridge.h1
-rw-r--r--src/northbridge/amd/lx/northbridgeinit.c140
-rw-r--r--src/northbridge/amd/lx/pll_reset.c56
-rw-r--r--src/northbridge/amd/lx/raminit.c74
-rw-r--r--targets/artecgroup/dbe61/Config.lb17
12 files changed, 606 insertions, 481 deletions
diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c
index 4bbab3f933..124fc409fb 100644
--- a/src/cpu/amd/model_lx/cpubug.c
+++ b/src/cpu/amd/model_lx/cpubug.c
@@ -349,9 +349,10 @@ void disablememoryreadorder(void)
void
cpubug(void)
{
+#if 0 //GX3: any CPU bugs to fix here? :)
msr_t msr;
int rev;
-#if 0 //GX3
+
msr = rdmsr(GLCP_CHIP_REVID);
rev = msr.lo & 0xff;
diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/model_lx/model_lx_init.c
index 9eee1833e9..b24651102e 100644
--- a/src/cpu/amd/model_lx/model_lx_init.c
+++ b/src/cpu/amd/model_lx/model_lx_init.c
@@ -5,6 +5,7 @@
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
+#include <arch/io.h>
static void vsm_end_post_smi(void)
{
@@ -27,8 +28,14 @@ static void model_lx_init(device_t dev)
/* Enable the local cpu apics */
//setup_lapic();
+ // do VSA late init
vsm_end_post_smi();
+ // Set gate A20 (legacy vsm disables it in late init)
+ printk_debug("A20 (0x92): %d\n",inb(0x92));
+ outb(0x02,0x92);
+ printk_debug("A20 (0x92): %d\n",inb(0x92));
+
printk_debug("model_lx_init DONE\n");
};
diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c
index 965f3480a0..3edced36e3 100644
--- a/src/cpu/amd/model_lx/vsmsetup.c
+++ b/src/cpu/amd/model_lx/vsmsetup.c
@@ -6,13 +6,14 @@
#include <arch/io.h>
#include <string.h>
#include <cpu/amd/lxdef.h>
+#include <cpu/amd/vr.h>
-/* what a mess this uncompress thing is. I am not at all happy about how this
- * was done, but can't fix it yet. RGM
- */
-#warning "Fix the uncompress once linuxbios knows how to do it"
+// andrei: use the /lib copy of nrv2b
#include "../lib/nrv2b.c"
+#define VSA2_BUFFER 0x60000
+#define VSA2_ENTRY_POINT 0x60020
+
/* vsmsetup.c derived from vgabios.c. Derived from: */
/*------------------------------------------------------------ -*- C -*-
@@ -67,7 +68,7 @@
* negligence or otherwise) arising in any way out of the use of this
* software, even if advised of the possibility of such damage.
*
- * $Id: Exp $
+ * $Id: vsmsetup.c,v 1.8 2006/09/08 12:47:57 andrei Exp $
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
@@ -137,29 +138,32 @@ __asm__ ("__myidt: \n"
/* The address arguments to this function are PHYSICAL ADDRESSES */
static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
{
+ uint16_t entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4;
+ uint16_t entryLo = (VSA2_ENTRY_POINT & 0xffff);
+
__asm__ __volatile__ (
// paranoia -- does ecx get saved? not sure. This is
// the easiest safe thing to do.
" pushal \n"
/* save the stack */
- " mov %esp, __stack \n"
+ " mov %%esp, __stack \n"
" jmp 1f \n"
"__stack: .long 0 \n"
"1:\n"
- /* get devfn into %ecx */
- " movl %esp, %ebp \n"
+ /* get devfn into %%ecx */
+ " movl %%esp, %%ebp \n"
#if 0
/* I'm not happy about that pushal followed by esp-relative references.
* just do hard-codes for now
*/
- " movl 8(%ebp), %ecx \n"
- " movl 12(%ebp), %edx \n"
+ " movl 8(%%ebp), %%ecx \n"
+ " movl 12(%%ebp), %%edx \n"
#endif
- " movl $0x10000026, %ecx \n"
- " movl $0x10000028, %edx \n"
+ " movl %0, %%ecx \n"
+ " movl %1, %%edx \n"
/* load 'our' gdt */
- " lgdt %cs:__mygdtaddr \n"
+ " lgdt %%cs:__mygdtaddr \n"
/* This configures CS properly for real mode. */
" ljmp $0x28, $__rms_16bit\n"
@@ -170,17 +174,17 @@ static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
/* Load the segment registers w/ properly configured segment
* descriptors. They will retain these configurations (limits,
* writability, etc.) once protected mode is turned off. */
- " mov $0x30, %ax \n"
- " mov %ax, %ds \n"
- " mov %ax, %es \n"
- " mov %ax, %fs \n"
- " mov %ax, %gs \n"
- " mov %ax, %ss \n"
+ " mov $0x30, %%ax \n"
+ " mov %%ax, %%ds \n"
+ " mov %%ax, %%es \n"
+ " mov %%ax, %%fs \n"
+ " mov %%ax, %%gs \n"
+ " mov %%ax, %%ss \n"
/* Turn off protection (bit 0 in CR0) */
- " movl %cr0, %eax \n"
- " andl $0xFFFFFFFE, %eax \n"
- " movl %eax, %cr0 \n"
+ " movl %%cr0, %%eax \n"
+ " andl $0xFFFFFFFE, %%eax \n"
+ " movl %%eax, %%cr0 \n"
/* Now really going into real mode */
" ljmp $0, $__rms_real\n"
@@ -190,61 +194,98 @@ static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
* that way we can easily share it between real and protected,
* since the 16-bit ESP at segment 0 will work for any case. */
/* Setup a stack */
- " mov $0x0, %ax \n"
- " mov %ax, %ss \n"
- " movl $0x1000, %eax \n"
- " movl %eax, %esp \n"
+ " mov $0x0, %%ax \n"
+ " mov %%ax, %%ss \n"
+ " movl $0x1000, %%eax \n"
+ " movl %%eax, %%esp \n"
/* Load our 16 it idt */
- " xor %ax, %ax \n"
- " mov %ax, %ds \n"
+ " xor %%ax, %%ax \n"
+ " mov %%ax, %%ds \n"
" lidt __myidt \n"
/* Dump zeros in the other segregs */
- " mov %ax, %es \n"
+ " mov %%ax, %%es \n"
/* FixMe: Big real mode for gs, fs? */
- " mov %ax, %fs \n"
- " mov %ax, %gs \n"
- " mov $0x40, %ax \n"
- " mov %ax, %ds \n"
- //" mov %cx, %ax \n"
- " movl $0x10000026, %ecx \n"
- " movl $0x10000028, %edx \n"
+ " mov %%ax, %%fs \n"
+ " mov %%ax, %%gs \n"
+ " mov $0x40, %%ax \n"
+ " mov %%ax, %%ds \n"
+ //" mov %%cx, %%ax \n"
+ " movl %0, %%ecx \n"
+ " movl %1, %%edx \n"
- /* run VGA BIOS at 0x6000:0020 */
- " lcall $0x6000, $0x0020\n"
+ /* call the VSA2 entry point address */
+ " lcall %2, %3\n"
/* if we got here, just about done.
* Need to get back to protected mode */
- " movl %cr0, %eax \n"
- " orl $0x0000001, %eax\n" /* PE = 1 */
- " movl %eax, %cr0 \n"
+ " movl %%cr0, %%eax \n"
+ " orl $0x0000001, %%eax\n" /* PE = 1 */
+ " movl %%eax, %%cr0 \n"
/* Now that we are in protected mode jump to a 32 bit code segment. */
" data32 ljmp $0x10, $vsmrestart\n"
"vsmrestart:\n"
" .code32\n"
- " movw $0x18, %ax \n"
- " mov %ax, %ds \n"
- " mov %ax, %es \n"
- " mov %ax, %fs \n"
- " mov %ax, %gs \n"
- " mov %ax, %ss \n"
+ " movw $0x18, %%ax \n"
+ " mov %%ax, %%ds \n"
+ " mov %%ax, %%es \n"
+ " mov %%ax, %%fs \n"
+ " mov %%ax, %%gs \n"
+ " mov %%ax, %%ss \n"
/* restore proper gdt and idt */
- " lgdt %cs:gdtarg \n"
+ " lgdt %%cs:gdtarg \n"
" lidt idtarg \n"
".globl vsm_exit \n"
"vsm_exit: \n"
- " mov __stack, %esp \n"
+ " mov __stack, %%esp \n"
" popal \n"
- );
+ :: "g" (smm), "g" (sysm), "g" (entryHi), "g" (entryLo));
}
__asm__ (".text\n""real_mode_switch_end:\n");
extern char real_mode_switch_end[];
+// andrei: some VSA virtual register helpers: raw read and MSR read
+
+uint32_t VSA_vrRead(uint16_t classIndex)
+{
+ unsigned eax, ebx, ecx, edx;
+ asm volatile(
+
+ "movw $0x0AC1C, %%dx \n"
+ "orl $0x0FC530000, %%eax \n"
+ "outl %%eax, %%dx \n"
+ "addb $2, %%dl \n"
+ "inw %%dx, %%ax \n"
+
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (classIndex)
+ );
+
+ return eax;
+}
+
+uint32_t VSA_msrRead(uint32_t msrAddr)
+{
+ unsigned eax, ebx, ecx, edx;
+ asm volatile(
+
+ "movw $0x0AC1C, %%dx \n"
+ "movl $0x0FC530007, %%eax \n"
+ "outl %%eax, %%dx \n"
+ "addb $2, %%dl \n"
+ "inw %%dx, %%ax \n"
+
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "c" (msrAddr)
+ );
+
+ return eax;
+}
void do_vsmbios(void)
{
@@ -272,9 +313,9 @@ void do_vsmbios(void)
/* the VSA starts at the base of rom - 64 */
//rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024);
- rom = 0xfffc0000;
+ rom = 0xfffc8000;
- buf = (unsigned char *) 0x60000;
+ buf = (unsigned char *) VSA2_BUFFER;
unrv2b((uint8_t *)rom, buf);
printk_debug("buf %p *buf %d buf[256k] %d\n",
buf, buf[0], buf[SMM_SIZE*1024]);
@@ -288,18 +329,23 @@ void do_vsmbios(void)
return;
}
- //memcpy((void *) 0x60000, buf, size);
+ //memcpy((void *) VSA2_BUFFER, buf, size);
//for (i = 0; i < 0x800000; i++)
// outb(0xaa, 0x80);
/* ecx gets smm, edx gets sysm */
printk_err("Call real_mode_switch_call_vsm\n");
- real_mode_switch_call_vsm(0x10000026, 0x10000028);
+ real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
/* restart timer 1 */
outb(0x56, 0x43);
outb(0x12, 0x41);
+
+ // check that VSA is running OK
+ if(VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
+ printk_debug("do_vsmbios: VSA2 VR signature verified\n");
+ else printk_err("do_vsmbios: VSA2 VR signature not valid, install failed!\n");
}
@@ -520,7 +566,7 @@ int biosint(unsigned long intnumber,
break;
case MEMSIZE:
// who cares.
- eax = 64 * 1024;
+ eax = 128 * 1024;
ret = 0;
break;
case 0x15:
@@ -562,7 +608,7 @@ void setup_realmode_idt(void)
// and get it that way. But that's really disgusting.
for (i = 0; i < 256; i++) {
idts[i].cs = 0;
- codeptr = (char*) 4096 + i * codesize;
+ codeptr = (unsigned char*) 4096 + i * codesize;
idts[i].offset = (unsigned) codeptr;
memcpy(codeptr, &idthandle, codesize);
intbyte = codeptr + 3;
@@ -575,7 +621,7 @@ void setup_realmode_idt(void)
// int10.
// calling convention here is the same as INTs, we can reuse
// the int entry code.
- codeptr = (char*) 0xff065;
+ codeptr = (unsigned char*) 0xff065;
memcpy(codeptr, &idthandle, codesize);
intbyte = codeptr + 3;
*intbyte = 0x42; /* int42 is the relocated int10 */
@@ -584,7 +630,7 @@ void setup_realmode_idt(void)
TF bit is set upon call to real mode */
idts[1].cs = 0;
idts[1].offset = 16384;
- memcpy(16384, &debughandle, &end_debughandle - &debughandle);
+ memcpy((void*)16384, &debughandle, &end_debughandle - &debughandle);
}
@@ -761,10 +807,10 @@ int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp,
*eax=0x860f;
break;
case 0xBEA7:
- *eax=33;
+ *eax=66;
break;
case 0xBEA4:
- *eax=333;
+ *eax=500;
break;
}
return res;
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 3f174f3507..6f7677bede 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -221,12 +221,19 @@
#define CPU_IM_BIST_DATA 0x1731
+/* ----- GX3 OK ---- */
+
/* various CPU MSRs */
#define CPU_DM_CONFIG0 0x1800
#define DM_CONFIG0_UPPER_WSREQ_SHIFT 12
#define DM_CONFIG0_LOWER_DCDIS_SET (1<<8)
#define DM_CONFIG0_LOWER_WBINVD_SET (1<<5)
#define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
+
+#define CPU_DM_CONFIG1 0x1801
+
+#define CPU_DM_PFLOCK 0x1804
+
/* configuration MSRs */
#define CPU_RCONF_DEFAULT 0x1808
#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
@@ -236,7 +243,6 @@
#define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8
#define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0
-/* ----- GX3 OK ---- */
#define CPU_RCONF_BYPASS 0x180A
#define CPU_RCONF_A0_BF 0x180B
@@ -421,20 +427,24 @@
#define GLPCI_CTRL_LOWER_ME_SET (1<<0)
#define GLPCI_ARB (MSR_PCI + 0x2011)
-#define GLPCI_ARB_UPPER_BM1_SET (1<<17)
-#define GLPCI_ARB_UPPER_BM0_SET (1<<16)
-#define GLPCI_ARB_UPPER_CPRE_SET (1<<15)
-#define GLPCI_ARB_UPPER_PRE2_SET (1<<10)
-#define GLPCI_ARB_UPPER_PRE1_SET (1<<9)
-#define GLPCI_ARB_UPPER_PRE0_SET (1<<8)
-#define GLPCI_ARB_UPPER_CRME_SET (1<<7)
-#define GLPCI_ARB_UPPER_RME2_SET (1<<2)
-#define GLPCI_ARB_UPPER_RME1_SET (1<<1)
-#define GLPCI_ARB_UPPER_RME0_SET (1<<0)
-#define GLPCI_ARB_LOWER_PRCM_SHIFT 24
-#define GLPCI_ARB_LOWER_FPVEC_SHIFT 16
-#define GLPCI_ARB_LOWER_RMT_SHIFT 6
-#define GLPCI_ARB_LOWER_IIE_SET (1<<8)
+#define GLPCI_ARB_UPPER_CR_SHIFT (28)
+#define GLPCI_ARB_UPPER_R2_SHIFT (24)
+#define GLPCI_ARB_UPPER_R1_SHIFT (20)
+#define GLPCI_ARB_UPPER_R0_SHIFT (16)
+#define GLPCI_ARB_UPPER_CH_SHIFT (12)
+#define GLPCI_ARB_UPPER_H2_SHIFT (8)
+#define GLPCI_ARB_UPPER_H1_SHIFT (4)
+#define GLPCI_ARB_UPPER_H0_SHIFT (0)
+#define GLPCI_ARB_LOWER_COV_SET (1<<23)
+#define GLPCI_ARB_LOWER_MSK2_SET (1<<18)
+#define GLPCI_ARB_LOWER_MSK1_SET (1<<17)
+#define GLPCI_ARB_LOWER_MSK0_SET (1<<16)
+#define GLPCI_ARB_LOWER_CPRE_SET (1<<11)
+#define GLPCI_ARB_LOWER_PRE2_SET (1<<10)
+#define GLPCI_ARB_LOWER_PRE1_SET (1<<9)
+#define GLPCI_ARB_LOWER_PRE0_SET (1<<8)
+#define GLPCI_ARB_LOWER_BM1_SET (1<<7)
+#define GLPCI_ARB_LOWER_BM0_SET (1<<6)
#define GLPCI_ARB_LOWER_PARK_SET (1<<0)
#define GLPCI_REN (MSR_PCI + 0x2014)
@@ -507,24 +517,83 @@
/* Set up desc addresses from 20 - 3f*/
/* This is chip specific!*/
+
+/* ---------- GX3 OK -------------- */
#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/
#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/
+#define MSR_GLIU0_BASE3 (MSR_GLIU0 + 0x22) /* BM*/
+#define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* BM*/
+#define MSR_GLIU0_BASE5 (MSR_GLIU0 + 0x24) /* BM*/
+#define MSR_GLIU0_BASE6 (MSR_GLIU0 + 0x25) /* BM*/
+
+#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26)
+#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27)
+
+#define MSR_GLIU0_SMM (GLIU0_P2D_BMO_0)
+#define MSR_GLIU0_DMM (GLIU0_P2D_BMO_1)
+
+#define GLIU0_P2D_R (MSR_GLIU0 + 0x28)
+#define MSR_GLIU0_SYSMEM (GLIU0_P2D_R)
+
+#define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29)
+#define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A)
+#define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B)
+
#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
-#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/
-#define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO*/
-#define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO*/
+
+#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
+#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
+#define GLIU0_IOD_BM_2 (MSR_GLIU0 + 0xE2)
+
+#define GLIU0_IOD_SC_0 (MSR_GLIU0 + 0xE3)
+#define GLIU0_IOD_SC_1 (MSR_GLIU0 + 0xE4)
+#define GLIU0_IOD_SC_2 (MSR_GLIU0 + 0xE5)
+#define GLIU0_IOD_SC_3 (MSR_GLIU0 + 0xE6)
+#define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7)
+#define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8)
+
#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/
#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/
-#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E) /* SCO should only be SC*/ // GX3 0x2D -> 0x2E
-#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x2A) /* RO should only be R*/ // GX3 0x29 -> 0x2A
-#define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM*/
-#define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM*/
-#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/
+#define MSR_GLIU1_BASE3 (MSR_GLIU1 + 0x22) /* BM*/
+#define MSR_GLIU1_BASE4 (MSR_GLIU1 + 0x23) /* BM*/
+#define MSR_GLIU1_BASE5 (MSR_GLIU1 + 0x24) /* BM*/
+#define MSR_GLIU1_BASE6 (MSR_GLIU1 + 0x25) /* BM*/
+#define MSR_GLIU1_BASE7 (MSR_GLIU1 + 0x26) /* BM*/
+#define MSR_GLIU1_BASE8 (MSR_GLIU1 + 0x27) /* BM*/
+#define MSR_GLIU1_BASE9 (MSR_GLIU1 + 0x28) /* BM*/
+#define MSR_GLIU1_BASE10 (MSR_GLIU1 + 0x29) /* BM*/
+
+#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x2A)
+#define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2B)
+#define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2C)
+#define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2D)
+
+
+#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E)
+
+#define MSR_GLIU1_SYSMEM (GLIU1_P2D_R_0)
+
+#define MSR_GLIU1_SMM (MSR_GLIU1_BASE4) /* BM*/
+#define MSR_GLIU1_DMM (MSR_GLIU1_BASE5) /* BM*/
+
+#define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0)
+#define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1)
+#define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2)
+
+#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3)
+#define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4)
+#define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5)
+#define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6)
+
+/* ------------------------ */
+
+#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/
+
/* definitions that are "once you are mostly up, start VSA" type things */
#define SMM_OFFSET (0x40400000)
-#define SMM_SIZE (128) /* changed SMM_SIZE from 256 KB to 128 KB */
+#define SMM_SIZE (256)
#define DMM_OFFSET (0x0C0000000)
#define DMM_SIZE (128)
#define FB_OFFSET (0x41000000)
diff --git a/src/northbridge/amd/lx/chipsetinit.c b/src/northbridge/amd/lx/chipsetinit.c
index 0178079795..4e0d329512 100644
--- a/src/northbridge/amd/lx/chipsetinit.c
+++ b/src/northbridge/amd/lx/chipsetinit.c
@@ -274,7 +274,7 @@ ChipsetGeodeLinkInit(void){
if ((msr.lo&0xff) == 0x11)
return;
- totalmem = sizeram() << 20 - 1;
+ totalmem = (sizeram() << 20) - 1;
totalmem >>= 12;
totalmem = ~totalmem;
totalmem &= 0xfffff;
diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c
index 4e0da1789d..82636aa1fe 100644
--- a/src/northbridge/amd/lx/grphinit.c
+++ b/src/northbridge/amd/lx/grphinit.c
@@ -1,8 +1,7 @@
#include <arch/io.h>
#include <stdint.h>
#include <cpu/amd/vr.h>
-
-#define VIDEO_MB 8 // MB of video memory
+#include <console/console.h>
/*
* Write to a Virtual Register
@@ -33,11 +32,36 @@ uint16_t vrRead(uint16_t wClassIndex)
*/
void graphics_init(void)
{
+ uint16_t wClassIndex, wData, res;
+
/* SoftVG initialization */
+ printk_debug("Graphics init...\n");
/* Call SoftVG with the main configuration parameters. */
- /* NOTE: SoftVG expects the memory size to be given in 512 KB pages */
- vrWrite((VRC_VG << 8) + VG_MEM_SIZE, 0x0100 | (VIDEO_MB * 2));
+ /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
+
+ wClassIndex = (VRC_VG << 8) + VG_MEM_SIZE;
+
+ /*
+ * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP)
+ * External Monochrome Card Support(12) 0, NO
+ * Controller Priority Select(11) 1, Primary
+ * Display Select(10:8) 0x0, CRT
+ * Graphics Memory Size(7:1) VIDEO_MB >> 1,
+ * defined in mainboard/../Options.lb
+ * PLL Reference Clock Bypass(0) 0, Default
+ */
+
+ /* video RAM has to be given in 2MB chunks
+ * the value is read @ 7:1 (value in 7:0 looks like /2)
+ * so we can add the real value in megabytes
+ */
+
+ wData = 0x0800 | (VIDEO_MB & VG_MEM_MASK);
+ vrWrite(wClassIndex, wData);
+
+ res = vrRead(wClassIndex);
+ printk_debug("VRC_VG value: 0x%04x\n", res);
}
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 14617243dd..7d84c5c2d3 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -14,41 +14,6 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/vr.h>
-#define VIDEO_MB 8
-
-extern void graphics_init(void);
-
-#define NORTHBRIDGE_FILE "northbridge.c"
-
-/* todo: add a resource record. We don't do this here because this may be called when
- * very little of the platform is actually working.
- */
-int
-sizeram(void)
-{
- msr_t msr;
- int sizem = 0;
- unsigned short dimm;
-
- msr = rdmsr(0x20000018);
- printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
-
- /* dimm 0 */
- dimm = msr.hi;
- /* installed? */
- if ((dimm & 7) != 7)
- sizem = (1 << ((dimm >> 12)-1)) * 8;
-
-
- /* dimm 1*/
- dimm = msr.hi >> 16;
- /* installed? */
- if ((dimm & 7) != 7)
- sizem += (1 << ((dimm >> 12)-1)) * 8;
-
- printk_debug("sizeram: sizem 0x%x\n", sizem);
- return sizem;
-}
/* here is programming for the various MSRs.*/
@@ -87,7 +52,15 @@ sizeram(void)
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
+#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
+
+extern void graphics_init(void);
+extern void cpubug(void);
+void northbridge_init_early(void);
+void chipsetinit(struct northbridge_amd_lx_config *nb);
+void setup_realmode_idt(void);
+void do_vsmbios(void);
struct msr_defaults {
int msr_no;
@@ -111,16 +84,44 @@ struct msr_defaults {
//{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
/* now for GLPCI routing */
/* GLIU0 */
- P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
- P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
- P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
+ P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80),
+ P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
+ P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
/* GLIU1 */
- P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
- P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
- P2D_SC(0x4000002e, 0x1, 0x0, 0x0, 0xff03, 0xC0000), // GX3 0x4000002d -> 0x4000002e
+ P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80),
+ P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
+ P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
{0}
};
+/* todo: add a resource record. We don't do this here because this may be called when
+ * very little of the platform is actually working.
+ */
+int
+sizeram(void)
+{
+ msr_t msr;
+ int sizem = 0;
+ unsigned short dimm;
+
+ msr = rdmsr(0x20000018);
+ printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
+
+ /* dimm 0 */
+ dimm = msr.hi;
+ sizem = (1 << ((dimm >> 12)-1)) * 8;
+
+
+ /* dimm 1*/
+ dimm = msr.hi >> 16;
+ /* installed? */
+ if ((dimm & 7) != 7)
+ sizem += (1 << ((dimm >> 12)-1)) * 8;
+
+ printk_debug("sizeram: sizem 0x%x\n", sizem);
+ return sizem;
+}
+
/* note that dev is NOT used -- yet */
static void irq_init_steering(struct device *dev, uint16_t irq_map) {
/* Set up IRQ steering */
@@ -173,13 +174,19 @@ setup_lx_cache(void)
/* yank off memory for the SMM handler */
sizekbytes -= SMM_SIZE;
sizereg = sizekbytes;
- sizereg *= 1024; // convert to bytes
- sizereg >>= 12;
+ sizereg >>= 2;
sizereg <<= 8;
val |= sizereg;
val |= RAM_PROPERTIES;
msr.lo = val;
msr.hi = (val >> 32);
+
+ // GX3
+ //msr.hi = 0x04FFFC02;
+ //msr.lo = 0x1077BE00;
+
+ //sizekbytes = 122616;
+
printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
wrmsr(CPU_RCONF_DEFAULT, msr);
@@ -199,6 +206,7 @@ setup_lx(void)
size_kb = setup_lx_cache();
+#if 0 // andrei: this is done in northbridge.c SMMGL0Init and SystemInit!
membytes = size_kb * 1024;
/* NOTE! setup_lx_cache returns the SIZE OF RAM - RAMADJUST!
* so it is safe to use. You should NOT at this point call
@@ -211,23 +219,7 @@ setup_lx(void)
* SYSTOP (a.k.a. TOM, or Top of Memory)
*/
-#if 0
- /* This has already been done elsewhere */
- printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
- msr.hi = 0x20000000 | membytes>>24;
- msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
- wrmsr(0x10000028, msr);
- msr.hi = 0x20000000 | membytes>>24;
- msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
- wrmsr(0x40000029, msr);
-#endif
-#if 0
- msr = rdmsr(0x10000028);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
- msr = rdmsr(0x40000029);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
-#endif
-#if 1
+
/* fixme: SMM MSR 0x10000026 and 0x400000023 */
/* calculate the OFFSET field */
tmp = membytes - SMM_OFFSET;
@@ -244,37 +236,135 @@ setup_lx(void)
msr.lo = tmp2;
wrmsr(0x10000026, msr);
#endif
-#if 0
-
- msr.hi = 0x2cfbc040;
- msr.lo = 0x400fffc0;
- wrmsr(0x10000026, msr);
- msr = rdmsr(0x10000026);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
-#endif
-#if 0
- msr.hi = 0x22fffc02;
- msr.lo = 0x10ffbf00;
- wrmsr(0x1808, msr);
- msr = rdmsr(0x1808);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
-#endif
-#if 0 // SDG - don't do this
- /* now do the default MSR values */
- for(i = 0; msr_defaults[i].msr_no; i++) {
- msr_t msr;
- wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above
- msr = rdmsr(msr_defaults[i].msr_no);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
- }
-#endif
}
static void enable_shadow(device_t dev)
{
-
}
+void print_conf(void) {
+ int i;
+ unsigned long iol;
+ msr_t msr;
+
+ int cpu_msr_defs[] = { L2_CONFIG_MSR, CPU_IM_CONFIG,
+ CPU_DM_CONFIG0, CPU_DM_CONFIG1, CPU_DM_PFLOCK, CPU_RCONF_DEFAULT,
+ CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
+ CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
+ };
+
+ int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE3, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
+ GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
+ GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
+ GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
+ GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
+ GLIU0_GLD_MSR_COH, GL_END
+ };
+
+ int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
+ MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
+ GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
+ GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
+ GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
+ GLIU1_GLD_MSR_COH, GL_END
+ };
+
+ int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
+ CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
+ };
+
+ int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
+ MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
+ };
+
+ int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
+ GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_EXT_MSR, GLPCI_SPARE,
+ GL_END
+ };
+
+ int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
+ MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
+ MDD_DMA_SHAD9, GL_END
+ };
+
+
+ printk_debug("---------- CPU ------------\n");
+
+ for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(cpu_msr_defs[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- GLIU 0 ------------\n");
+
+ for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(gliu0_msr_defs[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- GLIU 1 ------------\n");
+
+ for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(gliu1_msr_defs[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- RCONF ------------\n");
+
+ for(i = 0; rconf_msr[i] != GL_END; i++) {
+ msr = rdmsr(rconf_msr[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- VARIA ------------\n");
+ msr = rdmsr(0x51300010);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
+
+ msr = rdmsr(0x51400015);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
+
+ printk_debug("---------- DIVIL IRQ ------------\n");
+ msr = rdmsr(MDD_IRQM_YLOW);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
+ msr = rdmsr(MDD_IRQM_YHIGH);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
+ msr = rdmsr(MDD_IRQM_ZLOW);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
+ msr = rdmsr(MDD_IRQM_ZHIGH);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
+
+
+ printk_debug("---------- PCI ------------\n");
+
+ for(i = 0; pci_msr[i] != GL_END; i++) {
+ msr = rdmsr(pci_msr[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- LPC/UART DMA ------------\n");
+
+ for(i = 0; dma_msr[i] != GL_END; i++) {
+ msr = rdmsr(dma_msr[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- CS5536 ------------\n");
+
+ for(i = 0; cs5536_msr[i] != GL_END; i++) {
+ msr = rdmsr(cs5536_msr[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
+ }
+
+ iol = inl(GPIOL_INPUT_ENABLE);
+ printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_ENABLE, iol);
+ iol = inl(GPIOL_EVENTS_ENABLE);
+ printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_EVENTS_ENABLE, iol);
+ iol = inl(GPIOL_INPUT_INVERT_ENABLE);
+ printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_INVERT_ENABLE, iol);
+ iol = inl(GPIO_MAPPER_X);
+ printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_MAPPER_X, iol);
+
+}
static void enable_L2_cache(void) {
msr_t msr;
@@ -306,19 +396,75 @@ static void enable_L2_cache(void) {
printk_debug("L2 cache enabled\n");
}
-
static void northbridge_init(device_t dev)
{
+ //msr_t msr;
struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
- printk_debug("northbridge: %s()\n", __FUNCTION__);
+
+ printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
enable_shadow(dev);
- irq_init_steering(dev, nb->irqmap);
+ /*
+ * Swiss cheese
+ */
+ //msr = rdmsr(MSR_GLIU0_SHADOW);
+
+ //msr.hi |= 0x3;
+ //msr.lo |= 0x30000;
+
+// not needed (also irq steering is in legacy vsm so it wouldnt work either)
+// irq_init_steering(dev, nb->irqmap);
+
+ //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
+ //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+}
+
+void northbridge_set_resources(struct device *dev)
+{
+ struct resource *resource, *last;
+ unsigned link;
+ uint8_t line;
+
+ last = &dev->resource[dev->resources];
+
+ for(resource = &dev->resource[0]; resource < last; resource++)
+ {
+
+ // andrei: do not change the base address, it will make the VSA virtual registers unusable
+ //pci_set_resource(dev, resource);
+ // FIXME: static allocation may conflict with dynamic mappings!
+ }
+
+ for(link = 0; link < dev->links; link++) {
+ struct bus *bus;
+ bus = &dev->link[link];
+ if (bus->children) {
+ printk_debug("my_dev_set_resources: assign_resources %d\n", bus);
+ assign_resources(bus);
+ }
+ }
+
+ /* set a default latency timer */
+ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
+
+ /* set a default secondary latency timer */
+ if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+ pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
+ }
+
+ /* zero the irq settings */
+ line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+ if (line) {
+ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
+ }
+
+ /* set the cache line size, so far 64 bytes is good for everyone */
+ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
}
static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
+ .set_resources = northbridge_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = 0,
@@ -328,16 +474,14 @@ static struct device_operations northbridge_operations = {
static struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_LX,
+ .device = PCI_DEVICE_ID_AMD_LXBRIDGE,
};
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
-
- printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
+ printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
@@ -355,96 +499,64 @@ static void ram_resource(device_t dev, unsigned long index,
{
struct resource *resource;
- if (!sizek) {
- return;
- }
+ if (!sizek) return;
+
resource = new_resource(dev, index);
resource->base = ((resource_t)basek) << 10;
resource->size = ((resource_t)sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+ resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
+static void pci_domain_set_resources(device_t dev)
{
- struct resource **best_p = gp;
- struct resource *best;
- best = *best_p;
- if (!best || (best->base > new->base)) {
- best = new;
- }
- *best_p = best;
-}
+ int idx;
+ device_t mc_dev;
-#if 0
-static uint32_t find_pci_tolm(struct bus *bus)
-{
- struct resource *min;
- uint32_t tolm;
- min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
- tolm = 0xffffffffUL;
- if (min && tolm > min->base) {
- tolm = min->base;
+ printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
+
+ mc_dev = dev->link[0].children;
+ if (mc_dev)
+ {
+ /* Report the memory regions */
+ idx = 10;
+ ram_resource(dev, idx++, 0, 640);
+ ram_resource(dev, idx++, 1024, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE - 1024);
}
- return tolm;
+
+ assign_resources(&dev->link[0]);
}
-#endif
-#define FRAMEBUFFERK 4096
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_enable(device_t dev)
{
-#if 0
- device_t mc_dev;
- uint32_t pci_tolm;
+ struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
- pci_tolm = find_pci_tolm(&dev->link[0]);
- mc_dev = dev->link[0].children;
- if (mc_dev) {
- unsigned int tomk, tolmk;
- unsigned int ramreg = 0;
- int i, idx;
- unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
- unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
-
- for(i=0; i<0x20; i+= 0x10) {
- unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
- unsigned int mem_config = *mcreg;
-
- if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
- continue;
- ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
- }
-
- tomk = ramreg << 10;
+ printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
- /* Sort out the framebuffer size */
- tomk -= FRAMEBUFFERK;
- *bcdramtop = ((tomk << 10) - 1);
- *mcgbaseadd = (tomk >> 9);
+ // do this here for now -- this chip really breaks our device model
+ enable_L2_cache();
+ northbridge_init_early();
+ cpubug();
+ chipsetinit(nb);
+ setup_lx();
+ setup_realmode_idt();
- printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
- printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+ printk_debug("Before VSA:\n");
+ print_conf();
- printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+ do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;)
+
+ printk_debug("After VSA:\n");
+ print_conf();
- /* Compute the top of Low memory */
- tolmk = pci_tolm >> 10;
- if (tolmk >= tomk) {
- /* The PCI hole does does not overlap the memory.
- */
- tolmk = tomk;
- }
- /* Report the memory regions */
- idx = 10;
- ram_resource(dev, idx++, 0, tolmk);
- }
-#endif
- assign_resources(&dev->link[0]);
+ graphics_init();
+ pci_set_method(dev);
}
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
+ printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
+
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
@@ -453,12 +565,14 @@ static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
- .init = 0,
.scan_bus = pci_domain_scan_bus,
+ .enable = pci_domain_enable,
};
static void cpu_bus_init(device_t dev)
{
+ printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
+
initialize_cpus(&dev->link[0]);
}
@@ -474,38 +588,16 @@ static struct device_operations cpu_bus_ops = {
.scan_bus = 0,
};
-void chipsetInit (void);
-
static void enable_dev(struct device *dev)
{
- printk_debug("lx north: enable_dev\n");
- void northbridgeinit(void);
- void chipsetinit(struct northbridge_amd_lx_config *nb);
- void setup_realmode_idt(void);
- void do_vsmbios(void);
+ printk_spew(">> Entering northbridge.c: %s with path %d\n",
+ __FUNCTION__, dev->path.type);
+
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
- struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
- extern void cpubug(void);
- printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
- /* cpubug MUST be called before setup_lx(), so we force the issue here */
- enable_L2_cache();
- northbridgeinit();
- /* cpubug(); GX3*/
- chipsetinit(nb);
- setup_lx();
- /* do this here for now -- this chip really breaks our device model */
- setup_realmode_idt();
- do_vsmbios();
- graphics_init();
+ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN)
dev->ops = &pci_domain_ops;
- pci_set_method(dev);
- ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE);
- } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
- printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
+ else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER)
dev->ops = &cpu_bus_ops;
- }
- printk_debug("lx north: end enable_dev\n");
}
struct chip_operations northbridge_amd_lx_ops = {
diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h
index 391fbf3177..837e2a3ae5 100644
--- a/src/northbridge/amd/lx/northbridge.h
+++ b/src/northbridge/amd/lx/northbridge.h
@@ -2,5 +2,6 @@
#define NORTHBRIDGE_AMD_LX_H
extern unsigned int lx_scan_root_bus(device_t root, unsigned int max);
+int sizeram(void);
#endif /* NORTHBRIDGE_AMD_LX_H */
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 08b8816610..21d2736bcb 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -26,7 +26,6 @@ struct gliutable gliu0table[] = {
{.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/
{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
- {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
{.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
@@ -38,10 +37,8 @@ struct gliutable gliu1table[] = {
{.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc*/
{.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode)*/
{.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
- {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
{.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
- {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/
{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
@@ -102,9 +99,6 @@ struct msrinit GeodeLinkPriorityTable [] = {
{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/
};
-/* do we have dmi or not? assume NO per AMD */
-int havedmi = 0;
-
static void
writeglmsr(struct gliutable *gl){
msr_t msr;
@@ -112,10 +106,10 @@ writeglmsr(struct gliutable *gl){
msr.lo = gl->lo;
msr.hi = gl->hi;
wrmsr(gl->desc_name, msr); // MSR - see table above
- printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+ // printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); //GX3
/* they do this, so we do this */
msr = rdmsr(gl->desc_name);
- printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+ // printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo); // GX3
}
static void
@@ -144,97 +138,43 @@ SysmemInit(struct gliutable *gl)
/*
* Figure out how much RAM is in the machine and alocate all to the
- * system. We will adjust for SMM and DMM now and Frame Buffer later.
+ * system. We will adjust for SMM now and Frame Buffer later.
*/
sizembytes = sizeram();
printk_debug("%s: enable for %dm bytes\n", __FUNCTION__, sizembytes);
sizebytes = sizembytes << 20;
- sizebytes -= SMM_SIZE*1024 +1;
+ sizebytes -= ((SMM_SIZE)<<10);
+ printk_debug("usable RAM: %d bytes\n", sizebytes);
- if (havedmi)
- sizebytes -= DMM_SIZE * 1024 + 1;
-
- sizebytes -= 1;
msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
/* set up sizebytes to fit into msr.lo */
sizebytes <<= 8; /* what? well, we want bits 23:12 in bits 31:20. */
sizebytes &= 0xfff00000;
sizebytes |= 0x100;
msr.lo = sizebytes;
- wrmsr(gl->desc_name, msr); // MSR - see table above
- msr = rdmsr(gl->desc_name);
- printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__,
- gl->desc_name, msr.hi, msr.lo);
-
-}
-static void
-DMMGL0Init(struct gliutable *gl) {
- msr_t msr;
- int sizebytes = sizeram()<<20;
- long offset;
-
- if (! havedmi)
- return;
-
- printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes);
- sizebytes -= DMM_SIZE*1024;
- offset = sizebytes - DMM_OFFSET;
- printk_debug("%s: offset is 0x%08x\n", __FUNCTION__, offset);
- offset >>= 12;
- msr.hi = (gl->hi) | (offset << 8);
- /* I don't think this is needed */
- msr.hi &= 0xffffff00;
- msr.hi |= (DMM_OFFSET >> 24);
- msr.lo = DMM_OFFSET << 8;
- msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
-
- wrmsr(gl->desc_name, msr); // MSR - See table above
+ wrmsr(gl->desc_name, msr); // MSR - see table above
msr = rdmsr(gl->desc_name);
- printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
-
+ /* printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__,
+ gl->desc_name, msr.hi, msr.lo); */ // GX3
}
-static void
-DMMGL1Init(struct gliutable *gl) {
- msr_t msr;
-
- if (! havedmi)
- return;
-
- printk_debug("%s:\n", __FUNCTION__ );
- msr.hi = gl->hi;
- /* I don't think this is needed */
- msr.hi &= 0xffffff00;
- msr.hi |= (DMM_OFFSET >> 24);
- msr.lo = DMM_OFFSET << 8;
- /* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
- printk_err("%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __FUNCTION__);
- msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
-
- wrmsr(gl->desc_name, msr); // MSR - See table above
- msr = rdmsr(gl->desc_name);
- printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
-}
static void
SMMGL0Init(struct gliutable *gl) {
msr_t msr;
int sizebytes = sizeram()<<20;
long offset;
- sizebytes -= SMM_SIZE*1024;
-
- if (havedmi)
- sizebytes -= DMM_SIZE * 1024;
+ sizebytes -= ((SMM_SIZE)<<10);
printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes);
offset = sizebytes - SMM_OFFSET;
+ offset = (offset >> 12) & 0x000fffff;
printk_debug("%s: offset is 0x%08x\n", __FUNCTION__, offset);
- offset >>= 12;
- msr.hi = offset << 8;
+ msr.hi = offset << 8 | MSR_MC;
msr.hi |= SMM_OFFSET>>24;
msr.lo = SMM_OFFSET << 8;
@@ -277,14 +217,6 @@ GLIUInit(struct gliutable *gl){
SysmemInit(gl);
break;
- case BMO_DMM: /* check for a DMM entry*/
- DMMGL0Init(gl);
- break;
-
- case BM_DMM : /* check for a DMM entry*/
- DMMGL1Init(gl);
- break;
-
case BMO_SMM : /* check for a SMM entry*/
SMMGL0Init(gl);
break;
@@ -317,7 +249,8 @@ static void GLPCIInit(void){
struct gliutable *gl = 0;
int i;
msr_t msr;
- int msrnum;
+ int msrnum, enable_preempt, enable_cpu_override;
+ int nic_grants_control, enable_bus_parking;
/* */
/* R0 - GLPCI settings for Conventional Memory space.*/
@@ -415,12 +348,20 @@ static void GLPCIInit(void){
/* */
/* 5535 NB Init*/
/* */
+
+ /* Arbiter setup */
+
+ enable_preempt = GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET | GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET;
+ enable_cpu_override = GLPCI_ARB_LOWER_COV_SET;
+ enable_bus_parking = GLPCI_ARB_LOWER_PARK_SET;
+ nic_grants_control = (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 << GLPCI_ARB_UPPER_H2_SHIFT );
+
msrnum = GLPCI_ARB;
msr = rdmsr(msrnum);
- msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
- msr.lo |= GLPCI_ARB_LOWER_IIE_SET;
- wrmsr(msrnum, msr);
+ msr.hi |= nic_grants_control;
+ msr.lo |= enable_cpu_override | enable_preempt | enable_bus_parking;
+ wrmsr(msrnum, msr);
msrnum = GLPCI_CTRL;
msr = rdmsr(msrnum);
@@ -507,11 +448,11 @@ performance:
for(i = 0; gating->msrnum != 0xffffffff; i++) {
msr = rdmsr(gating->msrnum);
- printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, gating->msrnum, msr.hi, msr.lo);
+ //printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, gating->msrnum, msr.hi, msr.lo); //GX3
msr.hi |= gating->msr.hi;
msr.lo |= gating->msr.lo;
- printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__,
- gating->msrnum, msr.hi, msr.lo);
+ /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__,
+ gating->msrnum, msr.hi, msr.lo); */ // GX3
wrmsr(gating->msrnum, msr); // MSR - See the table above
gating +=1;
}
@@ -526,12 +467,12 @@ GeodeLinkPriority(void){
for(i = 0; prio->msrnum != 0xffffffff; i++) {
msr = rdmsr(prio->msrnum);
- printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, prio->msrnum, msr.hi, msr.lo);
+ // printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, prio->msrnum, msr.hi, msr.lo); // GX3
msr.hi |= prio->msr.hi;
msr.lo &= ~0xfff;
msr.lo |= prio->msr.lo;
- printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__,
- prio->msrnum, msr.hi, msr.lo);
+ /* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__,
+ prio->msrnum, msr.hi, msr.lo); */ // GX3
wrmsr(prio->msrnum, msr); // MSR - See the table above
prio +=1;
}
@@ -563,7 +504,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
// ok this is whacky bit translation time.
int bit;
uint8_t shadowByte;
- msr_t msr;
+ msr_t msr = {0, 0};
shadowByte = (uint8_t) (shadowLo >> 16);
// load up D000 settings in edx.
@@ -674,6 +615,7 @@ shadowRom(void)
uint64_t shadowSettings = getShadow();
shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes
shadowSettings |= (uint64_t) 0x00000000F0000000ULL; // Enable reads for F0000-FFFFF
+ shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable rw for C0000-CFFFF
setShadow(shadowSettings);
}
@@ -704,7 +646,7 @@ RCONFInit(void)
int i;
msr_t msr;
uint8_t SysMemCacheProp;
- uint8_t RegionProp;
+ //uint8_t RegionProp;
/* Locate SYSMEM entry in GLIU0table */
for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
@@ -722,6 +664,8 @@ RCONFInit(void)
/* found the descriptor... get its contents */
msr = rdmsr(gl->desc_name);
+ printk_debug("SYSDESC: 0x%08X:0x%08X\n",msr.hi,msr.lo);
+
/* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the
* top 8 bits go into 0-7 of edx.
*/
@@ -729,6 +673,8 @@ RCONFInit(void)
msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8
+ printk_debug("RCONF LO: 0x%08X\n",msr.lo);
+
// Set Default SYSMEM region properties
msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // 8 (or ~8)
@@ -752,12 +698,13 @@ RCONFInit(void)
msr = rdmsr(CPU_RCONF_BYPASS);
msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
wrmsr(CPU_RCONF_BYPASS, msr);
+
+ printk_debug("CPU_RCONF_SMM (180E) 0x%08x : 0x%08x\n", msr.hi, msr.lo);
}
-/* ***************************************************************************/
-/* **/
-/* * northBridgeInit*/
+/****************************************************************************/
+/* * northbridge_init_early */
/* **/
/* * Core Logic initialization: Host bridge*/
/* **/
@@ -767,8 +714,7 @@ RCONFInit(void)
/* **/
/* ***************************************************************************/
-void
-northbridgeinit(void)
+void northbridge_init_early(void)
{
msr_t msr;
int i;
@@ -791,6 +737,8 @@ northbridgeinit(void)
// makes sure all INVD instructions are treated as WBINVD. We do this
// because we've found some programs which require this behavior.
// That subset of cacheInit() is implemented here:
+
+ /* GX3 OK */
msr = rdmsr(CPU_DM_CONFIG0);
msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
wrmsr(CPU_DM_CONFIG0, msr);
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index be92e9b90d..13e21be8de 100644
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -6,7 +6,7 @@ static void pll_reset(void)
msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
- print_debug("MSR GLCP_SYS_RSTPLL (");
+ print_debug("_MSR GLCP_SYS_RSTPLL (");
print_debug_hex32(GLCP_SYS_RSTPLL);
print_debug(") value is: ");
print_debug_hex32(msrGlcpSysRstpll.hi);
@@ -19,60 +19,18 @@ static void pll_reset(void)
// If the "we've already been here" flag is set, don't reconfigure the pll
if ( !(msrGlcpSysRstpll.lo) )
{ // we haven't configured the PLL; do it now
+ print_debug("CONFIGURING PLL");
+
POST_CODE(0x77);
- /*
- * 64 - 32 | 31-0
- *
- * (03FB)
- * 0000 0011 1111 1011 | 1000 0000 1101 1110 0000 0000 1000 0001
- *
- * (039C)
- * 0000 0011 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001
- *
- * (029C)
- * 0000 0010 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001
- *
- * (02CB)
- * 0000 0010 1100 1011 | 1000 0000 1101 1110 0000 0000 1000 0001
- *
- * 00101 1 00101 1 | 100000 0 0 11011110 0000 0000 1000 0001
- * GLIUMULT GLIUDIV COREMULT COREDIV | SWFLAGS (RO) (RO) HOLD_COUNT
- */
-
- /* ### 02CB ###
- * GLIUMULT = 6
- * GLIUDIV = 2
- * COREMULT = 6
- * COREDIV = 2
- *
- * ### 03FB ###
- * GLIUMULT = 8
- * GLIUDIV = 2
- * COREMULT = 30
- * COREDIV = 2
- *
- * ### 039C ### bad... why?
- * GLIUMULT = 8
- * GLIUDIV = 0
- * COREMULT = 15
- * COREDIV = 0
- *
- * ### 029C ### good...
- * GLIUMULT = 6
- * GLIUDIV = 0
- * COREMULT = 15
- * COREDIV = 0
- *
- * CLOCK = 33 MHz
- *
- */
+ // HARDCODED VALUES MOVED BACK TO auto.c AS THEY HAVE TO BE BOARD-SPECIFIC
+ // (this file is included from there)
/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
- msrGlcpSysRstpll.hi = 0x0000029C;
+ msrGlcpSysRstpll.hi = PLLMSRhi;
/* Hold Count - how long we will sit in reset */
- msrGlcpSysRstpll.lo = 0x00DE0000;
+ msrGlcpSysRstpll.lo = PLLMSRlo;
/* Use SWFLAGS to remember: "we've already been here" */
msrGlcpSysRstpll.lo |= 0x80000000;
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 3aeea646c1..f1ae87d69e 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -18,27 +18,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
* — MSR 20000019h
*/
- // This is done by sdram_set_spd_registers()
- /*WR_MSR MC_CF07_DATA, DIMMCONFIG, 0x05000040
-
- ;WR_MSR MC_CF07_DATA, DIMMCONFIG, 0x00000040 ; MSR 20000018h except REF_INT bits [23:8]. REF_STAG value from DOCS*/
-
- /*
- * 0x18000100 : 0x696332A3
- *
- * 63 - 32 | 31 15 0
- * xxxxxxx | 0110 1001 0110 0011 0011 0010 1010 0011
- *
- * 30:28 CAS latency
- *
- * 010 - 2.0
- * 110 - 2.5
- *
- */
-
- msr.hi = 0x18000100;
- msr.lo = 0x696332A3;
- wrmsr(MC_CF8F_DATA, msr);
+ // This is done by sdram_set_spd_registers() that is called by sdram/generic_sdram.c just before this
+ // sdram_set_spd_registers is responsible for reading ram settings from spd rom and configuring sdram conrtoller
+ // Here follows generic sdram initialization procedure.
/* 2) Initialize the following GLMC registers:
* — MSR 2000001Ah[15:8] = C8h
@@ -48,6 +30,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo = 0x130AD101;
wrmsr(MC_CF1017_DATA, msr);
+ //ok
msr.hi = 0x00000000;
msr.lo = 0x00000001;
wrmsr(MC_GLD_MSR_PM, msr);
@@ -55,41 +38,37 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 3) Release MASK_CKE[1:0] (MSR 2000001Dh[9:8] = 11) */
msr.hi = 0x00000000;
- msr.lo = 0x00001000;
+ msr.lo = 0x00000000;
wrmsr(MC_CFCLK_DBUG, msr);
- //print_debug("sdram_enable step 3\r\n");
+ // reset memory controller
+ msr = rdmsr(MC_CF07_DATA);
+ msr.lo |= 0x00000002;
+ wrmsr(MC_CF07_DATA, msr);
+ msr.lo &= 0xFFFFFFFD;
+ wrmsr(MC_CF07_DATA, msr);
/* 4. set and clear REF_TST 16 times, more shouldn't hurt
* why this is before EMRS and MRS ? */
for (i = 0; i < 19; i++) {
msr = rdmsr(MC_CF07_DATA);
- msr.lo |= (0x01 << 3);
+ msr.lo |= 0x00000008;
wrmsr(MC_CF07_DATA, msr);
- msr.lo &= ~(0x01 << 3);
+ msr.lo &= 0xFFFFFFF7;
wrmsr(MC_CF07_DATA, msr);
}
/* 5) Initialize REF_INT (MSR 20000018h[23:8]) to set refresh interval. */
- msr.lo |= 0x2B00;
+ msr.lo |= 0x3A00;
wrmsr(MC_CF07_DATA, msr);
-
-
- /* set refresh staggering to 4 SDRAM clocks */
- msr = rdmsr(0x20000018);
- msr.lo &= ~(0x03 << 6);
- msr.lo |= (0x00 << 6);
- wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 5\r\n");
-
-
/* 6) Perform load-mode with MSR_BA = 01 (MSR 200000018h[29:28] = 01)
* to initialize DIMM Extended Mode register.
* Load-mode is performed by setting/clearing PROG_DRAM (MSR 200000018h[0]).
*/
+// eeldus et bit29 = 0, mida ta praegu ka on
msr.lo |= ((0x01 << 28) | 0x01);
wrmsr(MC_CF07_DATA, msr);
@@ -100,13 +79,20 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
* it is documented in LX datasheet */
/* load Mode Register by set and clear PROG_DRAM */
+// eeldus et bit27:28=00, mida nad ka on
msr = rdmsr(MC_CF07_DATA);
msr.lo |= ((0x01 << 27) | 0x01);
wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~((0x01 << 27) | 0x01);
wrmsr(MC_CF07_DATA, msr);
- //print_debug("sdram_enable step 7\r\n");
+ //Delay
+ i=inb(0x61);
+ while (i==inb(0x61));
+ i=inb(0x61);
+ while (i==inb(0x61));
+ i=inb(0x61);
+ while (i==inb(0x61));
/* 8. load Mode Register by set and clear PROG_DRAM */
msr = rdmsr(MC_CF07_DATA);
@@ -114,25 +100,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~0x01;
wrmsr(MC_CF07_DATA, msr);
- //print_debug("sdram_enable step 8\r\n");
/* wait 200 SDCLKs */
for (i = 0; i < 200; i++)
outb(0xaa, 0x80);
- /* load RDSYNC */
- /*msr = rdmsr(0x2000001f);
- msr.hi = 0x000ff310;
- msr.lo = 0x00000000;
- wrmsr(0x2000001f, msr);*/
-
- /* set delay control */
- msr = rdmsr(0x4c00000f);
- msr.hi = 0x830d415a;
- msr.lo = 0x8ea0ad6a;
- wrmsr(0x4c00000f, msr);
-
-
print_debug("DRAM controller init done.\r\n");
/* Fixes from Jordan Crouse of AMD. */
diff --git a/targets/artecgroup/dbe61/Config.lb b/targets/artecgroup/dbe61/Config.lb
index 1bbe5f1f98..b36693a3df 100644
--- a/targets/artecgroup/dbe61/Config.lb
+++ b/targets/artecgroup/dbe61/Config.lb
@@ -3,18 +3,25 @@
target dbe61
mainboard artecgroup/dbe61
-# leave 64k for vsa
option CONFIG_COMPRESSED_ROM_STREAM=0
-option ROM_SIZE=1024*256-64*1024
-option FALLBACK_SIZE=ROM_SIZE
+
+## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
+## (normal AND fallback images and payloads).
+## leave 64k for vsa and 32K for video ROM
+option ROM_SIZE = 1024*256 - 64*1024 - 32 * 1024
+
+## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
+## not including any payload.
+option ROM_IMAGE_SIZE=64*1024
+
+option FALLBACK_SIZE = ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 11
option MAXIMUM_CONSOLE_LOGLEVEL = 11
romimage "fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_IMAGE_SIZE=32*1024
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
- payload /tmp/rtl8139--filo.zelf
+ payload /tmp/filo.elf
end
buildrom ./linuxbios.rom ROM_SIZE "fallback"
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 23:14:00 +0000