diff options
10 files changed, 360 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1f3b3d5b53..7686d6c1aa 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -113,6 +113,7 @@ config DRIVER_TPM_I2C_BUS default 0x1 if BOARD_GOOGLE_BRASK default 0x1 if BOARD_GOOGLE_PRIMUS default 0x3 if BOARD_GOOGLE_PRIMUS4ES + default 0x1 if BOARD_GOOGLE_GHOST4ADL default 0x1 if BOARD_GOOGLE_GIMBLE default 0x3 if BOARD_GOOGLE_GIMBLE4ES default 0x1 if BOARD_GOOGLE_REDRIX @@ -172,6 +173,7 @@ config MAINBOARD_PART_NUMBER default "Brask" if BOARD_GOOGLE_BRASK default "Primus" if BOARD_GOOGLE_PRIMUS default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES + default "Ghost4ADL" if BOARD_GOOGLE_GHOST4ADL default "Gimble" if BOARD_GOOGLE_GIMBLE default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES default "Redrix" if BOARD_GOOGLE_REDRIX @@ -204,6 +206,7 @@ config VARIANT_DIR default "brask" if BOARD_GOOGLE_BRASK default "primus" if BOARD_GOOGLE_PRIMUS default "primus4es" if BOARD_GOOGLE_PRIMUS4ES + default "ghost4adl" if BOARD_GOOGLE_GHOST4ADL default "gimble" if BOARD_GOOGLE_GIMBLE default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES default "redrix" if BOARD_GOOGLE_REDRIX diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 70ee5a84dd..015269791c 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -57,6 +57,10 @@ config BOARD_GOOGLE_FELWINTER select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9755 +config BOARD_GOOGLE_GHOST4ADL + bool "-> Ghost4ADL" + select BOARD_GOOGLE_BASEBOARD_BRYA + config BOARD_GOOGLE_GIMBLE bool "-> Gimble" select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/ghost4adl/Makefile.inc b/src/mainboard/google/brya/variants/ghost4adl/Makefile.inc new file mode 100644 index 0000000000..c44e4f0364 --- /dev/null +++ b/src/mainboard/google/brya/variants/ghost4adl/Makefile.inc @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/ghost4adl/include/variant/ec.h b/src/mainboard/google/brya/variants/ghost4adl/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/ghost4adl/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/ghost4adl/include/variant/gpio.h b/src/mainboard/google/brya/variants/ghost4adl/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/ghost4adl/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/ghost4adl/memory.c b/src/mainboard/google/brya/variants/ghost4adl/memory.c new file mode 100644 index 0000000000..4503a1f587 --- /dev/null +++ b/src/mainboard/google/brya/variants/ghost4adl/memory.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + /* + * DQ byte map + * + * To calculate from schematics, reference + * ADL_LP5_DqMapCpu2Dram sheet of this spreadsheet: + * https://cdrdv2.intel.com/v1/dl/getContent/573387 + */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 5, 0, 4, 1, 2, 6, 7, 3, }, + .dq1 = { 9, 12, 8, 13, 15, 10, 14, 11, }, + }, + .ddr1 = { + .dq0 = { 9, 10, 11, 8, 13, 15, 14, 12, }, + .dq1 = { 0, 3, 1, 2, 7, 5, 6, 4, }, + }, + .ddr2 = { + .dq0 = { 9, 13, 8, 12, 15, 10, 14, 11, }, + .dq1 = { 7, 6, 4, 5, 0, 3, 1, 2, }, + }, + .ddr3 = { + .dq0 = { 3, 7, 2, 6, 4, 1, 5, 0, }, + .dq1 = { 12, 14, 15, 13, 11, 10, 8, 9, }, + }, + .ddr4 = { + .dq0 = { 15, 14, 12, 13, 10, 9, 8, 11, }, + .dq1 = { 7, 5, 4, 6, 2, 0, 1, 3, }, + }, + .ddr5 = { + .dq0 = { 9, 10, 11, 8, 12, 15, 13, 14, }, + .dq1 = { 3, 7, 2, 6, 0, 4, 5, 1, }, + }, + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 5, 6, 4, }, + .dq1 = { 12, 13, 10, 9, 14, 11, 8, 15, }, + }, + .ddr7 = { + .dq0 = { 11, 8, 10, 9, 12, 14, 13, 15, }, + .dq1 = { 1, 7, 0, 2, 5, 3, 4, 6, }, + }, + }, + + /* + * DQS CPU<>DRAM map + * + * To calculate from schematics, reference + * MTL_RPL_ADL_LP5_DqsMapCpu2Dram sheet of this spreadsheet: + * https://cdrdv2.intel.com/v1/dl/getContent/573387 + */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + /* Enable Early Command Training */ + .ect = true, + + .UserBd = BOARD_TYPE_MOBILE, + + .lp5x_config = { + /* + * CA and CS signals are in descending order. + * + * Reference the MTL_RPL_ADL_LP5_CccConfig sheet of + * this spreadsheet for instructions: + * https://cdrdv2.intel.com/v1/dl/getContent/573387 + */ + .ccc_config = 0xff, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * - MEM_STRAP_0: GPP_E3 + * - MEM_STRAP_1: GPP_E2 + * - MEM_STRAP_2: GPP_E1 + * - MEM_STRAP_3: GPP_E7 + * + * MEM_STRAP_0 is LSB, and MEM_STRAP_3 is MSB. + */ + gpio_t spd_gpios[] = { + GPP_E3, + GPP_E2, + GPP_E1, + GPP_E7, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL is GPP_B3 */ + return gpio_get(GPP_B3); +} diff --git a/src/mainboard/google/brya/variants/ghost4adl/memory/Makefile.inc b/src/mainboard/google/brya/variants/ghost4adl/memory/Makefile.inc new file mode 100644 index 0000000000..9d5733da7f --- /dev/null +++ b/src/mainboard/google/brya/variants/ghost4adl/memory/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost4adl/memory src/mainboard/google/brya/variants/ghost4adl/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = H58G56AK6BX069 diff --git a/src/mainboard/google/brya/variants/ghost4adl/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/ghost4adl/memory/dram_id.generated.txt new file mode 100644 index 0000000000..0dd1f38b55 --- /dev/null +++ b/src/mainboard/google/brya/variants/ghost4adl/memory/dram_id.generated.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost4adl/memory src/mainboard/google/brya/variants/ghost4adl/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H9JCNNNBK3MLYR-N6E 0 (0000) +H58G56AK6BX069 1 (0001) diff --git a/src/mainboard/google/brya/variants/ghost4adl/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/ghost4adl/memory/mem_parts_used.txt new file mode 100644 index 0000000000..0612b5e4e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/ghost4adl/memory/mem_parts_used.txt @@ -0,0 +1,13 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +H9JCNNNBK3MLYR-N6E +H58G56AK6BX069 diff --git a/src/mainboard/google/brya/variants/ghost4adl/overridetree.cb b/src/mainboard/google/brya/variants/ghost4adl/overridetree.cb new file mode 100644 index 0000000000..491d793ba3 --- /dev/null +++ b/src/mainboard/google/brya/variants/ghost4adl/overridetree.cb @@ -0,0 +1,188 @@ +chip soc/intel/alderlake + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | FPMCU | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C2 | Misc (Cam, Display, LED) | + #| I2C3 | Touchscreen | + #| I2C4 | NC | + #| I2C5 | Touchpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_lcnt = 45, + .scl_hcnt = 33, + .sda_hold = 20, + }, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_STANDARD, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[2] = { + .speed = I2C_SPEED_STANDARD, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_STANDARD, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_STANDARD, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + + # I2C Port Config + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C7] = PchSerialIoDisabled, + }" + device domain 0 on + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 1 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 1, + .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tbt_pcie_rp3 on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 off end + device ref pcie_rp9 on + # Enable NVMe on PCIE 9-12 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + # Replicate Brya, except we have 2 ports instead of 3. + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + # USB C0 is on RIGHT panel, LEFT side (when user is facing front) + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + # USB C1 is on the RIGHT panel, RIGHT side (when user is facing front) + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + end + end + end + end +end |