diff options
23 files changed, 42 insertions, 55 deletions
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 75f1f439b8..38066c15a2 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -309,8 +309,9 @@ struct postcar_frame { }; /* - * Initialize postcar_frame object allocating stack size in cbmem - * with the provided size. Returns 0 on success, < 0 on error. + * Initialize postcar_frame object allocating stack from cbmem, + * with stack_size == 0, default 4 KiB is allocated. + * Returns 0 on success, < 0 on error. */ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 732b767bf6..35e139fe1c 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -48,6 +48,15 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size) { void *stack; + /* + * Use default postcar stack size of 4 KiB. This value should + * not be decreased, because if mainboards use vboot, 1 KiB will + * not be enough anymore. + */ + + if (stack_size == 0) + stack_size = 4 * KiB; + stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, stack_size); if (stack == NULL) { printk(BIOS_ERR, "Couldn't add %zd byte stack in cbmem.\n", diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 3cbdf44c1d..47b9976786 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -38,8 +38,6 @@ #include <cpu/intel/romstage.h> #include "haswell.h" -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -48,7 +46,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 84ea7d153c..1e89a8eb89 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -25,8 +25,6 @@ #include <program_loading.h> #include <timestamp.h> -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -35,7 +33,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index e1d4f62708..6b1883ccbd 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> #include <stdint.h> #include <cbmem.h> #include <console/console.h> @@ -31,11 +32,7 @@ asmlinkage void car_stage_entry(void) timestamp_add_now(TS_START_ROMSTAGE); - /** - * The LZMA decoder needs about 4 KiB stack. - * Leave 1 KiB stack for general postcar code. - */ - if (postcar_frame_init(&pcf, 5 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /** diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 3e0870ffec..e409ad1e5f 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> #include <stdint.h> #include <cbmem.h> #include <console/console.h> @@ -32,11 +33,7 @@ asmlinkage void car_stage_entry(void) timestamp_add_now(TS_START_ROMSTAGE); - /** - * The LZMA decoder needs about 4 KiB stack. - * Leave 1 KiB stack for general postcar code. - */ - if (postcar_frame_init(&pcf, 5 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /** diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index f7a08bc28d..d45006566e 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -35,8 +35,6 @@ void *cbmem_top(void) return (void *)tolm; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -45,7 +43,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c1307c48f5..c6140824f0 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -123,8 +123,6 @@ void *cbmem_top(void) return (void *) top_of_ram; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -133,7 +131,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index 09a3b03272..495ca8682a 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -15,6 +15,7 @@ #define __SIMPLE_DEVICE__ +#include <arch/cpu.h> #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> @@ -67,8 +68,6 @@ void *cbmem_top(void) return (void *)tom; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -77,7 +76,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 752c8f901c..525a5b9c0e 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -88,8 +88,6 @@ u32 decode_igd_memory_size(const u32 gms) return ggc2uma[gms] << 10; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -98,7 +96,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index e32190f519..ba3761065b 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -43,8 +43,6 @@ void *cbmem_top(void) return (void *) smm_region_start(); } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -53,7 +51,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index a789956ea3..d1b43aa42d 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -16,6 +16,7 @@ #define __SIMPLE_DEVICE__ +#include <arch/cpu.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> @@ -137,8 +138,6 @@ void *cbmem_top(void) } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -147,7 +146,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 5cda8a33fe..343ae62711 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -43,8 +43,6 @@ void *cbmem_top(void) return (void *) smm_region_start(); } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -53,7 +51,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 371496985f..be9c10f001 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -134,8 +134,6 @@ void *cbmem_top(void) return (void *) top_of_ram; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -144,7 +142,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 12ee2a8aca..000d100fa3 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -153,7 +153,7 @@ asmlinkage void car_stage_entry(void) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); post_code(0x44); - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 5bf501dcfa..5d65a0029e 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -240,7 +240,7 @@ asmlinkage void car_stage_entry(void) else printk(BIOS_ERR, "Failed to determine variable data\n"); - if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); mainboard_save_dimm_info(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 5621dd16eb..7e2bb64ba6 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -238,8 +238,6 @@ void romstage_common(struct romstage_params *params) romstage_handoff_init(prev_sleep_state == ACPI_S3); } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void platform_enter_postcar(void) @@ -247,7 +245,7 @@ static void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 9bca716447..9c86809368 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,6 +16,7 @@ #include <stddef.h> #include <stdint.h> #include <arch/cbfs.h> +#include <arch/cpu.h> #include <bootblock_common.h> #include <bootmode.h> #include <cbmem.h> @@ -34,8 +35,6 @@ #include <soc/romstage.h> #include <soc/spi.h> -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -44,7 +43,7 @@ void platform_enter_postcar(void) struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 9dadb2d14e..94b9899422 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> @@ -146,7 +147,7 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 4477c927e9..6d8eaab9b1 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> #include <arch/io.h> #include <cbmem.h> #include <cf9_reset.h> @@ -161,7 +162,7 @@ asmlinkage void car_stage_entry(void) display_fsp_smbios_memory_info_hob(); #endif - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index b0eeb2e959..514e5e8925 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> @@ -131,7 +132,7 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 5ebbacbd2a..a8bd26eceb 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> #include <arch/symbols.h> #include <console/console.h> #include <cbmem.h> @@ -61,7 +62,7 @@ asmlinkage void car_stage_c_entry(void) /* Initialize the PCIe bridges */ pcie_init(); - if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Locate the top of RAM */ diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 6ff59bad65..fafa343780 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -158,7 +158,7 @@ asmlinkage void car_stage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* |