diff options
| -rw-r--r-- | src/northbridge/intel/haswell/pcie.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index d93639932f..cea3f6ac84 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -54,7 +54,9 @@ static void peg_enable(struct device *dev) assert(func < ARRAY_SIZE(config->peg_cfg)); - const bool slot_implemented = !config->peg_cfg[func].is_onboard; + const struct peg_config *peg_cfg = &config->peg_cfg[func]; + + const bool slot_implemented = !peg_cfg->is_onboard; if (slot_implemented) { /* Default is 1, but register is R/WO and needs to be written to once */ @@ -69,7 +71,7 @@ static void peg_enable(struct device *dev) /* Physical slot number (zero for ports connected to onboard devices) */ slotcap &= ~(0x1fff << 19); if (slot_implemented) { - uint16_t slot_number = config->peg_cfg[func].phys_slot_number & 0x1fff; + uint16_t slot_number = peg_cfg->phys_slot_number & 0x1fff; if (slot_number == 0) { /* Slot number must be non-zero and unique */ slot_number = func + 1; @@ -79,9 +81,9 @@ static void peg_enable(struct device *dev) /* Default to 1.0 watt scale */ slotcap &= ~(3 << 15); - slotcap |= (config->peg_cfg[func].power_limit_scale & 3) << 15; + slotcap |= (peg_cfg->power_limit_scale & 3) << 15; - uint8_t power_limit_value = config->peg_cfg[func].power_limit_value; + uint8_t power_limit_value = peg_cfg->power_limit_value; if (power_limit_value == 0) { /* Default to 75 watts */ power_limit_value = 75; |