diff options
| -rw-r--r-- | src/southbridge/intel/lynxpoint/chip.h | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/usb_xhci.c | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index e47a0310be..cc2cda0210 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -111,6 +111,9 @@ struct southbridge_intel_lynxpoint_config { * [24] = CLKOUT_ITPXDP */ uint32_t icc_clock_disable; + + /* Route USB ports to XHCI per default */ + uint8_t xhci_default; }; extern struct chip_operations southbridge_intel_lynxpoint_ops; diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 997ef61098..6c7bf046a8 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -26,6 +26,8 @@ #include <arch/io.h> #include "pch.h" +typedef struct southbridge_intel_lynxpoint_config config_t; + static u32 usb_xhci_mem_base(device_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -294,6 +296,7 @@ static void usb_xhci_init(device_t dev) u32 reg32; u16 reg16; u32 mem_base = usb_xhci_mem_base(dev); + config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); @@ -356,6 +359,9 @@ static void usb_xhci_init(device_t dev) /* Reset ports that are disabled or * polling before returning to the OS. */ usb_xhci_reset_usb3(dev, 0); + } else if (config->xhci_default) { + /* Route all ports to XHCI */ + outb(0xca, 0xb2); } } |