diff options
| -rw-r--r-- | src/cpu/x86/entry16.S | 2 | ||||
| -rw-r--r-- | src/cpu/x86/entry32.S | 9 | ||||
| -rw-r--r-- | src/drivers/amd/agesa/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/car/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/pre_c.S | 2 |
5 files changed, 9 insertions, 8 deletions
diff --git a/src/cpu/x86/entry16.S b/src/cpu/x86/entry16.S index 1ecd6ed422..501d01d3e4 100644 --- a/src/cpu/x86/entry16.S +++ b/src/cpu/x86/entry16.S @@ -125,7 +125,7 @@ _start16bit: movl %ebp, %eax /* Now that we are in protected mode jump to a 32 bit code segment. */ - ljmpl $ROM_CODE_SEG, $__protected_start + ljmpl $ROM_CODE_SEG, $bootblock_protected_mode_entry /** * The gdt is defined in gdt_init.S, it has a 4 Gb code segment diff --git a/src/cpu/x86/entry32.S b/src/cpu/x86/entry32.S index 32f61ad261..639ab36a57 100644 --- a/src/cpu/x86/entry32.S +++ b/src/cpu/x86/entry32.S @@ -25,8 +25,9 @@ */ .align 4 -.globl __protected_start -__protected_start: +.globl bootblock_protected_mode_entry +bootblock_protected_mode_entry: + /* Save the BIST value */ movl %eax, %ebp @@ -54,14 +55,14 @@ debug_spinloop: jz debug_spinloop #endif -bootblock_protected_mode_entry: - #if !CONFIG(USE_MARCH_586) /* MMX registers required here */ /* BIST result in eax */ movd %eax, %mm0 +__timestamp: + /* Get an early timestamp */ rdtsc movd %eax, %mm1 diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 33940cb489..1e15eda017 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -26,7 +26,7 @@ _cache_as_ram_setup: /* * on entry: * mm0: BIST (ignored) - * mm2_mm1: timestamp at bootblock_protected_mode_entry + * mm2_mm1: timestamp */ bootblock_pre_c_entry: diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 6282d7e571..251e23aaad 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -21,7 +21,7 @@ _cache_as_ram_setup: /* * on entry: * mm0: BIST (ignored) - * mm2_mm1: timestamp at bootblock_protected_mode_entry + * mm2_mm1: timestamp */ .global bootblock_pre_c_entry diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 520e3c08b0..5c16c29c8f 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -18,7 +18,7 @@ bootblock_resume_entry: /* * on entry: * mm0: BIST (ignored) - * mm2_mm1: timestamp at bootblock_protected_mode_entry + * mm2_mm1: timestamp */ .global bootblock_pre_c_entry |