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-rw-r--r--util/autoport/azalia.go11
-rw-r--r--util/autoport/bd82x6x.go40
-rw-r--r--util/autoport/ec_fixme.go4
-rw-r--r--util/autoport/main.go18
-rw-r--r--util/autoport/sandybridge.go13
5 files changed, 40 insertions, 46 deletions
diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index c525189972..d94441b6aa 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -20,13 +20,12 @@ const u32 cim_verb_data[] = {
`)
for _, codec := range ctx.InfoSource.GetAzaliaCodecs() {
- fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n",
+ fmt.Fprintf(az, "\t0x%08x,\t/* Codec Vendor / Device ID: %s */\n",
codec.VendorID, codec.Name)
- fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n",
+ fmt.Fprintf(az, "\t0x%08x,\t/* Subsystem ID */\n",
codec.SubsystemID)
- fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n",
+ fmt.Fprintf(az, "\t%d,\t\t/* Number of 4 dword sets */\n",
len(codec.PinConfig)+1)
- fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n")
fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n",
codec.CodecNo, codec.SubsystemID)
@@ -38,10 +37,10 @@ const u32 cim_verb_data[] = {
sort.Ints(keys)
for _, nid := range keys {
- fmt.Fprintf(az, "\n\t/* NID 0x%02x. */\n", nid)
fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n",
codec.CodecNo, nid, codec.PinConfig[nid])
}
+ az.WriteString("\n");
}
az.WriteString(
@@ -52,7 +51,7 @@ const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;
`)
- PutPCIDev(addr, "Audio controller")
+ PutPCIDev(addr, "")
}
func init() {
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index fbe0c3a03e..3ad212b343 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -41,6 +41,7 @@ func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) {
gpio := Create(ctx, "gpio.c")
defer gpio.Close()
+ AddBootBlockFile("gpio.c", "")
AddROMStageFile("gpio.c", "")
Add_gpl(gpio)
@@ -279,20 +280,22 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
DSDTIncludes = append(DSDTIncludes, DSDTInclude{
- File: "southbridge/intel/bd82x6x/acpi/platform.asl",
+ File: "southbridge/intel/common/acpi/platform.asl",
})
DSDTIncludes = append(DSDTIncludes, DSDTInclude{
- File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl",
- Comment: "global NVS and variables",
+ File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl",
})
DSDTIncludes = append(DSDTIncludes, DSDTInclude{
- File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl",
+ File: "southbridge/intel/common/acpi/sleepstates.asl",
})
DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
File: "southbridge/intel/bd82x6x/acpi/pch.asl",
})
- sb := Create(ctx, "romstage.c")
+ AddBootBlockFile("early_init.c", "")
+ AddROMStageFile("early_init.c", "")
+
+ sb := Create(ctx, "early_init.c")
defer sb.Close()
Add_gpl(sb)
sb.WriteString(`/* FIXME: Check if all includes are needed. */
@@ -305,25 +308,13 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
#include <device/pci_ops.h>
#include <device/pnp_ops.h>
#include <console/console.h>
+#include <bootblock_common.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
-void pch_enable_lpc(void)
-{
-`)
- RestorePCI16Simple(sb, addr, 0x82)
-
- RestorePCI16Simple(sb, addr, 0x80)
-
- sb.WriteString(`}
-
-void mainboard_rcba_config(void)
-{
`)
- sb.WriteString("}\n\n")
-
sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n")
currentMap := map[uint32]int{
@@ -360,13 +351,14 @@ void mainboard_rcba_config(void)
guessedMap := GuessSPDMap(ctx)
sb.WriteString(`
-void mainboard_early_init(int s3resume)
+void bootblock_mainboard_early_init(void)
{
-}
+`)
+ RestorePCI16Simple(sb, addr, 0x82)
-void mainboard_config_superio(void)
-{
-}
+ RestorePCI16Simple(sb, addr, 0x80)
+
+ sb.WriteString(`}
/* FIXME: Put proper SPD map here. */
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
@@ -394,7 +386,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- // the lid is open by default.
+ /* The lid is open by default. */
gnvs->lids = 1;
gnvs->tcrt = 100;
diff --git a/util/autoport/ec_fixme.go b/util/autoport/ec_fixme.go
index f06d4570d4..f54bb1ac50 100644
--- a/util/autoport/ec_fixme.go
+++ b/util/autoport/ec_fixme.go
@@ -22,13 +22,13 @@ func FIXMEEC(ctx Context) {
ap.WriteString(
`Method(_WAK,1)
{
- /* FIXME: EC support */
+ /* FIXME: EC support */
Return(Package(){0,0})
}
Method(_PTS,1)
{
- /* FIXME: EC support */
+ /* FIXME: EC support */
}
`)
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 03523a2c39..dbd8913723 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -77,6 +77,7 @@ type SouthBridger interface {
}
var SouthBridge SouthBridger
+var BootBlockFiles map[string]string = map[string]string{}
var ROMStageFiles map[string]string = map[string]string{}
var RAMStageFiles map[string]string = map[string]string{}
var SMMFiles map[string]string = map[string]string{}
@@ -154,6 +155,10 @@ func sanitize(inp string) string {
return result
}
+func AddBootBlockFile(Name string, Condition string) {
+ BootBlockFiles[Name] = Condition
+}
+
func AddROMStageFile(Name string, Condition string) {
ROMStageFiles[Name] = Condition
}
@@ -190,8 +195,7 @@ func writeMF(mf *os.File, files map[string]string, category string) {
if condition == "" {
fmt.Fprintf(mf, "%s-y += %s\n", category, file)
} else {
- fmt.Fprintf(mf, "%s-$(%s) += %s\n", category,
- condition, file)
+ fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, condition, file)
}
}
}
@@ -757,9 +761,10 @@ func main() {
AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT")
}
- if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 {
+ if len(BootBlockFiles) > 0 || len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 {
mf := Create(ctx, "Makefile.inc")
defer mf.Close()
+ writeMF(mf, BootBlockFiles, "bootblock")
writeMF(mf, ROMStageFiles, "romstage")
writeMF(mf, RAMStageFiles, "ramstage")
writeMF(mf, SMMFiles, "smm")
@@ -854,17 +859,18 @@ func main() {
dsdt.WriteString(
`
+
#include <arch/acpi.h>
+
DefinitionBlock(
"dsdt.aml",
"DSDT",
- 0x02, // DSDT revision: ACPI 2.0 and up
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
OEM_ID,
ACPI_TABLE_CREATOR,
- 0x20141018 // OEM revision
+ 0x20141018 /* OEM revision */
)
{
- /* Some generic macros */
#include "acpi/platform.asl"
`)
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
index 170d197af4..718fbe8f37 100644
--- a/util/autoport/sandybridge.go
+++ b/util/autoport/sandybridge.go
@@ -8,7 +8,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
/* FIXME:XX Move this somewhere else. */
MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
- MainboardEnable += (` /* FIXME: fix those values*/
+ MainboardEnable += (` /* FIXME: fix these values. */
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
@@ -37,7 +37,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
DevTree = DevTreeNode{
Chip: "northbridge/intel/sandybridge",
MissingParent: "northbridge",
- Comment: "FIXME: check gfx.ndid and gfx.did",
+ Comment: "FIXME: GPU registers may not always apply.",
Registers: map[string]string{
"gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
"gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
@@ -52,9 +52,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
"gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
"gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000),
- /* FIXME:XX hardcoded. */
- "gfx.ndid": "3",
- "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410 }",
},
Children: []DevTreeNode{
{
@@ -95,8 +92,8 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
ChildPCIBus: 0,
PCISlots: []PCISlot{
PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
- PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
- PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PEG"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "iGPU"},
},
},
},
@@ -134,7 +131,7 @@ func init() {
0x0112, 0x0116, 0x0122, 0x0126,
0x0152, 0x0156, 0x0162, 0x0166,
} {
- RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ RegisterPCI(0x8086, id, GenericVGA{GenericPCI{}})
}
/* PCIe bridge */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 03:49:30 +0000