diff options
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index ad934c3e0c..15902528af 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -166,6 +166,10 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[2]" = "1" # RP 3 uses SRCCLKREQ0# register "PcieRpClkReqNumber[2]" = "0" + # RP 3, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[2]" = "1" + # RP 3, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[2]" = "1" # Enable Root port 4(x1) for WLAN. register "PcieRpEnable[3]" = "1" @@ -173,6 +177,10 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[3]" = "1" # RP 4 uses SRCCLKREQ5# register "PcieRpClkReqNumber[3]" = "5" + # RP 4, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[3]" = "1" + # RP 4, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[3]" = "1" # Enable Root port 5(x4) for NVMe. register "PcieRpEnable[4]" = "1" @@ -180,6 +188,10 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[4]" = "1" # RP 5 uses SRCCLKREQ1# register "PcieRpClkReqNumber[4]" = "1" + # RP 5, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # RP 5, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" # Enable Root port 9 for BtoB. register "PcieRpEnable[8]" = "1" @@ -187,6 +199,10 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[8]" = "1" # RP 9 uses SRCCLKREQ2# register "PcieRpClkReqNumber[8]" = "2" + # RP 9, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[8]" = "1" + # RP 9, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[8]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear |