diff options
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cpulib.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 2 |
3 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9e4f7a27b0..4898066d4a 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -510,3 +510,10 @@ bool is_tme_supported(void) return (cpuid_regs.ecx & TME_SUPPORTED); } + +void set_tme_core_activate(void) +{ + msr_t msr = { .lo = 0, .hi = 0 }; + + wrmsr(MSR_CORE_MKTME_ACTIVATION, msr); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index f0ebd09f82..7878bf4203 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -202,4 +202,13 @@ void init_core_prmrr(void); */ bool is_tme_supported(void); +/* + * Set TME core activate MSR + * + * Write zero to TME core activate MSR will translate the TME_ACTIVATE[MK_TME_KEYID_BITS] + * value into PMH mask register. + * TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35] + */ +void set_tme_core_activate(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index a7ad699733..47b9e4a9b9 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -94,6 +94,8 @@ #define PKG_POWER_LIMIT_TIME_MASK (0x7f) #define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24 #define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f) + +#define MSR_CORE_MKTME_ACTIVATION 0x9ff /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 |