diff options
| -rw-r--r-- | src/mainboard/intel/d510mo/romstage.c | 14 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/ram_calc.c | 47 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/raminit.c | 1 |
6 files changed, 61 insertions, 6 deletions
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index d39d2f6542..f99e185f2a 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -31,6 +31,8 @@ #include <superio/winbond/common/winbond.h> #include <lib.h> #include <arch/stages.h> +#include <cbmem.h> +#include <romstage_handoff.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) @@ -99,6 +101,8 @@ static void rcba_config(void) void mainboard_romstage_entry(unsigned long bist) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; + int cbmem_was_initted; + int s3resume = 0; if (bist == 0) enable_lapic(); @@ -131,4 +135,14 @@ void mainboard_romstage_entry(unsigned long bist) ram_check(0x200000,0x300000); rcba_config(); + + cbmem_was_initted = !cbmem_recovery(s3resume); + + if (!cbmem_was_initted && s3resume) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + halt(); + } + + romstage_handoff_init(s3resume); } diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 5b34fb2bfe..3cfda9f97e 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -23,7 +23,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER - select LATE_CBMEM_INIT select VGA select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index e1cf95f298..3984fb7a07 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci.h> -#include <cbmem.h> #include <halt.h> #include <string.h> #include <northbridge/intel/pineview/pineview.h> diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 6fc841c09e..b7fd8a1085 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -25,7 +25,6 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> -#include <cbmem.h> #include <northbridge/intel/pineview/pineview.h> /* Reserve everything between A segment and 1MB: @@ -126,8 +125,6 @@ static void mch_domain_read_resources(device_t dev) } add_fixed_resources(dev, index); - - set_top_of_ram(tomk << 10); } static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index af1ca72dba..63f39428db 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -22,6 +22,8 @@ #include <console/console.h> #include <cbmem.h> #include <northbridge/intel/pineview/pineview.h> +#include <cpu/x86/mtrr.h> +#include <cpu/intel/romstage.h> u8 decode_pciebar(u32 *const base, u32 *const len) { @@ -91,3 +93,48 @@ u32 decode_igd_gtt_size(const u32 gsm) } return (u32)(gsmsize[gsm] << 10); } + +/* Depending of UMA and TSEG configuration, TSEG might start at any + * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * CBMEM top downwards to 4 MiB boundary. + */ +void *cbmem_top(void) +{ + uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); + return (void *) top_of_ram; +} + +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +void *setup_stack_and_mtrrs(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache two separate 4 MiB regions below the top of ram, this + * satisfies MTRR alignment requirements. If you modify this to + * cover TSEG, make sure UMA region is not set with WRBACK as it + * causes hard-to-recover boot failures. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); +} diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 69880580c1..330c912a12 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -15,7 +15,6 @@ */ #include <arch/io.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> |