diff options
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 5 | ||||
| -rw-r--r-- | src/soc/amd/picasso/reset.c | 5 |
3 files changed, 3 insertions, 8 deletions
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index cec3aaffc7..43e56582a1 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -83,6 +83,5 @@ #define BIOSRAM_DATA 0xcd5 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) -#define SYS_RESET 0xcf9 #endif /* AMD_PICASSO_IOMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 08e242828b..220d92ea7a 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -163,11 +163,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* IO 0xcf9 - Reset control port*/ -#define FULL_RST BIT(3) -#define RST_CMD BIT(2) -#define SYS_RST BIT(1) - /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT BIT(7) /* Write-once */ diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index dea166a11f..e16223a50e 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -2,6 +2,7 @@ #include <arch/io.h> #include <console/console.h> +#include <cf9_reset.h> #include <reset.h> #include <soc/reset.h> #include <soc/southbridge.h> @@ -27,7 +28,7 @@ void do_cold_reset(void) /* De-assert and then assert all PwrGood signals on CF9 reset. */ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); } void do_warm_reset(void) @@ -35,7 +36,7 @@ void do_warm_reset(void) set_warm_reset_flag(); /* Assert reset signals only. */ - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); } void do_board_reset(void) |