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-rw-r--r--src/cpu/intel/car/romstage.c18
-rw-r--r--src/drivers/intel/fsp1_1/car.c15
-rw-r--r--src/include/cpu/intel/romstage.h6
-rw-r--r--src/northbridge/intel/e7505/memmap.c17
-rw-r--r--src/northbridge/intel/gm45/memmap.c19
-rw-r--r--src/northbridge/intel/haswell/memmap.c16
-rw-r--r--src/northbridge/intel/i440bx/memmap.c15
-rw-r--r--src/northbridge/intel/i945/memmap.c19
-rw-r--r--src/northbridge/intel/nehalem/memmap.c20
-rw-r--r--src/northbridge/intel/pineview/memmap.c20
-rw-r--r--src/northbridge/intel/sandybridge/memmap.c20
-rw-r--r--src/northbridge/intel/x4x/memmap.c20
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c37
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c16
14 files changed, 93 insertions, 165 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 89052d6be6..f6b62192f1 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -22,6 +22,21 @@
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
+static struct postcar_frame early_mtrrs;
+
+/* prepare_and_run_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
+static void prepare_and_run_postcar(struct postcar_frame *pcf)
+{
+ if (postcar_frame_init(pcf, 0))
+ die("Unable to initialize postcar frame.\n");
+
+ fill_postcar_frame(pcf);
+
+ run_postcar_phase(pcf);
+ /* We do not return here. */
+}
+
static void romstage_main(unsigned long bist)
{
int i;
@@ -52,7 +67,8 @@ static void romstage_main(unsigned long bist)
printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
}
- platform_enter_postcar();
+ prepare_and_run_postcar(&early_mtrrs);
+ /* We do not return here. */
}
#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 1b6f62c351..f6e42d7bfa 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -24,30 +24,23 @@
#include <fsp/util.h>
#include <program_loading.h>
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+ postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations. */
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK);
- run_postcar_phase(&pcf);
}
/* This is the romstage entry called from cpu/intel/car/romstage.c */
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index 47cd169e6a..328f464ec4 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -5,6 +5,10 @@
void mainboard_romstage_entry(unsigned long bist);
-void platform_enter_postcar(void);
+/* fill_postcar_frame() is called after raminit completes and right before
+ * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()
+ * to tag memory ranges as cacheable to speed up execution of postcar and
+ * early ramstage. */
+void fill_postcar_frame(struct postcar_frame *pcf);
#endif /* _CPU_INTEL_ROMSTAGE_H */
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index b954c6af74..c3b59e9415 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -43,17 +43,10 @@ void northbridge_write_smram(u8 smram)
pci_write_config8(mch, SMRAMC, smram);
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
-
/*
* Choose to NOT set ROM as WP cacheable here.
* Timestamps indicate the CPU this northbridge code is
@@ -62,14 +55,10 @@ void platform_enter_postcar(void)
*/
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache CBMEM region as WB. */
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
-
- /* We do not return here. */
}
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 6795f7a61f..9337470e1e 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -134,33 +134,24 @@ void stage_cache_external_region(void **base, size_t *size)
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
- postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+ postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
- run_postcar_phase(&pcf);
-
- /* We do not return here. */
}
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 14b66a0fc7..13881e99b2 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -53,29 +53,21 @@ void stage_cache_external_region(void **base, size_t *size)
*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
}
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 495ca8682a..084679ff4a 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -68,27 +68,20 @@ void *cbmem_top(void)
return (void *)tom;
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache CBMEM region as WB. */
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
- run_postcar_phase(&pcf);
}
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index ac1499e0fc..5f3e2569fb 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -100,33 +100,24 @@ void stage_cache_external_region(void **base, size_t *size)
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
- postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+ postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
- run_postcar_phase(&pcf);
-
- /* We do not return here. */
}
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index ec036c9d7c..1a3a6d7cdf 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -58,32 +58,22 @@ void stage_cache_external_region(void **base, size_t *size)
northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
- postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
-
- /* We do not return here. */
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
}
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 2f3ff6e921..66900af2ef 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -150,33 +150,23 @@ void stage_cache_external_region(void **base, size_t *size)
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
- postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+ postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
-
- /* We do not return here. */
}
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 7d5c173829..99f11a0f2a 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -57,38 +57,28 @@ void stage_cache_external_region(void **base, size_t *size)
- CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
top_of_ram = (uintptr_t)cbmem_top();
/* Cache 8MiB below the top of ram. On sandybridge systems the top of
* ram under 4GiB is the start of the TSEG region. It is required to
* be 8MiB aligned. Set this area as cacheable so it can be used later
* for ramstage before setting up the entire RAM as cacheable. */
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
/* Cache 8MiB at the top of ram. Top of ram on sandybridge systems
* is where the TSEG region resides. However, it is not restricted
* to SMM mode until SMM has been relocated. By setting the region
* to cacheable it provides faster access when relocating the SMM
* handler as well as using the TSEG region for other purposes. */
- postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
-
- /* We do not return here. */
+ postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
}
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index dda838760d..254ca880fa 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -145,33 +145,23 @@ void stage_cache_external_region(void **base, size_t *size)
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
- postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+ postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
-
- /* We do not return here. */
}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 7e2bb64ba6..acdf2613fa 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -49,7 +49,22 @@
* Because we can't use global variables the stack is used for allocations --
* thus the need to call back and forth. */
-static void platform_enter_postcar(void);
+static struct postcar_frame early_mtrrs;
+
+static void fill_postcar_frame(struct postcar_frame *pcf);
+
+/* prepare_and_run_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
+static void prepare_and_run_postcar(struct postcar_frame *pcf)
+{
+ if (postcar_frame_init(pcf, 0))
+ die("Unable to initialize postcar frame.\n");
+
+ fill_postcar_frame(pcf);
+
+ run_postcar_phase(pcf);
+ /* We do not return here. */
+}
static void program_base_addresses(void)
{
@@ -129,9 +144,8 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
/* Call into mainboard. */
mainboard_romstage_entry(&rp);
- platform_enter_postcar();
-
- /* We don't return here */
+ prepare_and_run_postcar(&early_mtrrs);
+ /* We do not return here. */
}
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
@@ -238,28 +252,21 @@ void romstage_common(struct romstage_params *params)
romstage_handoff_init(prev_sleep_state == ACPI_S3);
}
-/* setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-static void platform_enter_postcar(void)
+static void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
}
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 9c86809368..ca478f7313 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -35,31 +35,23 @@
#include <soc/romstage.h>
#include <soc/spi.h>
-/* platform_enter_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use,
- * and continues execution in postcar stage. */
-void platform_enter_postcar(void)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
- struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
*/
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
}
/* Entry from cpu/intel/car/romstage.c. */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 09:54:11 +0000