diff options
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/sata.c | 7 |
2 files changed, 12 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index b46c2e256d..8e05998c19 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -246,8 +246,11 @@ static void initialize_vr_config(void) msr = rdmsr(MSR_VR_MISC_CONFIG2); msr.lo &= ~0xffff; /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; + * set the fast ramp voltage in 10mV steps. */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) + msr.lo |= 0x006a; /* 1.56V */ + else + msr.lo |= 0x006f; /* 1.60V */ wrmsr(MSR_VR_MISC_CONFIG2, msr); } diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e9e0810de1..0e2516185a 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -92,6 +92,13 @@ static void sata_init(struct device *dev) abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5)); printk(BIOS_DEBUG, "ABAR: %p\n", abar); + /* CAP (HBA Capabilities) : enable power management */ + reg32 = read32(abar + 0x00); + reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ + reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ + reg32 |= (1 << 18); /* SAM: SATA AHCI MODE ONLY */ + write32(abar + 0x00, reg32); + /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); (void) read32(abar + 0x0c); /* Read back 1 */ |