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-rw-r--r--src/soc/mediatek/common/ddp.c1
-rw-r--r--src/soc/mediatek/common/display.c1
-rw-r--r--src/soc/mediatek/common/dp/dptx_hal.c1
-rw-r--r--src/soc/mediatek/common/i2c.c1
-rw-r--r--src/soc/mediatek/common/msdc.c1
-rw-r--r--src/soc/mediatek/common/uart.c1
-rw-r--r--src/soc/mediatek/mt8173/da9212.c1
-rw-r--r--src/soc/mediatek/mt8173/dramc_pi_basic_api.c4
-rw-r--r--src/soc/mediatek/mt8173/dramc_pi_calibration_api.c4
-rw-r--r--src/soc/mediatek/mt8173/mt6391.c2
-rw-r--r--src/soc/mediatek/mt8183/dramc_pi_basic_api.c1
-rw-r--r--src/soc/mediatek/mt8183/emi.c2
-rw-r--r--src/soc/mediatek/mt8186/devapc.c1
-rw-r--r--src/soc/mediatek/mt8188/devapc.c6
-rw-r--r--src/soc/mediatek/mt8188/include/soc/gpio.h1
-rw-r--r--src/soc/mediatek/mt8192/devapc.c1
-rw-r--r--src/soc/mediatek/mt8195/include/soc/gpio.h1
-rw-r--r--src/soc/mediatek/mt8195/spm.c1
18 files changed, 0 insertions, 31 deletions
diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c
index 67e2fbf725..7e2d373b56 100644
--- a/src/soc/mediatek/common/ddp.c
+++ b/src/soc/mediatek/common/ddp.c
@@ -46,7 +46,6 @@ void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size)
void color_start(u32 width, u32 height)
{
-
write32(&disp_color0->width, width);
write32(&disp_color0->height, height);
write32(&disp_color0->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL);
diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c
index a5b0e6b031..0dea58c74f 100644
--- a/src/soc/mediatek/common/display.c
+++ b/src/soc/mediatek/common/display.c
@@ -81,7 +81,6 @@ int mtk_display_init(void)
return -1;
}
} else {
-
struct panel_serializable_data *mipi_data = NULL;
if (panel->get_edid) {
diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c
index b246c20119..c46f45765e 100644
--- a/src/soc/mediatek/common/dp/dptx_hal.c
+++ b/src/soc/mediatek/common/dp/dptx_hal.c
@@ -324,7 +324,6 @@ void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value)
void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value)
{
mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff);
-
}
void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value)
diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c
index ab7b0def1c..886fb2a662 100644
--- a/src/soc/mediatek/common/i2c.c
+++ b/src/soc/mediatek/common/i2c.c
@@ -472,7 +472,6 @@ int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
base_step_cnt = step_cnt;
if (best_mul == opt_div + clock_div_constraint)
break;
-
}
if (!success)
diff --git a/src/soc/mediatek/common/msdc.c b/src/soc/mediatek/common/msdc.c
index 0d1dbb5049..e7cd571d8e 100644
--- a/src/soc/mediatek/common/msdc.c
+++ b/src/soc/mediatek/common/msdc.c
@@ -388,7 +388,6 @@ static void msdc_set_ios(struct sd_mmc_ctrlr *ctrlr)
msdc_set_clock(host, ctrlr->request_hz);
msdc_set_buswidth(host, ctrlr->bus_width);
-
}
static void msdc_update_pointers(struct msdc_ctrlr *host)
diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c
index 79ca07230f..4585fc07cb 100644
--- a/src/soc/mediatek/common/uart.c
+++ b/src/soc/mediatek/common/uart.c
@@ -111,7 +111,6 @@ static void mtk_uart_init(void)
write8(&uart_ptr->fcr,
UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |
UART8250_FCR_CLEAR_XMIT);
-
}
static void mtk_uart_tx_byte(unsigned char data)
diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c
index 5028f18792..2b118bfa0c 100644
--- a/src/soc/mediatek/mt8173/da9212.c
+++ b/src/soc/mediatek/mt8173/da9212.c
@@ -47,7 +47,6 @@ static void da9212_hw_init(uint8_t i2c_num, unsigned char variant_id)
if (ret)
printk(BIOS_ERR, "%s failed\n", __func__);
-
}
void da9212_probe(uint8_t i2c_num)
diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
index 10d03e0c8e..e58ea53bbd 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
@@ -154,7 +154,6 @@ static void mem_pll_init_phase_sync(u32 channel)
static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs)
{
switch (mempll->phase) {
-
case MEMPLL_INIT:
/* initial phase: zero out RG_MEPLL(2,3,4)_(REF_DL,FB)_DL */
clrbits32(&ch[channel].ddrphy_regs->mempll[reg_offs],
@@ -189,7 +188,6 @@ static void pll_phase_check(u32 channel, struct mem_pll *mempll, int idx)
(idx + 2), mempll->phase, one_count, zero_count);
switch (mempll->phase) {
-
case MEMPLL_INIT:
if ((one_count - zero_count) > JMETER_COUNT_N) {
/* REF lag FBK */
@@ -243,7 +241,6 @@ static void mem_pll_phase_cali(u32 channel)
JMETER_COUNT << JMETER_COUNTER_SHIFT);
while (1) {
-
for (i = 0; i < 3; i++) {
if (!mempll[i].done) {
pll_phase_adjust(channel, &mempll[i], (i + 2) * 3);
@@ -317,7 +314,6 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params)
udelay(100);
for (channel = 0; channel < CHANNEL_NUM; channel++) {
-
/* mempll_bias_en */
write32(&ch[channel].ddrphy_regs->mempll[3], 0xd << 28 |
0x1 << 6);
diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
index fc5c58c0c6..b9f11a0e5a 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
@@ -751,7 +751,6 @@ void tx_delay_for_wrleveling(u32 channel,
max_taps = MAX_DQDLY_TAPS - 1;
for (i = 0; i < DATA_WIDTH_32BIT; i++) {
-
index = i / DQS_BIT_NUMBER;
if (i % DQS_BIT_NUMBER == 0)
@@ -823,7 +822,6 @@ static void set_tx_dly_factor(u32 channel, u32 curr_val, u8 type)
value += (curr_val << (4 * i));
switch (type) {
-
case TX_DQS:
write32(&ch[channel].ddrphy_regs->padctl3, value);
break;
@@ -979,7 +977,6 @@ void perbit_window_cal(u32 channel, u8 type)
/* delay DQ from 0 to 15 to get the setup time */
for (dly = FIRST_DQ_DELAY; dly < MAX_DQDLY_TAPS; dly++) {
-
set_dly_factor(channel, STAGE_SETUP, type, dly);
err_value = dram_k_perbit(channel);
@@ -1015,7 +1012,6 @@ void perbit_window_cal(u32 channel, u8 type)
/* delay DQS to get the hold time, dq_dly = dqs_dly = 0 is counted */
/* when we delay dq, so we set first dqs delay to 1 */
for (dly = (FIRST_DQS_DELAY + 1); dly < max_dqs_taps; dly++) {
-
set_dly_factor(channel, STAGE_HOLD, type, dly);
err_value = dram_k_perbit(channel);
diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c
index 2186c063c1..f9a4629ca5 100644
--- a/src/soc/mediatek/mt8173/mt6391.c
+++ b/src/soc/mediatek/mt8173/mt6391.c
@@ -78,7 +78,6 @@ void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
pwrap_write_field(addr, vsel, 0x7, 5);
pwrap_write_field(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15);
-
}
void mt6391_enable_reset_when_ap_resets(void)
@@ -362,7 +361,6 @@ static void mt6391_init_setting(void)
pwrap_write_field(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3);
/* For low power, VIO18 set sleep_en to HW mode */
pwrap_write_field(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8);
-
}
static void mt6391_default_buck_voltage(void)
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
index d992371fac..0a4039bfa6 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
@@ -289,7 +289,6 @@ static void dramc_rx_input_delay_tracking(u8 chn)
clrsetbits32(&ch[chn].phy.r[rank].b[b].rxdvs[2],
(0x3 << 30) | (0x1 << 28) | (0x1 << 23),
(0x2 << 30) | (0x1 << 28) | (0x1 << 23));
-
}
static void dramc_hw_dqs_gating_tracking(u8 chn)
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index 5e4f01531a..8b0566749a 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -537,7 +537,6 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
dst_addr = (u8 *)&ch[chn].ao.shu[dst_shuffle] +
offset;
write32(dst_addr, read32(src_addr));
-
}
}
@@ -569,7 +568,6 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
dst_addr = (u8 *)&ch[chn].phy.shu[dst_shuffle] +
offset;
write32(dst_addr, read32(src_addr));
-
}
}
}
diff --git a/src/soc/mediatek/mt8186/devapc.c b/src/soc/mediatek/mt8186/devapc.c
index d831dcdf27..d32e62cbc3 100644
--- a/src/soc/mediatek/mt8186/devapc.c
+++ b/src/soc/mediatek/mt8186/devapc.c
@@ -370,7 +370,6 @@ static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = {
/* module, AP permission, N/A, SSPM permission, N/A */
static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[] = {
-
/* 0 */
DAPC_MM_AO_SYS0_ATTR("IP",
NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION),
diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c
index 6e47f70597..6c585baf50 100644
--- a/src/soc/mediatek/mt8188/devapc.c
+++ b/src/soc/mediatek/mt8188/devapc.c
@@ -1492,7 +1492,6 @@ static void set_infra_ao_apc(uintptr_t base)
for (j = 0; j < ARRAY_SIZE(infra_ao_sys2_devices[i].d_permission); j++)
set_module_apc(base + SYS2_D0_APC_0, i, domain_map[j],
infra_ao_sys2_devices[i].d_permission[j]);
-
}
static void set_peri_ao_apc(uintptr_t base)
@@ -1516,7 +1515,6 @@ static void set_peri_ao_apc(uintptr_t base)
for (j = 0; j < ARRAY_SIZE(peri_ao_sys1_devices[i].d_permission); j++)
set_module_apc(base + SYS1_D0_APC_0, i, domain_map[j],
peri_ao_sys1_devices[i].d_permission[j]);
-
}
static void set_peri2_ao_apc(uintptr_t base)
@@ -1527,7 +1525,6 @@ static void set_peri2_ao_apc(uintptr_t base)
for (j = 0; j < ARRAY_SIZE(peri2_ao_sys0_devices[i].d_permission); j++)
set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j],
peri2_ao_sys0_devices[i].d_permission[j]);
-
}
static void set_peri_par_ao_apc(uintptr_t base)
@@ -1538,7 +1535,6 @@ static void set_peri_par_ao_apc(uintptr_t base)
for (j = 0; j < ARRAY_SIZE(peri_par_ao_sys0_devices[i].d_permission); j++)
set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j],
peri_par_ao_sys0_devices[i].d_permission[j]);
-
}
static void dump_infra_ao_apc(uintptr_t base)
@@ -1599,7 +1595,6 @@ static void dump_peri2_ao_apc(uintptr_t base)
for (i = 0; i < reg_max; i++)
printk(BIOS_DEBUG, "[DEVAPC] (PERI2_AO_SYS0)D%d_APC_%d: %#x\n", d,
i, read32(getreg_domain(base, SYS0_D0_APC_0, d, i)));
-
}
static void dump_peri_par_ao_apc(uintptr_t base)
@@ -1716,7 +1711,6 @@ static void peri_par_init(uintptr_t base)
/* Master Domain */
SET32_BITFIELDS(getreg_domain(base, MAS_DOM_0, 0, 4),
PCIE0_DOM, DOMAIN_2);
-
}
static void fmem_master_init(uintptr_t base)
diff --git a/src/soc/mediatek/mt8188/include/soc/gpio.h b/src/soc/mediatek/mt8188/include/soc/gpio.h
index 8767e0f7a9..916cf84e8f 100644
--- a/src/soc/mediatek/mt8188/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8188/include/soc/gpio.h
@@ -44,7 +44,6 @@ enum {
})
enum {
-
PIN(0, GPIO00, 0, 6, 0x31, 0xe0,
TP_GPIO0_AO, SPIM5_CSB, UTXD1, DMIC3_CLK,
I2SIN_MCK, I2SO2_MCK, DBG_MON_A0),
diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c
index 1fdc519c28..96bd2bdc04 100644
--- a/src/soc/mediatek/mt8192/devapc.c
+++ b/src/soc/mediatek/mt8192/devapc.c
@@ -46,7 +46,6 @@ static void infra_master_init(uintptr_t base)
TWO_BIT_DOM_REMAP_2, MAS_DOMAIN_1,
TWO_BIT_DOM_REMAP_3, MAS_DOMAIN_3,
TWO_BIT_DOM_REMAP_4, MAS_DOMAIN_1);
-
}
static void peri_master_init(uintptr_t base)
diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h
index 60f3af1d41..02c3580329 100644
--- a/src/soc/mediatek/mt8195/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8195/include/soc/gpio.h
@@ -37,7 +37,6 @@ enum {
})
enum {
-
PIN(0, GPIO_00, 1, 0, 0x23, 0x60,
TP_GPIO0_AO, MSDC2_CMD, TDMIN_MCK, CLKM0,
PERSTN_1, IDDIG_1P, DMIC4_CLK),
diff --git a/src/soc/mediatek/mt8195/spm.c b/src/soc/mediatek/mt8195/spm.c
index 457c019604..01df38d859 100644
--- a/src/soc/mediatek/mt8195/spm.c
+++ b/src/soc/mediatek/mt8195/spm.c
@@ -467,7 +467,6 @@ void spm_register_init(void)
SPM_DVFSRC_ENABLE_LSB, 1);
write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF);
write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF);
-
}
void spm_reset_and_init_pcm(void)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 16:10:24 +0000