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-rw-r--r--src/cpu/amd/pi/00730F01/Makefile.inc3
-rw-r--r--src/cpu/amd/pi/00730F01/fixme.c103
-rw-r--r--src/mainboard/amd/olivehillplus/agesawrapper.c90
-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c2
-rw-r--r--src/northbridge/amd/pi/agesawrapper.h3
5 files changed, 109 insertions, 92 deletions
diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc
index fba21854e7..833b0fc90a 100644
--- a/src/cpu/amd/pi/00730F01/Makefile.inc
+++ b/src/cpu/amd/pi/00730F01/Makefile.inc
@@ -17,6 +17,9 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+romstage-y += fixme.c
+
+ramstage-y += fixme.c
ramstage-y += chip_name.c
ramstage-y += model_16_init.c
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
new file mode 100644
index 0000000000..d483391a76
--- /dev/null
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include "amdlib.h"
+
+void amd_initcpuio(void)
+{
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /* Enable legacy video routing: D18F1xF4 VGA Enable */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+ PciData = 1;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+ * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+ * set to non-posted regions.
+ */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+ PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
+ PciData |= 1 << 7; /* set NP (non-posted) bit */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+ PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Map the remaining PCI hole as posted MMIO */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+ PciData = 0x00FECF00; /* last address before non-posted range */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ MsrReg = (MsrReg >> 8) | 3;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+ PciData = (UINT32)MsrReg;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Send all IO (0000-FFFF) to southbridge. */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+ PciData = 0x0000F000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+ PciData = 0x00000003;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+}
+
+void amd_initmmio(void)
+{
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+ Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+ LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | 0x0000400000000000;
+ LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+ /* For serial port */
+ PciData = 0xFF03FFD5;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* PSP */
+ //PciData = 0xD;
+ //PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x8, 0x0, 0x48);
+ //LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
+ LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+}
diff --git a/src/mainboard/amd/olivehillplus/agesawrapper.c b/src/mainboard/amd/olivehillplus/agesawrapper.c
index 0cc2ebecf8..686c8287ab 100644
--- a/src/mainboard/amd/olivehillplus/agesawrapper.c
+++ b/src/mainboard/amd/olivehillplus/agesawrapper.c
@@ -58,94 +58,6 @@ static void *AcpiAlib = NULL;
static void *AcpiIvrs = NULL;
#endif
-AGESA_STATUS agesawrapper_amdinitcpuio(void)
-{
- AGESA_STATUS Status;
- UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- AMD_CONFIG_PARAMS StdHeader;
-
- /* Enable legacy video routing: D18F1xF4 VGA Enable */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
- PciData = 1;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
- * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
- * set to non-posted regions.
- */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
- PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
- PciData |= 1 << 7; /* set NP (non-posted) bit */
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
- PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Map the remaining PCI hole as posted MMIO */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
- PciData = 0x00FECF00; /* last address before non-posted range */
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
- MsrReg = (MsrReg >> 8) | 3;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
- PciData = (UINT32)MsrReg;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Send all IO (0000-FFFF) to southbridge. */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
- PciData = 0x0000F000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
- PciData = 0x00000003;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- Status = AGESA_SUCCESS;
- return Status;
-}
-
-AGESA_STATUS agesawrapper_amdinitmmio(void)
-{
- AGESA_STATUS Status;
- UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- AMD_CONFIG_PARAMS StdHeader;
-
- /*
- Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
- Address MSR register.
- */
- MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
- LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-
- /*
- Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
- */
- LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
- MsrReg = MsrReg | 0x0000400000000000;
- LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
- /* For serial port */
- PciData = 0xFF03FFD5;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* PSP */
- //PciData = 0xD;
- //PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x8, 0x0, 0x48);
- //LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Set ROM cache onto WP to decrease post time */
- MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
- MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
-
- Status = AGESA_SUCCESS;
- return Status;
-}
-
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status;
@@ -322,7 +234,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
- agesawrapper_amdinitcpuio ();
+ amd_initcpuio ();
LibAmdMemFill (&AmdParamStruct,
0,
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 6b081c653e..bf274a6cca 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -52,7 +52,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+ amd_initmmio();
hudson_lpc_port80();
diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h
index 848434cc90..adcc75529b 100644
--- a/src/northbridge/amd/pi/agesawrapper.h
+++ b/src/northbridge/amd/pi/agesawrapper.h
@@ -43,8 +43,6 @@ AGESA_STATUS agesawrapper_amdinitlate(void);
AGESA_STATUS agesawrapper_amdinitpost(void);
AGESA_STATUS agesawrapper_amdinitmid(void);
AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus);
-AGESA_STATUS agesawrapper_amdinitmmio(void);
-AGESA_STATUS agesawrapper_amdinitcpuio(void);
void *agesawrapper_getlateinitptr(int pick);
AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, void *ConfigPtr);
AGESA_STATUS agesawrapper_amdS3Save(void);
@@ -56,5 +54,6 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void);
VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly);
VOID amd_initcpuio(void);
+VOID amd_initmmio(void);
#endif /* _AGESAWRAPPER_H_ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-22 01:08:38 +0000