summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/arch/x86/Makefile.inc3
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc8
-rw-r--r--src/cpu/amd/geode_gx2/cache_as_ram.inc2
-rw-r--r--src/cpu/amd/geode_lx/cache_as_ram.inc2
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc8
-rw-r--r--src/cpu/intel/car/cache_as_ram_ht.inc4
-rw-r--r--src/cpu/intel/haswell/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/model_2065x/cache_as_ram.inc4
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc6
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc4
-rw-r--r--src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc2
-rw-r--r--src/soc/intel/baytrail/romstage/cache_as_ram.inc4
-rw-r--r--src/soc/intel/broadwell/romstage/cache_as_ram.inc4
-rw-r--r--src/vendorcode/amd/agesa/f10/gcccar.inc6
-rw-r--r--src/vendorcode/amd/agesa/f12/gcccar.inc6
-rw-r--r--src/vendorcode/amd/agesa/f14/gcccar.inc6
-rw-r--r--src/vendorcode/amd/agesa/f15/gcccar.inc6
-rw-r--r--src/vendorcode/amd/agesa/f15tn/gcccar.inc6
-rw-r--r--src/vendorcode/amd/agesa/f16kb/gcccar.inc6
19 files changed, 44 insertions, 47 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 20740a4df1..f502bbe03e 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -247,9 +247,6 @@ $(objgenerated)/crt0.S: $$(crt0s)
# Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428
romstage-S-ccopts += -I. -g0
-# Some cache as ram code is doing divisions
-romstage-S-ccopts +=-Wa,--divide
-
endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64
###############################################################################
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index ac6ea33b98..133daace3d 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -240,15 +240,15 @@ clear_fixed_var_mtrr_out:
* windowoffset is the 32k-aligned window into CAR size.
*/
.macro simplemask carsize, windowoffset
- .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
+ .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4)
extractmask gas_bug_workaround, %eax
- .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
+ .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12))
extractmask gas_bug_workaround, %edx
/*
* Without the gas bug workaround, the entire macro would consist
* only of the two lines below:
- * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
- * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+ * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax
+ * extractmask (((\carsize - \windowoffset) >> 12)), %edx
*/
.endm
diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc
index 7ddd3af803..837352f8a7 100644
--- a/src/cpu/amd/geode_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc
@@ -166,7 +166,7 @@ done_cache_as_ram_main:
/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
push %edi
- mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
+ mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx
push %esi
mov $(CONFIG_DCACHE_RAM_BASE),%edi
mov %edi,%esi
diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index df6f942f58..bcb0d4b52a 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -192,7 +192,7 @@ done_cache_as_ram_main:
* copying it back to itself to invalidate the cache */
push %edi
- mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
+ mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx
push %esi
mov $(CONFIG_DCACHE_RAM_BASE),%edi
mov %edi,%esi
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 1d8ea8d844..f9be6e890f 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -195,15 +195,15 @@ clear_fixed_var_mtrr_out:
* windowoffset is the 32k-aligned window into CAR size.
*/
.macro simplemask carsize, windowoffset
- .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
+ .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4)
extractmask gas_bug_workaround, %eax
- .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
+ .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12))
extractmask gas_bug_workaround, %edx
/*
* Without the gas bug workaround, the entire macro would consist
* only of the two lines below:
- * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
- * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
+ * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax
+ * extractmask (((\carsize - \windowoffset) >> 12)), %edx
*/
.endm
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 29d7113600..193ad418c0 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -47,7 +47,7 @@ cache_as_ram:
* For hyper-threaded CPUs these are shared.
*/
movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -296,7 +296,7 @@ no_msr_11e:
cld
xorl %eax, %eax
movl $CACHE_AS_RAM_BASE, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 595b4df8b1..0a070b2e81 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -60,7 +60,7 @@ wait_for_sipi:
post_code(0x21)
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -116,7 +116,7 @@ clear_mtrrs:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 62f816acfd..cfa3b6b3bf 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -57,7 +57,7 @@ wait_for_sipi:
post_code(0x22)
/* Zero out all fixed range MTRRs. */
movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -121,7 +121,7 @@ clear_var_mtrrs:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index f54c691b9a..2d469ffa03 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -55,7 +55,7 @@ wait_for_sipi:
post_code(0x21)
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -111,7 +111,7 @@ clear_mtrrs:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
@@ -298,7 +298,7 @@ before_romstage:
cld
movl $CONFIG_RAMBASE, %esi
movl CBMEM_RESUME_BACKUP, %edi
- movl $HIGH_MEMORY_SAVE / 4, %ecx
+ movl $HIGH_MEMORY_SAVE >> 2, %ecx
rep movsl
__acpi_resume_backup_done:
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index d7d932e817..271b7568d9 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -40,7 +40,7 @@ cache_as_ram:
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -90,7 +90,7 @@ clear_mtrrs:
/* Clear the cache memory reagion. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
index 2e560d9416..86c10ce08d 100644
--- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
+++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
@@ -36,7 +36,7 @@ cache_as_ram:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
index 7c6a67faff..583ec5812b 100644
--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc
+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
@@ -82,7 +82,7 @@ wait_for_sipi:
/* Zero out all fixed range and variable range MTRRs. */
movl $fixed_mtrr_table, %esi
- movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi
+ movl $((fixed_mtrr_table_end - fixed_mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
1:
@@ -152,7 +152,7 @@ wait_for_sipi:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
xorl %eax, %eax
rep stosl
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index ba90c25c72..05d4889f3f 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -63,7 +63,7 @@ wait_for_sipi:
post_code(0x21)
/* Zero out all fixed range and variable range MTRRs. */
movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ movl $((mtrr_table_end - mtrr_table) >> 1), %edi
xorl %eax, %eax
xorl %edx, %edx
clear_mtrrs:
@@ -119,7 +119,7 @@ clear_mtrrs:
/* Clear the cache memory region. This will also fill up the cache */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
xorl %eax, %eax
rep stosl
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc
index 11f50dbae6..b0f4ee6a25 100644
--- a/src/vendorcode/amd/agesa/f10/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f10/gcccar.inc
@@ -1380,7 +1380,7 @@ SetupStack:
or %ah, %ah
jne 2f
# Is BSP, assign a 64K stack
- mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx
mov $BSP_STACK_BASE_ADDR, %ebp
jmp 0f
#.else # node 1 to 7, core0
@@ -1389,7 +1389,7 @@ SetupStack:
mov $AMD_MTRR_FIX16k_80000, %bx
shl $16, %ebx #
mov %ah, %bh # Node# is used as slot#
- mov $(CORE0_STACK_SIZE / 0x1000), %bl
+ mov $(CORE0_STACK_SIZE >> 12), %bl
mov %ah, %al # Base = (Node# * Size)#
mul %bl #
movzx %ax, %eax #
@@ -1411,7 +1411,7 @@ SetupStack:
mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
shr $4, %bh #
add $4, %bh #
- mov $(CORE1_STACK_SIZE / 0x1000), %bl
+ mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ...
movzx %ax, %eax #
diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc
index f6b08998de..147d16eba7 100644
--- a/src/vendorcode/amd/agesa/f12/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f12/gcccar.inc
@@ -1374,7 +1374,7 @@ SetupStack:
or %ah, %ah
jne 2f
# Is BSP, assign a 64K stack
- mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx
mov $BSP_STACK_BASE_ADDR, %ebp
jmp 0f
#.else # node 1 to 7, core0
@@ -1383,7 +1383,7 @@ SetupStack:
mov $AMD_MTRR_FIX16k_80000, %bx
shl $16, %ebx #
mov %ah, %bh # Node# is used as slot#
- mov $(CORE0_STACK_SIZE / 0x1000), %bl
+ mov $(CORE0_STACK_SIZE >> 12), %bl
mov %ah, %al # Base = (Node# * Size)#
mul %bl #
movzx %ax, %eax #
@@ -1405,7 +1405,7 @@ SetupStack:
mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
shr $4, %bh #
add $4, %bh #
- mov $(CORE1_STACK_SIZE / 0x1000), %bl
+ mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ...
movzx %ax, %eax #
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index f0a19019ce..2104c271cd 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -1388,7 +1388,7 @@ SetupStack:
or %ah, %ah
jne 2f
# Is BSP, assign a 64K stack
- mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx
mov $BSP_STACK_BASE_ADDR, %ebp
jmp 0f
#.else # node 1 to 7, core0
@@ -1397,7 +1397,7 @@ SetupStack:
mov $AMD_MTRR_FIX16k_80000, %bx
shl $16, %ebx #
mov %ah, %bh # Node# is used as slot#
- mov $(CORE0_STACK_SIZE / 0x1000), %bl
+ mov $(CORE0_STACK_SIZE >> 12), %bl
mov %ah, %al # Base = (Node# * Size)#
mul %bl #
movzx %ax, %eax #
@@ -1419,7 +1419,7 @@ SetupStack:
mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
shr $4, %bh #
add $4, %bh #
- mov $(CORE1_STACK_SIZE / 0x1000), %bl
+ mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ...
movzx %ax, %eax #
diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc
index c88709c7c4..1ccefcf0b9 100644
--- a/src/vendorcode/amd/agesa/f15/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15/gcccar.inc
@@ -1395,7 +1395,7 @@ SetupStack:
or %ah, %ah
jne 2f
# Is BSP, assign a 64K stack
- mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx
mov $BSP_STACK_BASE_ADDR, %ebp
jmp 0f
#.else # node 1 to 7, core0
@@ -1404,7 +1404,7 @@ SetupStack:
mov $AMD_MTRR_FIX16k_80000, %bx
shl $16, %ebx #
mov %ah, %bh # Node# is used as slot#
- mov $(CORE0_STACK_SIZE / 0x1000), %bl
+ mov $(CORE0_STACK_SIZE >> 12), %bl
mov %ah, %al # Base = (Node# * Size)#
mul %bl #
movzx %ax, %eax #
@@ -1426,7 +1426,7 @@ SetupStack:
mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
shr $4, %bh #
add $4, %bh #
- mov $(CORE1_STACK_SIZE / 0x1000), %bl
+ mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ...
movzx %ax, %eax #
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index d6c627850b..5118a4ca4a 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -1704,7 +1704,7 @@ SetupStack:
or %ah, %ah
jne 2f
# Is BSP, assign a 64K stack
- mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx
mov $BSP_STACK_BASE_ADDR, %ebp
jmp 0f
#.else # node 1 to 7, core0
@@ -1713,7 +1713,7 @@ SetupStack:
mov $AMD_MTRR_FIX16k_80000, %bx
shl $16, %ebx #
mov %ah, %bh # Node# is used as slot#
- mov $(CORE0_STACK_SIZE / 0x1000), %bl
+ mov $(CORE0_STACK_SIZE >> 12), %bl
mov %ah, %al # Base = (Node# * Size)#
mul %bl #
movzx %ax, %eax #
@@ -1735,7 +1735,7 @@ SetupStack:
mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
shr $4, %bh #
add $4, %bh #
- mov $(CORE1_STACK_SIZE / 0x1000), %bl
+ mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ...
movzx %ax, %eax #
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index 90c8cc6a68..862c8cbd81 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -1069,7 +1069,7 @@ SetupStack:
or %ah, %ah
jne 2f
# Is BSP, assign a 64K stack
- mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx
mov $BSP_STACK_BASE_ADDR, %ebp
jmp 0f
#.else # node 1 to 7, core0
@@ -1078,7 +1078,7 @@ SetupStack:
mov $AMD_MTRR_FIX16k_80000, %bx
shl $16, %ebx #
mov %ah, %bh # Node# is used as slot#
- mov $(CORE0_STACK_SIZE / 0x1000), %bl
+ mov $(CORE0_STACK_SIZE >> 12), %bl
mov %ah, %al # Base = (Node# * Size)#
mul %bl #
movzx %ax, %eax #
@@ -1100,7 +1100,7 @@ SetupStack:
mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
shr $4, %bh #
add $4, %bh #
- mov $(CORE1_STACK_SIZE / 0x1000), %bl
+ mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ...
movzx %ax, %eax #
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 12:06:35 +0000