diff options
| -rw-r--r-- | src/arch/i386/Config.lb | 6 | ||||
| -rw-r--r-- | src/cpu/p6/cpufixup.c | 43 | ||||
| -rw-r--r-- | src/mainboard/via/epia/Config.lb | 27 | ||||
| -rw-r--r-- | src/mainboard/via/epia/mainboard.c | 5 | ||||
| -rw-r--r-- | src/pc80/keyboard.c | 6 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/Config.lb | 2 | ||||
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231.c | 619 | ||||
| -rw-r--r-- | targets/via/epia/Config.lb | 6 |
8 files changed, 360 insertions, 354 deletions
diff --git a/src/arch/i386/Config.lb b/src/arch/i386/Config.lb index b43258b9d4..3e72425f27 100644 --- a/src/arch/i386/Config.lb +++ b/src/arch/i386/Config.lb @@ -1,3 +1,5 @@ +uses CONFIG_SMP + init config/crt0.base ldscript config/ldscript.lb @@ -37,4 +39,6 @@ addaction clean "rm -f romimage payload.*" dir lib dir boot -dir smp +if CONFIG_SMP + dir smp +end diff --git a/src/cpu/p6/cpufixup.c b/src/cpu/p6/cpufixup.c index f3d614b734..e5cd3fc017 100644 --- a/src/cpu/p6/cpufixup.c +++ b/src/cpu/p6/cpufixup.c @@ -1,18 +1,13 @@ /* microcode.c: Microcode update for PIII and later CPUS * - * $Id$ */ - -#ifndef lint -static char rcsid[] = "$Id$"; -#endif - -#include <pciconf.h> -#include <subr.h> +#include <console/console.h> +#include <mem.h> #include <cpu/p6/msr.h> -#include <printk.h> #include <cpu/p5/cpuid.h> -#include <cpu/cpufixup.h> +#include <cpu/k8/mtrr.h> +#include <device/device.h> +#include <device/chip.h> struct microcode { unsigned int hdrver; @@ -300,24 +295,33 @@ unsigned int microcode_updates [] = { 0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec, }; + static void display_cpuid_update_microcode(void) { unsigned int eax, ebx, ecx, edx; unsigned int pf, rev, sig, val[2]; unsigned int x86_model, x86_family, i; struct microcode *m; - + msr_t msr; /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ - wrmsr(0x8B, 0, 0); + //wrmsr(0x8B, 0, 0); + msr.lo = msr.hi = 0; + wrmsr(0x8b, msr); cpuid(1, &eax, &ebx, &ecx, &edx); - rdmsr(0x8B, val[0], rev); + //rdmsr(0x8B, val[0], rev); + msr = rdmsr(0x8b); + val[0] = msr.lo; + rev = msr.hi; x86_model = (eax >>4) & 0x0f; x86_family = (eax >>8) & 0x0f; sig = eax; pf = 0; if ((x86_model >= 5)||(x86_family>6)) { - rdmsr(0x17, val[0], val[1]); + //rdmsr(0x17, val[0], val[1]); + msr = rdmsr(0x17); + val[0] = msr.lo; + val[1] = msr.hi; pf = 1 << ((val[1] >> 18) & 7); } printk_debug("microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n", @@ -326,9 +330,16 @@ static void display_cpuid_update_microcode(void) m = (void *)µcode_updates; for(i = 0; i < sizeof(microcode_updates)/sizeof(struct microcode); i++) { if ((m[i].sig == sig) && (m[i].pf == pf)) { - wrmsr(0x79, (unsigned int)&m[i].bits, 0); + //wrmsr(0x79, (unsigned int)&m[i].bits, 0); + msr.lo = (unsigned int)&m[i].bits; + msr.hi = 0; + wrmsr(0x79, msr); + __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); - rdmsr(0x8B, val[0], val[1]); + //rdmsr(0x8B, val[0], val[1]); + msr = rdmsr(0x8b); + val[0] = msr.lo; + val[1] = msr.hi; printk_info("microcode updated from revision %d to %d\n", rev, val[1]); } diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb index 6d30820105..c4527cec17 100644 --- a/src/mainboard/via/epia/Config.lb +++ b/src/mainboard/via/epia/Config.lb @@ -14,6 +14,7 @@ uses PAYLOAD_SIZE uses _ROMBASE uses XIP_ROM_SIZE uses XIP_ROM_BASE +uses HAVE_MP_TABLE ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE 524288 @@ -28,6 +29,11 @@ default ROM_SIZE 524288 option HAVE_FALLBACK_BOOT=1 ## +## no MP table +## +option HAVE_MP_TABLE=0 + +## ## Build code to reset the motherboard from linuxBIOS ## option HAVE_HARD_RESET=1 @@ -37,12 +43,7 @@ option HAVE_HARD_RESET=1 ## option HAVE_PIRQ_TABLE=1 option IRQ_SLOT_COUNT=7 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -option HAVE_MP_TABLE=1 +object irq_tables.o ## ## Build code to export a CMOS option table @@ -50,18 +51,6 @@ option HAVE_MP_TABLE=1 option HAVE_OPTION_TABLE=1 ## -## Build code for SMP support -## Only worry about 2 micro processors -## -option CONFIG_SMP=1 -option CONFIG_MAX_CPUS=2 - -## -## Build code to setup a generic IOAPIC -## -option CONFIG_IOAPIC=1 - -## ## Clean up the motherboard id strings ## option MAINBOARD_PART_NUMBER="HDAMA" @@ -238,7 +227,7 @@ northbridge via/vt8601 "vt8601" end end -cpu p5 "cpu0" +cpu p6 "cpu0" end diff --git a/src/mainboard/via/epia/mainboard.c b/src/mainboard/via/epia/mainboard.c index 6790aaca1b..554c0d3336 100644 --- a/src/mainboard/via/epia/mainboard.c +++ b/src/mainboard/via/epia/mainboard.c @@ -7,7 +7,6 @@ #include <arch/io.h> #include <device/chip.h> -#include "../../../northbridge/amd/amdk8/northbridge.h" #include "chip.h" @@ -16,7 +15,7 @@ static struct device_operations mainboard_operations = { .set_resources = root_dev_set_resources, .enable_resources = enable_childrens_resources, .init = 0, - .scan_bus = vt8_scan_root_bus, + .scan_bus = pci_scan_bridge, .enable = 0, }; @@ -32,6 +31,6 @@ static void enumerate(struct chip *chip) } struct chip_control mainboard_via_epia_control = { .enumerate = enumerate, - .name = "Arima HDAMA mainboard ", + .name = "VIA EPIA mainboard ", }; diff --git a/src/pc80/keyboard.c b/src/pc80/keyboard.c index 9dc56b5698..a7ecf8cbd3 100644 --- a/src/pc80/keyboard.c +++ b/src/pc80/keyboard.c @@ -1,9 +1,5 @@ -#ifndef lint -static char rcsid[] = "$Id$"; -#endif - #include <arch/io.h> -#include <subr.h> + /* much better keyboard init courtesy ollie@sis.com.tw TODO: Typematic Setting, the keyboard is too slow for me */ void pc_keyboard_init() diff --git a/src/southbridge/via/vt8231/Config.lb b/src/southbridge/via/vt8231/Config.lb index adaa1218e9..b0b2ef5abf 100644 --- a/src/southbridge/via/vt8231/Config.lb +++ b/src/southbridge/via/vt8231/Config.lb @@ -1,2 +1,2 @@ config chip.h -object w83c553f.o +object vt8231.o diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index d1bb66ba64..f395b054fb 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -1,103 +1,111 @@ #include <arch/io.h> +#include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> #include <device/chip.h> #include <console/console.h> #include "vt8231.h" #include "chip.h" +void pc_keyboard_init(void); - -void usb_on(int enable) +void +hard_reset() { + printk_err("NO HARD RESET ON VT8231! FIX ME!\n"); +} +static void usb_on(int enable) { - unsigned char regval; - - /* Base 8231 controller */ - struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_8231, 0); - /* USB controller 1 */ - struct pci_dev *dev2 = pci_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_82C586_2, 0); - /* USB controller 2 */ - struct pci_dev *dev3 = pci_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_82C586_2, \ - dev2); - - /* enable USB1 */ - if(dev2) { - if (enable) { - pci_write_config_byte(dev2, 0x3c, 0x05); - pci_write_config_byte(dev2, 0x04, 0x07); - } else { - pci_write_config_byte(dev2, 0x3c, 0x00); - pci_write_config_byte(dev2, 0x04, 0x00); - } - } - - if(dev0) { - pci_read_config_byte(dev0, 0x50, ®val); - if (enable) - regval &= ~(0x10); - else - regval |= 0x10; - pci_write_config_byte(dev0, 0x50, regval); - } - - /* enable USB2 */ - if(dev3) { - if (enable) { - pci_write_config_byte(dev3, 0x3c, 0x05); - pci_write_config_byte(dev3, 0x04, 0x07); - } else { - pci_write_config_byte(dev3, 0x3c, 0x00); - pci_write_config_byte(dev3, 0x04, 0x00); - } - } - - if(dev0) { - pci_read_config_byte(dev0, 0x50, ®val); - if (enable) - regval &= ~(0x20); - else - regval |= 0x20; - pci_write_config_byte(dev0, 0x50, regval); - } + + unsigned char regval; + + /* Base 8231 controller */ + device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_8231, 0); + /* USB controller 1 */ + device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_82C586_2, 0); + /* USB controller 2 */ + device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_82C586_2, \ + dev2); + + /* enable USB1 */ + if(dev2) { + if (enable) { + pci_write_config8(dev2, 0x3c, 0x05); + pci_write_config8(dev2, 0x04, 0x07); + } else { + pci_write_config8(dev2, 0x3c, 0x00); + pci_write_config8(dev2, 0x04, 0x00); + } + } + + if(dev0) { + regval = pci_read_config8(dev0, 0x50); + if (enable) + regval &= ~(0x10); + else + regval |= 0x10; + pci_write_config8(dev0, 0x50, regval); + } + + /* enable USB2 */ + if(dev3) { + if (enable) { + pci_write_config8(dev3, 0x3c, 0x05); + pci_write_config8(dev3, 0x04, 0x07); + } else { + pci_write_config8(dev3, 0x3c, 0x00); + pci_write_config8(dev3, 0x04, 0x00); + } + } + + if(dev0) { + regval = pci_read_config8(dev0, 0x50); + if (enable) + regval &= ~(0x20); + else + regval |= 0x20; + pci_write_config8(dev0, 0x50, regval); + } } -void keyboard_on() +static void keyboard_on() { - unsigned char regval; + unsigned char regval; - /* Base 8231 controller */ - struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_8231, 0); + /* Base 8231 controller */ + device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_8231, 0); - /* kevinh/Ispiri - update entire function to use - new pci_write_config_byte */ + /* kevinh/Ispiri - update entire function to use + new pci_write_config8 */ - if (dev0) { - pci_read_config_byte(dev0, 0x51, ®val); - regval |= 0x0f; - pci_write_config_byte(dev0, 0x51, regval); - } - pc_keyboard_init(); + if (dev0) { + regval = pci_read_config8(dev0, 0x51); + regval |= 0x0f; + pci_write_config8(dev0, 0x51, regval); + } + pc_keyboard_init(); } -void nvram_on() +static void nvram_on() { - /* - * the VIA 8231 South has a very different nvram setup than the - * piix4e ... - * turn on ProMedia nvram. - * TO DO: use the PciWriteByte function here. - */ - - /* - * kevinh/Ispiri - I don't think this is the correct address/value - * intel_conf_writeb(0x80008841, 0xFF); - */ + /* + * the VIA 8231 South has a very different nvram setup than the + * piix4e ... + * turn on ProMedia nvram. + * TO DO: use the PciWriteByte function here. + */ + + /* + * kevinh/Ispiri - I don't think this is the correct address/value + * intel_conf_writeb(0x80008841, 0xFF); + */ } @@ -105,255 +113,256 @@ void nvram_on() * Enable the ethernet device and turn off stepping (because it is integrated * inside the southbridge) */ -void ethernet_fixup() +static void ethernet_fixup() { - struct pci_dev *dev, *edev; - u8 byte; - - printk_info("Ethernet fixup\n"); - - edev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0); - if (edev != NULL) { - printk_debug("Configuring VIA LAN\n"); - - /* We don't need stepping - though the device supports it */ - pci_read_config_byte(edev, PCI_COMMAND, &byte); - byte &= ~PCI_COMMAND_WAIT; - pci_write_config_byte(edev, PCI_COMMAND, byte); - } else { - printk_debug("VIA LAN not found\n"); - } + device_t edev; + uint8_t byte; + + printk_info("Ethernet fixup\n"); + + edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0); + if (edev) { + printk_debug("Configuring VIA LAN\n"); + + /* We don't need stepping - though the device supports it */ + byte = pci_read_config8(edev, PCI_COMMAND); + byte &= ~PCI_COMMAND_WAIT; + pci_write_config8(edev, PCI_COMMAND, byte); + } else { + printk_debug("VIA LAN not found\n"); + } } -void southbridge_fixup() +static void vt8231_init(struct southbridge_via_vt8231_config *conf) { - unsigned char enables; - struct pci_dev *dev0; - struct pci_dev *dev1; - struct pci_dev *devpwr; - - // to do: use the pcibios_find function here, instead of - // hard coding the devfn. - // done - kevinh/Ispiri - - /* Base 8231 controller */ - dev0 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - /* IDE controller */ - dev1 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, \ - 0); - /* Power management controller */ - devpwr = pci_find_device(PCI_VENDOR_ID_VIA, \ - PCI_DEVICE_ID_VIA_8231_4, 0); - - // enable the internal I/O decode - enables = pci_read_config_byte(dev0, 0x6C, &enables); - enables |= 0x80; - pci_write_config_byte(dev0, 0x6C, enables); - - // Map 4MB of FLASH into the address space - pci_write_config_byte(dev0, 0x41, 0x7f); - - // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI - // interrupts can be properly marked as level triggered. - enables = pci_read_config_byte(dev0, 0x40, &enables); enables |= 0x44; - pci_write_config_byte(dev0, 0x40, enables); - - // Set 0x42 to 0xf0 to match Award bios - enables = pci_read_config_byte(dev0, 0x42, &enables); - enables |= 0xf0; - pci_write_config_byte(dev0, 0x42, enables); - - // Set bit 3 of 0x4a, to match award (dummy pci request) - enables = pci_read_config_byte(dev0, 0x4a, &enables); - enables |= 0x08; - pci_write_config_byte(dev0, 0x4a, enables); - - // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) - enables = pci_read_config_byte(dev0, 0x4f, &enables); - enables |= 0x08; - pci_write_config_byte(dev0, 0x4f, enables); - - // Set 0x58 to 0x03 to match Award - pci_write_config_byte(dev0, 0x58, 0x03); - - // enable the ethernet/RTC - if(dev0) { - pci_read_config_byte(dev0, 0x51, &enables); - enables |= 0x18; - pci_write_config_byte(dev0, 0x51, enables); - } + unsigned char enables; + device_t dev0; + device_t dev1; + device_t devpwr; + + // to do: use the pcibios_find function here, instead of + // hard coding the devfn. + // done - kevinh/Ispiri + + /* Base 8231 controller */ + dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + /* IDE controller */ + dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, \ + 0); + /* Power management controller */ + devpwr = dev_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_8231_4, 0); + + // enable the internal I/O decode + enables = pci_read_config8(dev0, 0x6C); + enables |= 0x80; + pci_write_config8(dev0, 0x6C, enables); + + // Map 4MB of FLASH into the address space + pci_write_config8(dev0, 0x41, 0x7f); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config8(dev0, 0x40); + pci_write_config8(dev0, 0x40, enables); + + // Set 0x42 to 0xf0 to match Award bios + enables = pci_read_config8(dev0, 0x42); + enables |= 0xf0; + pci_write_config8(dev0, 0x42, enables); + + // Set bit 3 of 0x4a, to match award (dummy pci request) + enables = pci_read_config8(dev0, 0x4a); + enables |= 0x08; + pci_write_config8(dev0, 0x4a, enables); + + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) + enables = pci_read_config8(dev0, 0x4f); + enables |= 0x08; + pci_write_config8(dev0, 0x4f, enables); + + // Set 0x58 to 0x03 to match Award + pci_write_config8(dev0, 0x58, 0x03); + + // enable the ethernet/RTC + if(dev0) { + enables = pci_read_config8(dev0, 0x51); + enables |= 0x18; + pci_write_config8(dev0, 0x51, enables); + } - // enable com1 and com2. - if (conf->enable_com_ports) { - enables = pci_read_config_byte(dev0, 0x6e, &enables); - /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 - * is enable com port a as com1 kevinh/Ispiri - Old code - * thought 0x01 would make it com1, that was wrong /* - * enables = 0x80 | 0x10 | 0x8 ; pci_write_config_byte(dev0, - * 0x6e, enables); // note: this is also a redo of some port - * of assembly, but we want everything up. - */ - - /* set com1 to 115 kbaud not clear how to do this yet. - * forget it; done in assembly. - */ -#endif - - // enable IDE, since Linux won't do it. - // First do some more things to devfn (17,0) - // note: this should already be cleared, according to the book. - pci_read_config_byte(dev0, 0x50, &enables); - printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); - enables &= ~8; // need manifest constant here! - printk_debug("set IDE reg. 50 to 0x%x\n", enables); - pci_write_config_byte(dev0, 0x50, enables); - - // set default interrupt values (IDE) - pci_read_config_byte(dev0, 0x4c, &enables); - printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); - // clear out whatever was there. - enables &= ~0xf; - enables |= 4; - printk_debug("setting reg. 4c to 0x%x\n", enables); - pci_write_config_byte(dev0, 0x4c, enables); + // enable com1 and com2. + if (conf->enable_com_ports) { + enables = pci_read_config8(dev0, 0x6e); + + /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 + * is enable com port a as com1 kevinh/Ispiri - Old code + * thought 0x01 would make it com1, that was wrong enables = + * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e, + * enables); // note: this is also a redo of some port of + * assembly, but we want everything up. + */ + + /* set com1 to 115 kbaud not clear how to do this yet. + * forget it; done in assembly. + */ + + } + // enable IDE, since Linux won't do it. + // First do some more things to devfn (17,0) + // note: this should already be cleared, according to the book. + enables = pci_read_config8(dev0, 0x50); + printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); + enables &= ~8; // need manifest constant here! + printk_debug("set IDE reg. 50 to 0x%x\n", enables); + pci_write_config8(dev0, 0x50, enables); + + // set default interrupt values (IDE) + enables = pci_read_config8(dev0, 0x4c); + printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); + // clear out whatever was there. + enables &= ~0xf; + enables |= 4; + printk_debug("setting reg. 4c to 0x%x\n", enables); + pci_write_config8(dev0, 0x4c, enables); - // set up the serial port interrupts. - // com2 to 3, com1 to 4 - pci_write_config_byte(dev0, 0x46, 0x04); - pci_write_config_byte(dev0, 0x47, 0x03); - - // - // Power management setup - // - // Set ACPI base address to IO 0x4000 - pci_write_config_dword(devpwr, 0x48, 0x4001); - - // Enable ACPI access (and setup like award) - pci_write_config_byte(devpwr, 0x41, 0x84); - - // Set hardware monitor base address to IO 0x6000 - pci_write_config_dword(devpwr, 0x70, 0x6001); - - // Enable hardware monitor (and setup like award) - pci_write_config_byte(devpwr, 0x74, 0x01); - - // set IO base address to 0x5000 - pci_write_config_dword(devpwr, 0x90, 0x5001); - - // Enable SMBus - pci_write_config_byte(devpwr, 0xd2, 0x01); - - // - // IDE setup - // - if (conf->enable_native_ide) { - // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI - // interrupts. Using PCI ints confuses linux for some reason. + // set up the serial port interrupts. + // com2 to 3, com1 to 4 + pci_write_config8(dev0, 0x46, 0x04); + pci_write_config8(dev0, 0x47, 0x03); + + // + // Power management setup + // + // Set ACPI base address to IO 0x4000 + pci_write_config32(devpwr, 0x48, 0x4001); + + // Enable ACPI access (and setup like award) + pci_write_config8(devpwr, 0x41, 0x84); + + // Set hardware monitor base address to IO 0x6000 + pci_write_config32(devpwr, 0x70, 0x6001); + + // Enable hardware monitor (and setup like award) + pci_write_config8(devpwr, 0x74, 0x01); + + // set IO base address to 0x5000 + pci_write_config32(devpwr, 0x90, 0x5001); + + // Enable SMBus + pci_write_config8(devpwr, 0xd2, 0x01); + + // + // IDE setup + // + if (conf->enable_native_ide) { + // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI + // interrupts. Using PCI ints confuses linux for some reason. - pci_read_config_byte(dev1, 0x42, &enables); - printk_debug("enables in reg 0x42 0x%x\n", enables); - enables &= ~0xc0; // compatability mode - pci_write_config_byte(dev1, 0x42, enables); - pci_read_config_byte(dev1, 0x42, &enables); - printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); - } - - pci_read_config_byte(dev1, 0x40, &enables); - printk_debug("enables in reg 0x40 0x%x\n", enables); - enables |= 3; - pci_write_config_byte(dev1, 0x40, enables); - pci_read_config_byte(dev1, 0x40, &enables); - printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); - - // Enable prefetch buffers - pci_read_config_byte(dev1, 0x41, &enables); - enables |= 0xf0; - pci_write_config_byte(dev1, 0x41, enables); - - // Lower thresholds (cause award does it) - pci_read_config_byte(dev1, 0x43, &enables); - enables &= ~0x0f; - enables |= 0x05; - pci_write_config_byte(dev1, 0x43, enables); - - // PIO read prefetch counter (cause award does it) - pci_write_config_byte(dev1, 0x44, 0x18); - - // Use memory read multiple - pci_write_config_byte(dev1, 0x45, 0x1c); - - // address decoding. - // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - // kevinh@ispiri.com - the standard linux drivers seem ass slow when - // used in native mode - I've changed back to classic - pci_read_config_byte(dev1, 0x9, &enables); - printk_debug("enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. - if (conf->enable_native_ide) { - enables &= ~0xf; - // cf/cg silicon needs an 'f' here. - enables |= 0xf; - } else { - enables &= ~0x5; - } - - pci_write_config_byte(dev1, 0x9, enables); - pci_read_config_byte(dev1, 0x9, &enables); - printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. - pci_read_config_byte(dev1, 0x4, &enables); - printk_debug("command in reg 0x4 0x%x\n", enables); - enables |= 7; + enables = pci_read_config8(dev1, 0x42); + printk_debug("enables in reg 0x42 0x%x\n", enables); + enables &= ~0xc0; // compatability mode + pci_write_config8(dev1, 0x42, enables); + enables = pci_read_config8(dev1, 0x42); + printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); + } + + enables = pci_read_config8(dev1, 0x40); + printk_debug("enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pci_write_config8(dev1, 0x40, enables); + enables = pci_read_config8(dev1, 0x40); + printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); + + // Enable prefetch buffers + enables = pci_read_config8(dev1, 0x41); + enables |= 0xf0; + pci_write_config8(dev1, 0x41, enables); + + // Lower thresholds (cause award does it) + enables = pci_read_config8(dev1, 0x43); + enables &= ~0x0f; + enables |= 0x05; + pci_write_config8(dev1, 0x43, enables); + + // PIO read prefetch counter (cause award does it) + pci_write_config8(dev1, 0x44, 0x18); + + // Use memory read multiple + pci_write_config8(dev1, 0x45, 0x1c); + + // address decoding. + // we want "flexible", i.e. 1f0-1f7 etc. or native PCI + // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // used in native mode - I've changed back to classic + enables = pci_read_config8(dev1, 0x9); + printk_debug("enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. + if (conf->enable_native_ide) { + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; + } else { + enables &= ~0x5; + } + + pci_write_config8(dev1, 0x9, enables); + enables = pci_read_config8(dev1, 0x9); + printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); + + // standard bios sets master bit. + enables = pci_read_config8(dev1, 0x4); + printk_debug("command in reg 0x4 0x%x\n", enables); + enables |= 7; - // No need for stepping - kevinh@ispiri.com - enables &= ~0x80; - - pci_write_config_byte(dev1, 0x4, enables); - pci_read_config_byte(dev1, 0x4, &enables); - printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); - - if (! conf->enable_native_ide) { - // Use compatability mode - per award bios - pci_write_config_dword(dev1, 0x10, 0x0); - pci_write_config_dword(dev1, 0x14, 0x0); - pci_write_config_dword(dev1, 0x18, 0x0); - pci_write_config_dword(dev1, 0x1c, 0x0); + // No need for stepping - kevinh@ispiri.com + enables &= ~0x80; + + pci_write_config8(dev1, 0x4, enables); + enables = pci_read_config8(dev1, 0x4); + printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); + + if (! conf->enable_native_ide) { + // Use compatability mode - per award bios + pci_write_config32(dev1, 0x10, 0x0); + pci_write_config32(dev1, 0x14, 0x0); + pci_write_config32(dev1, 0x18, 0x0); + pci_write_config32(dev1, 0x1c, 0x0); - // Force interrupts to use compat mode - just like Award bios - pci_write_config_byte(dev1, 0x3d, 00); - pci_write_config_byte(dev1, 0x3c, 0xff); - } + // Force interrupts to use compat mode - just like Award bios + pci_write_config8(dev1, 0x3d, 00); + pci_write_config8(dev1, 0x3c, 0xff); + } - ethernet_fixup(); + ethernet_fixup(); - // Start the rtc - rtc_init(0); + // Start the rtc + rtc_init(0); } static void southbridge_init(struct chip *chip, enum chip_pass pass) { - struct southbridge_via_vt8231_config *conf = - (struct southbridge_via_vt8231_config *)chip->chip_info; + struct southbridge_via_vt8231_config *conf = + (struct southbridge_via_vt8231_config *)chip->chip_info; - switch (pass) { - case CONF_PASS_POST_PCI: - vt8231_init(conf); - break; + switch (pass) { + case CONF_PASS_POST_PCI: + vt8231_init(conf); + break; - default: - /* nothing yet */ - break; - } + default: + /* nothing yet */ + break; + } } struct chip_control southbridge_via_vt8231_control = { - enable: southbridge_init, - name: "VIA vt8231" + enable: southbridge_init, + name: "VIA vt8231" }; diff --git a/targets/via/epia/Config.lb b/targets/via/epia/Config.lb index da433f4486..d92f0c61ff 100644 --- a/targets/via/epia/Config.lb +++ b/targets/via/epia/Config.lb @@ -9,6 +9,7 @@ target epia uses ARCH uses CONFIG_COMPRESS uses CONFIG_IOAPIC +uses CONFIG_KEYBOARD uses CONFIG_ROM_STREAM uses CONFIG_ROM_STREAM_START uses CONFIG_UDELAY_TSC @@ -23,8 +24,6 @@ uses i686 uses INTEL_PPRO_MTRR uses HEAP_SIZE uses IRQ_SLOT_COUNT -uses k7 -uses k8 uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses CONFIG_SMP @@ -51,6 +50,7 @@ uses XIP_ROM_BASE uses LINUXBIOS_EXTRA_VERSION option CONFIG_CHIP_CONFIGURE=1 +option CONFIG_KEYBOARD=1 option MAXIMUM_CONSOLE_LOGLEVEL=8 option DEFAULT_CONSOLE_LOGLEVEL=8 @@ -61,8 +61,6 @@ option CONFIG_UDELAY_TSC=0 option i686=1 option i586=1 option INTEL_PPRO_MTRR=1 -option k7=1 -option k8=1 option ROM_SIZE=524288 |