diff options
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.h | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/lpc.c | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/lpc.c | 11 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/lpc.h | 2 |
4 files changed, 14 insertions, 8 deletions
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 28faea49fb..15738aaf48 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -56,6 +56,7 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; #define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 #ifdef __PRE_RAM__ void hudson_lpc_port80(void); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index b56fa382fb..86e937e569 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -23,6 +23,7 @@ #include <device/pnp.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> @@ -104,11 +105,12 @@ static void hudson_lpc_set_resources(struct device *dev) { struct resource *res; + /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); + res->base |= PCI_COMMAND_MEMORY; + pci_dev_set_resources(dev); - /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ - res = find_resource(dev, 0xA0); - pci_write_config32(dev, 0xA0, res->base | 1 << 1); } diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index caac5b14d2..44dd07dd83 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/pci.h> +#include <device/pci_def.h> #include <arch/ioapic.h> #include "lpc.h" #include <arch/io.h> @@ -32,7 +33,7 @@ void lpc_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ + pci_get_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); /* SPI ROM base address */ /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -61,11 +62,13 @@ void lpc_set_resources(struct device *dev) struct resource *res; printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); + + /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); + res->base |= PCI_COMMAND_MEMORY; + pci_dev_set_resources(dev); - /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ - res = find_resource(dev, SPIROM_BASE_ADDRESS); - pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 3d6a17a381..3fc8d39a10 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -20,7 +20,7 @@ #ifndef _SB800_LPC_H_ #define _SB800_LPC_H_ -#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); void lpc_set_resources(device_t dev); |