diff options
| -rw-r--r-- | src/ec/google/chromeec/Kconfig | 6 | ||||
| -rw-r--r-- | src/ec/google/chromeec/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/ec/google/chromeec/i2c_tunnel/Kconfig | 6 | ||||
| -rw-r--r-- | src/ec/google/chromeec/i2c_tunnel/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/ec/google/chromeec/i2c_tunnel/chip.h | 16 | ||||
| -rw-r--r-- | src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c | 71 |
6 files changed, 102 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 554677c387..461587800b 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -196,3 +196,9 @@ config EC_GOOGLE_CHROMEEC_SWITCHES help Enable support for Chrome OS mode switches provided by the Chrome OS EC. + +if EC_GOOGLE_CHROMEEC + +source "src/ec/google/chromeec/*/Kconfig" + +endif diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 590b131355..b11f5c8507 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y) +subdirs-y += i2c_tunnel + bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c diff --git a/src/ec/google/chromeec/i2c_tunnel/Kconfig b/src/ec/google/chromeec/i2c_tunnel/Kconfig new file mode 100644 index 0000000000..20169fde0f --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/Kconfig @@ -0,0 +1,6 @@ +config EC_GOOGLE_CHROMEEC_I2C_TUNNEL + bool + depends on HAVE_ACPI_TABLES + help + This enables the Cros EC I2C tunnel driver that is required to fill the + SSDT nodes for the I2C tunnel used by the mainboard. diff --git a/src/ec/google/chromeec/i2c_tunnel/Makefile.inc b/src/ec/google/chromeec/i2c_tunnel/Makefile.inc new file mode 100644 index 0000000000..85e0fba127 --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C_TUNNEL) += i2c_tunnel.c diff --git a/src/ec/google/chromeec/i2c_tunnel/chip.h b/src/ec/google/chromeec/i2c_tunnel/chip.h new file mode 100644 index 0000000000..01d52bd0b2 --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/chip.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef __EC_GOOGLE_CHROMEEC_I2C_TUNNEL__ +#define __EC_GOOGLE_CHROMEEC_I2C_TUNNEL__ + +struct ec_google_chromeec_i2c_tunnel_config { + /* ACPI device name */ + const char *name; + /* ACPI _UID */ + unsigned int uid; + /* EC I2C bus number we tunnel to on the other side. */ + unsigned int remote_bus; +}; + +#endif /* __EC_GOOGLE_CHROMEEC_I2C_TUNNEL__ */ diff --git a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c new file mode 100644 index 0000000000..51375f8f22 --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <string.h> +#include "chip.h" + +#define CROS_EC_I2C_TUNNEL_HID "GOOG0012" +#define CROS_EC_I2C_TUNNEL_DDN "Cros EC I2C Tunnel" + +static void crosec_i2c_tunnel_fill_ssdt(struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info; + struct acpi_dp *dsd; + + if (!dev->enabled || !scope || !cfg) + return; + + acpigen_write_scope(scope); + + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", CROS_EC_I2C_TUNNEL_HID); + acpigen_write_name_integer("_UID", cfg->uid); + acpigen_write_name_string("_DDN", CROS_EC_I2C_TUNNEL_DDN); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dsd, "google,remote-bus", cfg->remote_bus); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), CROS_EC_I2C_TUNNEL_DDN, + dev_path(dev)); +} + +static const char *crosec_i2c_tunnel_acpi_name(const struct device *dev) +{ + struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info; + static char name[5]; + + if (cfg->name) + return cfg->name; + + snprintf(name, sizeof(name), "TUN%X", dev->path.generic.id); + return name; +} + +static struct device_operations crosec_i2c_tunnel_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = crosec_i2c_tunnel_acpi_name, + .acpi_fill_ssdt = crosec_i2c_tunnel_fill_ssdt, + .scan_bus = scan_static_bus, +}; + +static void crosec_i2c_tunnel_enable(struct device *dev) +{ + dev->ops = &crosec_i2c_tunnel_ops; +} + +struct chip_operations ec_google_chromeec_i2c_tunnel_ops = { + CHIP_NAME("CrosEC I2C Tunnel Device") + .enable_dev = crosec_i2c_tunnel_enable +}; |