summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/mainboard/google/herobrine/Kconfig24
-rw-r--r--src/mainboard/google/herobrine/board.h21
-rw-r--r--src/mainboard/google/herobrine/bootblock.c12
-rw-r--r--src/mainboard/google/herobrine/chromeos.c32
4 files changed, 81 insertions, 8 deletions
diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig
index 5c7183f460..511e4cb297 100644
--- a/src/mainboard/google/herobrine/Kconfig
+++ b/src/mainboard/google/herobrine/Kconfig
@@ -5,7 +5,7 @@ if BOARD_GOOGLE_HEROBRINE_COMMON
config HEROBRINE_HAS_FINGERPRINT
bool
- default y if BOARD_GOOGLE_HEROBRINE
+ default y if BOARD_GOOGLE_HEROBRINE || BOARD_GOOGLE_HEROBRINE_REV0
default n
config BOARD_SPECIFIC_OPTIONS
@@ -24,7 +24,8 @@ config BOARD_SPECIFIC_OPTIONS
select SPI_FLASH_WINBOND
select SPI_FLASH_MACRONIX
select MAINBOARD_HAS_CHROMEOS
- select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_SENOR
+ select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_GOOGLE_PIGLIN || BOARD_GOOGLE_HOGLIN
+ select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_HEROBRINE_REV0 || BOARD_GOOGLE_HEROBRINE
select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_SENOR
config VBOOT
@@ -52,4 +53,23 @@ config MAINBOARD_PART_NUMBER
default "Piglin" if BOARD_GOOGLE_PIGLIN
default "Hoglin" if BOARD_GOOGLE_HOGLIN
+config DRIVER_TPM_I2C_BUS
+ depends on MAINBOARD_HAS_I2C_TPM_CR50
+ hex
+ default 0xC if BOARD_GOOGLE_HEROBRINE_REV0
+ default 0xE
+
+config DRIVER_TPM_I2C_ADDR
+ default 0x50
+
+config DRIVER_TPM_SPI_BUS
+ depends on MAINBOARD_HAS_SPI_TPM_CR50
+ hex
+ default 0xE
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+ hex
+ default 0x8 if BOARD_GOOGLE_HEROBRINE_REV0
+ default 0xA
+
endif # BOARD_GOOGLE_HEROBRINE_COMMON
diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h
index 9debfb8d6b..0f396bc816 100644
--- a/src/mainboard/google/herobrine/board.h
+++ b/src/mainboard/google/herobrine/board.h
@@ -7,13 +7,28 @@
#include <boardid.h>
#include <gpio.h>
+
+#if CONFIG(BOARD_GOOGLE_HEROBRINE_REV0)
+#define GPIO_EC_IN_RW GPIO(68)
+#define GPIO_AP_EC_INT GPIO(142)
+#define GPIO_H1_AP_INT GPIO(54)
+#elif CONFIG(BOARD_GOOGLE_SENOR)
+#define GPIO_EC_IN_RW dead_code_t(gpio_t)
+#define GPIO_AP_EC_INT dead_code_t(gpio_t)
+#define GPIO_H1_AP_INT dead_code_t(gpio_t)
+#else
+#define GPIO_EC_IN_RW GPIO(156)
+#define GPIO_AP_EC_INT GPIO(18)
+#define GPIO_H1_AP_INT GPIO(104)
+#endif
+
#define GPIO_SD_CD_L GPIO(91)
-#if CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN) || CONFIG(BOARD_GOOGLE_HOGLIN)
-#define USB_HUB_LDO_EN GPIO(157)
+#if CONFIG(BOARD_GOOGLE_HEROBRINE_REV0)
+#define USB_HUB_LDO_EN GPIO(24)
#else
/* For Herobrine board and all variants */
-#define USB_HUB_LDO_EN GPIO(24)
+#define USB_HUB_LDO_EN GPIO(157)
#endif
#define QCOM_SC7280_SKU1 0x0
diff --git a/src/mainboard/google/herobrine/bootblock.c b/src/mainboard/google/herobrine/bootblock.c
index 05e53a64bb..50ca0aa4e0 100644
--- a/src/mainboard/google/herobrine/bootblock.c
+++ b/src/mainboard/google/herobrine/bootblock.c
@@ -2,8 +2,20 @@
#include <bootblock_common.h>
#include "board.h"
+#include <soc/qupv3_i2c_common.h>
+#include <soc/qcom_qup_se.h>
+#include <soc/qupv3_spi_common.h>
void bootblock_mainboard_init(void)
{
setup_chromeos_gpios();
+
+ if (CONFIG(MAINBOARD_HAS_I2C_TPM_CR50))
+ i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */
+
+ if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50))
+ qup_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1010 * KHz); /* H1/TPM SPI */
+
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */
}
diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c
index 9faf4baf5f..4c37ef129c 100644
--- a/src/mainboard/google/herobrine/chromeos.c
+++ b/src/mainboard/google/herobrine/chromeos.c
@@ -3,9 +3,17 @@
#include <boot/coreboot_tables.h>
#include <bootmode.h>
#include "board.h"
+#include <security/tpm/tis.h>
void setup_chromeos_gpios(void)
{
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+ gpio_input_pullup(GPIO_EC_IN_RW);
+ gpio_input_pullup(GPIO_AP_EC_INT);
+ }
+ if (CONFIG(MAINBOARD_HAS_TPM2))
+ gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
+
gpio_input_pullup(GPIO_SD_CD_L);
if (CONFIG(HEROBRINE_HAS_FINGERPRINT)) {
@@ -17,9 +25,19 @@ void setup_chromeos_gpios(void)
void fill_lb_gpios(struct lb_gpios *gpios)
{
- struct lb_gpio chromeos_gpios[] = {
+ const struct lb_gpio chromeos_gpios[] = {
{GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L),
"SD card detect"},
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+ {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW),
+ "EC in RW"},
+ {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT),
+ "EC interrupt"},
+#endif
+#if CONFIG(MAINBOARD_HAS_TPM2)
+ {GPIO_H1_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_H1_AP_INT),
+ "TPM interrupt"},
+#endif
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
@@ -27,6 +45,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_ec_is_trusted(void)
{
- /* Stub GPIO. */
- return 0;
+ /* EC is trusted if not in RW. This is active low. */
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ return !!gpio_get(GPIO_EC_IN_RW);
+ else /* If no EC, always return true */
+ return 1;
+}
+
+int tis_plat_irq_status(void)
+{
+ return gpio_irq_status(GPIO_H1_AP_INT);
}