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-rw-r--r--src/mainboard/intel/adlrvp/include/baseboard/variants.h2
-rw-r--r--src/mainboard/intel/adlrvp/memory.c64
-rw-r--r--src/mainboard/intel/adlrvp/romstage_fsp_params.c1
-rw-r--r--src/mainboard/intel/adlrvp/spd/Makefile.inc2
-rw-r--r--src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex32
5 files changed, 100 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index 9ab05f6bb1..143679ac56 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -24,6 +24,8 @@ enum adl_boardid {
/* ADL-M LP4 and LP5 RVPs */
ADL_M_LP4 = 0x1,
ADL_M_LP5 = 0x2,
+ /* ADL-N LP5 RVP */
+ ADL_N_LP5 = 0x7,
};
/* The next set of functions return the gpio table and fill in the number of
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index f4ae5416d5..b917d98e10 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -290,6 +290,68 @@ static const struct mb_cfg adlm_lp5_mem_config = {
},
};
+static const struct mb_cfg adln_lp5_mem_config = {
+ .type = MEM_TYPE_LP5X,
+
+ /* DQ byte map */
+ .lpx_dq_map = {
+ .ddr0 = {
+ .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
+ .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
+ },
+ .ddr1 = {
+ .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
+ .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
+ },
+ .ddr2 = {
+ .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
+ .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
+ },
+ .ddr3 = {
+ .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
+ .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
+ },
+ .ddr4 = {
+ .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
+ .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
+ },
+ .ddr5 = {
+ .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
+ .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
+ },
+ .ddr6 = {
+ .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
+ .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
+ },
+ .ddr7 = {
+ .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
+ .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
+ },
+ },
+
+ /* DQS CPU<>DRAM map */
+ .lpx_dqs_map = {
+ .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+ },
+
+ .ect = true, /* Early Command Training */
+
+ .UserBd = BOARD_TYPE_ULT_ULX,
+
+ .LpDdrDqDqsReTraining = 1,
+
+ .lp5x_config = {
+ .ccc_config = 0xff,
+ },
+};
+
const struct mb_cfg *variant_memory_params(void)
{
int board_id = get_board_id();
@@ -311,6 +373,8 @@ const struct mb_cfg *variant_memory_params(void)
return &adlm_lp4_mem_config;
case ADL_M_LP5:
return &adlm_lp5_mem_config;
+ case ADL_N_LP5:
+ return &adln_lp5_mem_config;
default:
die("unsupported board id : 0x%x\n", board_id);
}
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 05d2a173ff..56bd0cd1b6 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -80,6 +80,7 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
case ADL_P_LP5_2:
case ADL_M_LP4:
case ADL_M_LP5:
+ case ADL_N_LP5:
memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated);
break;
default:
diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc
index 4cb0f98da1..96869f4870 100644
--- a/src/mainboard/intel/adlrvp/spd/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc
@@ -7,4 +7,4 @@ SPD_SOURCES += adlrvp_lp5 # 0b003
SPD_SOURCES += empty # 0b004
SPD_SOURCES += empty # 0b005
SPD_SOURCES += adlrvp_ddr5_mr # 0b006
-SPD_SOURCES += adlrvp_lp5 # 0b007
+SPD_SOURCES += adlrvp_n_lp5 # 0b007
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex
new file mode 100644
index 0000000000..88a1f1f473
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00
+48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
+03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-20 17:51:02 +0000