diff options
| -rw-r--r-- | src/drivers/generic/bayhub/bh720.c | 4 | ||||
| -rw-r--r-- | src/drivers/generic/bayhub/bh720.h | 11 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/mainboard.c | 38 |
3 files changed, 49 insertions, 4 deletions
diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index b689b679d0..044168366b 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -23,7 +23,7 @@ #include "chip.h" #include "bh720.h" -__attribute__((weak)) void bh720_driving_strength(struct device *dev) +__attribute__((weak)) void board_bh720(struct device *dev) { } @@ -55,7 +55,7 @@ static void bh720_init(struct device *dev) pci_read_config32(dev, BH720_LINK_CTRL)); } - bh720_driving_strength(dev); + board_bh720(dev); } static struct pci_operations pci_ops = { diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index b6fd2738cd..3a4b3b6f69 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -35,13 +35,20 @@ enum { BH720_MEM_RW_DATA = 0x200, BH720_MEM_RW_ADR = 0x204, + BH720_MEM_RW_READ = BIT(30), + BH720_MEM_RW_WRITE = BIT(31), BH720_MEM_ACCESS_EN = 0x208, - BH720_PCR = 0x304, + BH720_PCR_DrvStrength_PLL = 0x304, BH720_PCR_DATA_CMD_DRV_MAX = 7, BH720_PCR_CLK_DRV_MAX = 7, + BH720_PCR_EMMC_SETTING = 0x308, + BH720_PCR_EMMC_SETTING_1_8V = BIT(4), BH720_RTD3_L1 = 0x3e0, BH720_RTD3_L1_DISABLE_L1 = BIT(28), + + BH720_PCR_CSR = 0x3e4, + BH720_PCR_CSR_EMMC_MODE_SEL = BIT(22), }; -void bh720_driving_strength(struct device *dev); +void board_bh720(struct device *dev); diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index cf38b99073..3edcd65dc1 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -17,6 +17,8 @@ #include <baseboard/variants.h> #include <gpio.h> #include <variant/gpio.h> +#include <device/pci.h> +#include <drivers/generic/bayhub/bh720.h> uint8_t variant_board_sku(void) { @@ -35,3 +37,39 @@ void variant_mainboard_suspend_resume(void) gpio_set(GPIO_133, 0); } #endif + +void board_bh720(struct device *dev) +{ + u32 sdbar; + u32 bh720_pcr_data; + + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Bayhub SD base CLK 50MHz: case#1 PCR 0x3E4[22] = 0 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data & ~BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); +} |