diff options
| -rw-r--r-- | src/mainboard/google/veyron/Kconfig | 10 | ||||
| -rw-r--r-- | src/mainboard/google/veyron/boardid.c | 5 |
2 files changed, 14 insertions, 1 deletions
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 0bd1e2ef7b..2a16ff9d46 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -18,6 +18,16 @@ config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards if BOARD_GOOGLE_VEYRON +# Some Veyron boards incorrectly had their RAM code strapped with 100Kohm +# resistors. These get overpowered by the SoC's internal pull-downs, so we +# cannot read those pins as tri-state. They're restricted to binary RAM codes. +config VEYRON_FORCE_BINARY_RAM_CODE + bool + default y if BOARD_GOOGLE_VEYRON_JAQ + default y if BOARD_GOOGLE_VEYRON_JERRY + default y if BOARD_GOOGLE_VEYRON_MIGHTY + default n + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c index 47e946e635..8bd1d7665b 100644 --- a/src/mainboard/google/veyron/boardid.c +++ b/src/mainboard/google/veyron/boardid.c @@ -38,7 +38,10 @@ uint32_t ram_code(void) gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ - code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + if (IS_ENABLED(CONFIG_VEYRON_FORCE_BINARY_RAM_CODE)) + code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + else + code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); printk(BIOS_SPEW, "RAM Config: %u.\n", code); return code; |