diff options
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/early_fch.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/amd/picasso/early_fch.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 4 |
6 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 9a108c95fb..3d672d8de7 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -204,6 +204,14 @@ config DISABLE_SPI_FLASH_ROM_SHARING removes arbitration with board and assumes the chipset controls the SPI flash bus entirely. +config DISABLE_KEYBOARD_RESET_PIN + bool + help + Instruct the SoC to not use the state of GPIO_129 as keyboard reset + signal. When this pin is used as GPIO and the keyboard reset + functionality isn't disabled, configuring it as an output and driving + it as 0 will cause a reset. + menu "PSP Configuration Options" config AMD_FWM_POSITION_INDEX diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 4e7d84d389..0c72863ba3 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -52,6 +52,10 @@ void fch_pre_init(void) if (CONFIG(AMD_SOC_CONSOLE_UART)) set_uart_config(CONFIG_UART_FOR_CONSOLE); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); } /* After console init */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 1fca390fea..b6ab78494a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -320,6 +320,14 @@ config DISABLE_SPI_FLASH_ROM_SHARING removes arbitration with board and assumes the chipset controls the SPI flash bus entirely. +config DISABLE_KEYBOARD_RESET_PIN + bool + help + Instruct the SoC to not use the state of GPIO_129 as keyboard reset + signal. When this pin is used as GPIO and the keyboard reset + functionality isn't disabled, configuring it as an output and driving + it as 0 will cause a reset. + config MAINBOARD_POWER_RESTORE def_bool n help diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 1aff83b5c8..63e192fa7f 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -62,6 +62,10 @@ void fch_pre_init(void) if (CONFIG(AMD_SOC_CONSOLE_UART)) set_uart_config(CONFIG_UART_FOR_CONSOLE); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); } /* After console init */ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 5f1b65a476..adce99cfae 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -371,6 +371,14 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 +config DISABLE_KEYBOARD_RESET_PIN + bool + help + Instruct the SoC to not use the state of GPIO_129 as keyboard reset + signal. When this pin is used as GPIO and the keyboard reset + functionality isn't disabled, configuring it as an output and driving + it as 0 will cause a reset. + config MAINBOARD_POWER_RESTORE def_bool n help diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 161e3e8897..28310ce709 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -344,6 +344,10 @@ void bootblock_fch_early_init(void) fch_enable_legacy_io(); enable_aoac_devices(); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); } /* After console init */ |