diff options
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h | 78 |
1 files changed, 44 insertions, 34 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h index b7cb818e4d..05fffb4177 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h @@ -1555,7 +1555,17 @@ typedef struct { /** Offset 0x06A0 - Reserved **/ - UINT8 Reserved27[10]; + UINT8 Reserved27[7]; + +/** Offset 0x06A7 - VccIn Aux Imon slope correction + PCODE MMIO Mailbox: VccIn Aux Imon slope correction. <b>0 - Auto</b> Specified in + 1/100 increment values. Range is 0-200. 125 = 1.25 +**/ + UINT8 VccInAuxImonSlope; + +/** Offset 0x06A8 - Reserved +**/ + UINT8 Reserved28[2]; /** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b> @@ -1564,7 +1574,7 @@ typedef struct { /** Offset 0x06AB - Reserved **/ - UINT8 Reserved28[13]; + UINT8 Reserved29[13]; /** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1587,7 +1597,7 @@ typedef struct { /** Offset 0x06BC - Reserved **/ - UINT8 Reserved29[2]; + UINT8 Reserved30[2]; /** Offset 0x06BE - Min Voltage for C8 PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = @@ -1621,7 +1631,7 @@ typedef struct { /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved31; /** Offset 0x06CA - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. This value @@ -1632,7 +1642,7 @@ typedef struct { /** Offset 0x06CB - Reserved **/ - UINT8 Reserved31[32]; + UINT8 Reserved32[32]; /** Offset 0x06EB - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1826,7 +1836,7 @@ typedef struct { /** Offset 0x0894 - Reserved **/ - UINT8 Reserved32; + UINT8 Reserved33; /** Offset 0x0895 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1836,7 +1846,7 @@ typedef struct { /** Offset 0x0896 - Reserved **/ - UINT8 Reserved33[2]; + UINT8 Reserved34[2]; /** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer @@ -1846,7 +1856,7 @@ typedef struct { /** Offset 0x089C - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved35; /** Offset 0x089D - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; @@ -1878,7 +1888,7 @@ typedef struct { /** Offset 0x0929 - Reserved **/ - UINT8 Reserved35[28]; + UINT8 Reserved36[28]; /** Offset 0x0945 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. @@ -1936,7 +1946,7 @@ typedef struct { /** Offset 0x09A1 - Reserved **/ - UINT8 Reserved36[3]; + UINT8 Reserved37[3]; /** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset Allows to select the downstream port preset value that will be used during phase @@ -2225,7 +2235,7 @@ typedef struct { /** Offset 0x0A45 - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved38; /** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2400,7 +2410,7 @@ typedef struct { /** Offset 0x0A6B - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved39; /** Offset 0x0A6C - Thermal Device Temperature Decides the temperature. @@ -2425,7 +2435,7 @@ typedef struct { /** Offset 0x0A89 - Reserved **/ - UINT8 Reserved39[3]; + UINT8 Reserved40[3]; /** Offset 0x0A8C - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2475,7 +2485,7 @@ typedef struct { /** Offset 0x0A9C - Reserved **/ - UINT8 Reserved40[4]; + UINT8 Reserved41[4]; /** Offset 0x0AA0 - BgpdtHash[4] BgpdtHash values @@ -2489,7 +2499,7 @@ typedef struct { /** Offset 0x0AC4 - Reserved **/ - UINT8 Reserved41[4]; + UINT8 Reserved42[4]; /** Offset 0x0AC8 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2522,7 +2532,7 @@ typedef struct { /** Offset 0x0ADB - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved43; /** Offset 0x0ADC - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only @@ -2622,7 +2632,7 @@ typedef struct { /** Offset 0x0B00 - Reserved **/ - UINT8 Reserved43[12]; + UINT8 Reserved44[12]; /** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. @@ -2715,7 +2725,7 @@ typedef struct { /** Offset 0x0BD1 - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved45[3]; /** Offset 0x0BD4 - CPU PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This @@ -2992,7 +3002,7 @@ typedef struct { /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved45[2]; + UINT8 Reserved46[2]; /** Offset 0x0CA4 - LogoPixelHeight Address Address of LogoPixelHeight @@ -3006,7 +3016,7 @@ typedef struct { /** Offset 0x0CAC - Reserved **/ - UINT8 Reserved46[5]; + UINT8 Reserved47[5]; /** Offset 0x0CB1 - RSR feature Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b> @@ -3016,7 +3026,7 @@ typedef struct { /** Offset 0x0CB2 - Reserved **/ - UINT8 Reserved47[4]; + UINT8 Reserved48[4]; /** Offset 0x0CB6 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> @@ -3409,7 +3419,7 @@ typedef struct { /** Offset 0x0D2D - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved49; /** Offset 0x0D2E - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. @@ -3449,7 +3459,7 @@ typedef struct { /** Offset 0x0D3A - Reserved **/ - UINT8 Reserved49[2]; + UINT8 Reserved50[2]; /** Offset 0x0D3C - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. @@ -3552,7 +3562,7 @@ typedef struct { /** Offset 0x0D73 - Reserved **/ - UINT8 Reserved50[4]; + UINT8 Reserved51[4]; /** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b> @@ -3624,7 +3634,7 @@ typedef struct { /** Offset 0x0D82 - Reserved **/ - UINT8 Reserved51; + UINT8 Reserved52; /** Offset 0x0D83 - Dual Tau Boost Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0: @@ -3635,7 +3645,7 @@ typedef struct { /** Offset 0x0D84 - Reserved **/ - UINT8 Reserved52[32]; + UINT8 Reserved53[32]; /** Offset 0x0DA4 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3684,7 +3694,7 @@ typedef struct { /** Offset 0x0DAB - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved54; /** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -3836,7 +3846,7 @@ typedef struct { /** Offset 0x0F96 - Reserved **/ - UINT8 Reserved54[16]; + UINT8 Reserved55[16]; /** Offset 0x0FA6 - FOMS Control Policy Choose the Foms Control Policy, <b>Default = 0 </b> @@ -3858,7 +3868,7 @@ typedef struct { /** Offset 0x0FAF - Reserved **/ - UINT8 Reserved55[33]; + UINT8 Reserved56[33]; /** Offset 0x0FD0 - FspEventHandler <b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER. @@ -3885,7 +3895,7 @@ typedef struct { /** Offset 0x0FD7 - Reserved **/ - UINT8 Reserved56; + UINT8 Reserved57; /** Offset 0x0FD8 - Emmc Tx CMD Delay control register value Please see Tx CMD Delay Control register definition for help @@ -3919,7 +3929,7 @@ typedef struct { /** Offset 0x0FF0 - Reserved **/ - UINT8 Reserved57[69]; + UINT8 Reserved58[69]; /** Offset 0x1035 - Enable VMD Global Mapping Enable/disable to VMD controller.0: Disable; 1: Enable(Default) @@ -3929,7 +3939,7 @@ typedef struct { /** Offset 0x1036 - Reserved **/ - UINT8 Reserved58[122]; + UINT8 Reserved59[138]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3948,11 +3958,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x10B0 +/** Offset 0x10C0 **/ UINT8 UnusedUpdSpace45[6]; -/** Offset 0x10B6 +/** Offset 0x10C6 **/ UINT16 UpdTerminator; } FSPS_UPD; |