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-rw-r--r--Documentation/security/vboot/list_vboot.md1
-rw-r--r--src/mainboard/google/brox/Kconfig1
-rw-r--r--src/mainboard/google/brya/Kconfig11
-rw-r--r--src/mainboard/google/brya/Kconfig.name3
-rw-r--r--src/mainboard/google/brya/variants/primus4es/Makefile.inc6
-rw-r--r--src/mainboard/google/brya/variants/primus4es/fw_config.c91
-rw-r--r--src/mainboard/google/brya/variants/primus4es/gpio.c176
-rw-r--r--src/mainboard/google/brya/variants/primus4es/include/variant/ec.h11
-rw-r--r--src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h13
-rw-r--r--src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc9
-rw-r--r--src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt13
-rw-r--r--src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt7
-rw-r--r--src/mainboard/google/brya/variants/primus4es/overridetree.cb428
-rw-r--r--src/mainboard/google/brya/variants/primus4es/variant.c58
14 files changed, 0 insertions, 828 deletions
diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
index cbdf1357ce..4ebee573b0 100644
--- a/Documentation/security/vboot/list_vboot.md
+++ b/Documentation/security/vboot/list_vboot.md
@@ -66,7 +66,6 @@
- Osiris
- Pirrha
- Primus
-- Primus4ES
- Pujjo
- Quandiso
- Redrix
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index ce0f2e04c2..18a657545c 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -132,7 +132,6 @@ config HAVE_PCIE_WWAN
def_bool n
config USE_PM_ACPI_TIMER
- default y if BOARD_GOOGLE_PRIMUS4ES
default n
config MEMORY_SODIMM
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index be4e69466b..e2357f4866 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -332,13 +332,6 @@ config BOARD_GOOGLE_PRIMUS
select HAVE_WWAN_POWER_SEQUENCE
select INTEL_GMA_HAVE_VBT
-config BOARD_GOOGLE_PRIMUS4ES
- select BOARD_GOOGLE_BASEBOARD_BRYA
- select DEFAULT_ADL_NEM
- select DRIVERS_GENESYSLOGIC_GL9755
- select HAVE_PCIE_WWAN
- select HAVE_WWAN_POWER_SEQUENCE
-
config BOARD_GOOGLE_PUJJO
select BOARD_GOOGLE_BASEBOARD_NISSA
select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -539,7 +532,6 @@ config DRIVER_TPM_I2C_BUS
default 0x1 if BOARD_GOOGLE_BRYA0
default 0x1 if BOARD_GOOGLE_BRASK
default 0x1 if BOARD_GOOGLE_PRIMUS
- default 0x3 if BOARD_GOOGLE_PRIMUS4ES
default 0x1 if BOARD_GOOGLE_GIMBLE
default 0x3 if BOARD_GOOGLE_GIMBLE4ES
default 0x1 if BOARD_GOOGLE_REDRIX
@@ -621,7 +613,6 @@ config MAINBOARD_PART_NUMBER
default "Brya" if BOARD_GOOGLE_BRYA0
default "Brask" if BOARD_GOOGLE_BRASK
default "Primus" if BOARD_GOOGLE_PRIMUS
- default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES
default "Gimble" if BOARD_GOOGLE_GIMBLE
default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES
default "Redrix" if BOARD_GOOGLE_REDRIX
@@ -675,7 +666,6 @@ config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
default "brask" if BOARD_GOOGLE_BRASK
default "primus" if BOARD_GOOGLE_PRIMUS
- default "primus4es" if BOARD_GOOGLE_PRIMUS4ES
default "gimble" if BOARD_GOOGLE_GIMBLE
default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES
default "redrix" if BOARD_GOOGLE_REDRIX
@@ -749,7 +739,6 @@ config HAVE_PCIE_WWAN
def_bool n
config USE_PM_ACPI_TIMER
- default y if BOARD_GOOGLE_PRIMUS4ES
default n
config DEFAULT_ADL_NEM
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index bb6a4d2da5..efbdd1af20 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -96,9 +96,6 @@ config BOARD_GOOGLE_PIRRHA
config BOARD_GOOGLE_PRIMUS
bool "-> Primus"
-config BOARD_GOOGLE_PRIMUS4ES
- bool "-> Primus4ES"
-
config BOARD_GOOGLE_PUJJO
bool "-> Pujjo"
diff --git a/src/mainboard/google/brya/variants/primus4es/Makefile.inc b/src/mainboard/google/brya/variants/primus4es/Makefile.inc
deleted file mode 100644
index 725b883fba..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/Makefile.inc
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-bootblock-y += gpio.c
-romstage-y += gpio.c
-ramstage-y += gpio.c
-ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
-ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/primus4es/fw_config.c b/src/mainboard/google/brya/variants/primus4es/fw_config.c
deleted file mode 100644
index c9b4a38be5..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/fw_config.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootstate.h>
-#include <console/console.h>
-#include <fw_config.h>
-#include <gpio.h>
-
-static const struct pad_config dmic_enable_pads[] = {
- PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */
- PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */
- PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */
- PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */
-};
-
-static const struct pad_config dmic_disable_pads[] = {
- PAD_NC(GPP_R4, NONE),
- PAD_NC(GPP_R5, NONE),
- PAD_NC(GPP_R6, NONE),
- PAD_NC(GPP_R7, NONE),
-};
-
-static const struct pad_config i2s_enable_pads[] = {
- PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
- PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
- PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
- PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
- PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */
- PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */
- PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */
- PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
-};
-
-static const struct pad_config i2s_disable_pads[] = {
- PAD_NC(GPP_R0, NONE),
- PAD_NC(GPP_R1, NONE),
- PAD_NC(GPP_R2, NONE),
- PAD_NC(GPP_R3, NONE),
- PAD_NC(GPP_S0, NONE),
- PAD_NC(GPP_S1, NONE),
- PAD_NC(GPP_S2, NONE),
- PAD_NC(GPP_S3, NONE),
-};
-
-static const struct pad_config bt_i2s_enable_pads[] = {
- PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
- PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
- PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
- PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
- PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
- PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
- PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
- PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
-};
-
-static const struct pad_config bt_i2s_disable_pads[] = {
- PAD_NC(GPP_VGPIO_30, NONE),
- PAD_NC(GPP_VGPIO_31, NONE),
- PAD_NC(GPP_VGPIO_32, NONE),
- PAD_NC(GPP_VGPIO_33, NONE),
- PAD_NC(GPP_VGPIO_34, NONE),
- PAD_NC(GPP_VGPIO_35, NONE),
- PAD_NC(GPP_VGPIO_36, NONE),
- PAD_NC(GPP_VGPIO_37, NONE),
-};
-
-
-static void fw_config_handle(void *unused)
-{
- if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
- printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
- gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
- gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
- gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
- return;
- }
-
- if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
- printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n");
- gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
- gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
- gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
- }
-
- if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) {
- printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I-VS.\n");
- gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
- gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
- gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
- }
-}
-BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c
deleted file mode 100644
index 5b04d1fc5d..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/gpio.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <commonlib/helpers.h>
-#include <soc/gpio.h>
-
-/* Pad configuration in ramstage */
-static const struct pad_config override_gpio_table[] = {
- /* A6 : ESPI_ALERT1# ==> NC */
- PAD_NC(GPP_A6, NONE),
- /* A7 : SRCCLK_OE7# ==> NC */
- PAD_NC(GPP_A7, NONE),
- /* A14 : USB_OC1# ==> NC */
- PAD_NC(GPP_A14, NONE),
- /* A15 : USB_OC2# ==> NC */
- PAD_NC(GPP_A15, NONE),
- /* A21 : DDPC_CTRCLK ==> NC */
- PAD_NC(GPP_A21, NONE),
- /* A22 : DDPC_CTRLDATA ==> NC */
- PAD_NC(GPP_A22, NONE),
-
- /* B2 : VRALERT# ==> NC */
- PAD_NC(GPP_B2, NONE),
- /* B3 : PROC_GP2 ==> eMMC_PERST_L */
- PAD_CFG_GPO(GPP_B3, 1, DEEP),
- /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
- PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
- /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
- PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
- /* B15 : TIME_SYNC0 ==> NC */
- PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
-
- /* C3 : SML0CLK ==> NC */
- PAD_NC(GPP_C3, NONE),
- /* C4 : SML0DATA ==> NC */
- PAD_NC(GPP_C4, NONE),
-
- /* D3 : ISH_GP3 ==> NC */
- PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
- /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
- PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
- /* D6 : SRCCLKREQ1# ==> NC */
- PAD_NC(GPP_D6, NONE),
- /* D13 : ISH_UART0_RXD ==> NC */
- PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
- /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */
- PAD_CFG_GPO_LOCK(GPP_D14, 1, LOCK_CONFIG),
- /* D18 : UART1_TXD ==> SD_PE_RST_L */
- PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG),
-
- /* E3 : PROC_GP0 ==> NC */
- PAD_NC(GPP_E3, NONE),
- /* E7 : PROC_GP1 ==> NC */
- PAD_NC(GPP_E7, NONE),
- /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
- PAD_CFG_GPO(GPP_E20, 1, DEEP),
- /* E21 : DDP2_CTRLDATA ==> NC */
- PAD_NC(GPP_E21, NONE),
-
- /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
- PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
- /* F20 : EXT_PWR_GATE# ==> NC */
- PAD_NC(GPP_F20, NONE),
-
- /* H19 : SRCCLKREQ4# ==> NC */
- PAD_NC(GPP_H19, NONE),
- /* H21 : IMGCLKOUT2 ==> NC */
- PAD_NC(GPP_H21, NONE),
- /* H22 : IMGCLKOUT3 ==> NC */
- PAD_NC(GPP_H22, NONE),
- /* H23 : SRCCLKREQ5# ==> NC */
- PAD_NC(GPP_H23, NONE),
-
- /* S6 : SNDW3_CLK ==> NC */
- PAD_NC(GPP_S6, NONE),
- /* S7 : SNDW3_DATA ==> NC */
- PAD_NC(GPP_S7, NONE),
-
- /* T2 : GPP_T2 ==> eMMC_CFG */
- PAD_CFG_GPI(GPP_T2, NONE, DEEP),
-
- /* GPD11: LANPHYC ==> NC */
- PAD_NC(GPD11, NONE),
-};
-
-/* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
- /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
- PAD_CFG_GPO(GPP_A12, 1, DEEP),
- /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
- /* B3 : PROC_GP2 ==> eMMC_PERST_L */
- PAD_CFG_GPO(GPP_B3, 0, DEEP),
- /* B4 : PROC_GP3 ==> SSD_PERST_L */
- PAD_CFG_GPO(GPP_B4, 0, DEEP),
- /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
- PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
- /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
- PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
- /*
- * D1 : ISH_GP1 ==> FP_RST_ODL
- * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
- * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
- * early on in bootblock, followed by enabling of power. Reset signal is deasserted
- * later on in ramstage. Since reset signal is asserted in bootblock, it results in
- * FPMCU not working after a S3 resume. This is a known issue.
- */
- PAD_CFG_GPO(GPP_D1, 0, DEEP),
- /* D2 : ISH_GP2 ==> EN_FP_PWR */
- PAD_CFG_GPO(GPP_D2, 1, DEEP),
- /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
- PAD_CFG_GPO(GPP_D11, 1, DEEP),
- /* D18 : UART1_TXD ==> SD_PE_RST_L */
- PAD_CFG_GPO(GPP_D18, 0, PLTRST),
- /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage)*/
- PAD_CFG_GPO(GPP_E0, 0, DEEP),
- /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
- PAD_CFG_GPI(GPP_E13, NONE, DEEP),
- /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage)*/
- PAD_CFG_GPO(GPP_E16, 0, DEEP),
- /* E15 : RSVD_TP ==> PCH_WP_OD */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
- /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
- PAD_CFG_GPO(GPP_E20, 1, DEEP),
- /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
- PAD_CFG_GPO(GPP_F21, 0, DEEP),
- /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
- PAD_CFG_GPI(GPP_F18, NONE, DEEP),
- /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
- PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
- /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
- PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
- /* H13 : I2C7_SCL ==> EN_PP3300_SD */
- PAD_CFG_GPO(GPP_H13, 1, PLTRST),
-};
-
-static const struct pad_config romstage_gpio_table[] = {
- /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */
- PAD_CFG_GPO(GPP_A12, 1, DEEP),
-
- /* B4 : PROC_GP3 ==> SSD_PERST_L */
- PAD_CFG_GPO(GPP_B4, 1, DEEP),
-
- /* Enable touchscreen, hold in reset */
- /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
- PAD_CFG_GPO(GPP_C0, 1, DEEP),
- /* C1 : SMBDATA ==> USI_RST_L */
- PAD_CFG_GPO(GPP_C1, 0, DEEP),
-
- /* D1 : ISH_GP1 ==> FP_RST_ODL */
- PAD_CFG_GPO(GPP_D1, 0, DEEP),
- /* D2 : ISH_GP2 ==> EN_FP_PWR */
- PAD_CFG_GPO(GPP_D2, 0, DEEP),
-
- /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
- PAD_CFG_GPO(GPP_F21, 1, DEEP),
-};
-
-const struct pad_config *variant_gpio_override_table(size_t *num)
-{
- *num = ARRAY_SIZE(override_gpio_table);
- return override_gpio_table;
-}
-
-const struct pad_config *variant_early_gpio_table(size_t *num)
-{
- *num = ARRAY_SIZE(early_gpio_table);
- return early_gpio_table;
-}
-
-const struct pad_config *variant_romstage_gpio_table(size_t *num)
-{
- *num = ARRAY_SIZE(romstage_gpio_table);
- return romstage_gpio_table;
-}
diff --git a/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h b/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h
deleted file mode 100644
index 7309098359..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef __VARIANT_EC_H__
-#define __VARIANT_EC_H__
-
-#include <baseboard/ec.h>
-
-/* Enable PS/2 Mouse */
-#define SIO_EC_ENABLE_PS2M
-
-#endif
diff --git a/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h
deleted file mode 100644
index cbf6040265..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <baseboard/gpio.h>
-#define WWAN_FCPO GPP_F21
-#define WWAN_RST GPP_E16
-#define WWAN_PERST GPP_E0
-#define T1_OFF_MS 16
-#define T2_OFF_MS 2
-
-#endif
diff --git a/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc
deleted file mode 100644
index d2fae296db..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/primus/memory src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt
-
-SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B
-SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 1(0b0001) Parts = H9HCNNNFAMMLXR-NEE
-SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B, K4UBE3D4AA-MGCR
diff --git a/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt
deleted file mode 100644
index cdaaac01c6..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# This is an auto-generated file. Do not edit!!
-# Generated by:
-# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/primus/memory src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt
-
-DRAM Part Name ID to assign
-H9HCNNNBKMMLXR-NEE 0 (0000)
-H9HCNNNFAMMLXR-NEE 1 (0001)
-H9HCNNNCPMMLXR-NEE 2 (0010)
-K4U6E3S4AA-MGCR 0 (0000)
-MT53E512M32D1NP-046 WT:B 0 (0000)
-MT53E1G32D2NP-046 WT:B 2 (0010)
-K4UBE3D4AA-MGCR 2 (0010)
diff --git a/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt
deleted file mode 100644
index bb14464356..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-H9HCNNNBKMMLXR-NEE
-H9HCNNNFAMMLXR-NEE
-H9HCNNNCPMMLXR-NEE
-K4U6E3S4AA-MGCR
-MT53E512M32D1NP-046 WT:B
-MT53E1G32D2NP-046 WT:B
-K4UBE3D4AA-MGCR
diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
deleted file mode 100644
index baec228750..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb
+++ /dev/null
@@ -1,428 +0,0 @@
-fw_config
- field DB_USB 0 3
- option USB_ABSENT 0
- option USB3_PS8811 1
- end
- field DB_SD 4 5
- option SD_ABSENT 0
- option SD_GL9755S 1
- end
- field KB_BL 7 7
- option KB_BL_ABSENT 0
- option KB_BL_PRESENT 1
- end
- field AUDIO 8 10
- option AUDIO_UNKNOWN 0
- option MAX98360_ALC5682I_I2S 1
- option MAX98360_ALC5682I_VS_I2S 2
- end
- field DB_LTE 11 12
- option LTE_ABSENT 0
- option LTE_USB 1
- end
-end
-
-chip soc/intel/alderlake
- register "sagv" = "SaGv_Enabled"
- register "max_dram_speed_mts" = "3733"
-
- # Acoustic settings
- register "acoustic_noise_mitigation" = "1"
- register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
- register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
- register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
- register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
-
- # Intel Common SoC Config
- #+-------------------+---------------------------+
- #| Field | Value |
- #+-------------------+---------------------------+
- #| GSPI1 | Fingerprint MCU |
- #| I2C0 | Audio |
- #| I2C1 | Touchscreen |
- #| I2C2 | |
- #| I2C3 | cr50 TPM. Early init is |
- #| | required to set up a BAR |
- #| | for TPM communication |
- #| I2C5 | Trackpad |
- #+-------------------+---------------------------+
- register "common_soc_config" = "{
- .i2c[0] = {
- .speed = I2C_SPEED_FAST,
- },
- .i2c[1] = {
- .speed = I2C_SPEED_FAST,
- },
- .i2c[2] = {
- .speed = I2C_SPEED_FAST,
- },
- .i2c[3] = {
- .early_init = 1,
- .speed = I2C_SPEED_FAST,
- },
- .i2c[5] = {
- .speed = I2C_SPEED_FAST,
- },
- }"
-
- register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
- register "usb3_ports[2]" = "USB3_PORT_EMPTY"
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
-
- device domain 0 on
- device ref igpu on
- chip drivers/gfx/generic
- register "device_count" = "6"
- # DDIA for eDP
- register "device[0].name" = ""LCD""
- # DDIB for HDMI
- register "device[1].name" = ""DD01""
- # TCP0 (DP-1) for port C0
- register "device[2].name" = ""DD02""
- register "device[2].use_pld" = "true"
- register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))"
- # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
- register "device[3].name" = ""DD03""
- # TCP2 (DP-3) for port C2
- register "device[4].name" = ""DD04""
- register "device[4].use_pld" = "true"
- register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
- # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
- register "device[5].name" = ""DD05""
- device generic 0 on end
- end
- end # Integrated Graphics Device
- device ref dtt on
- chip drivers/intel/dptf
- ## sensor information
- register "options.tsr[0].desc" = ""CPU""
- register "options.tsr[1].desc" = ""SSD""
- register "options.tsr[2].desc" = ""CHARGER""
- register "options.tsr[3].desc" = ""MEMORY""
- register "options.tsr[4].desc" = ""TYPEC""
- # TODO: below values are initial reference values only
-
- ## Passive Policy
- register "policies.passive" = "{
- [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
- [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000),
- [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 92, 5000),
- [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000),
- [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000),
- [5] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_4, 90, 5000),
-
- }"
-
- ## Critical Policy
- register "policies.critical" = "{
- [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
- [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
- [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN),
- [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
- [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
- [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 85, SHUTDOWN),
- }"
-
- register "controls.power_limits" = "{
- .pl1 = {
- .min_power = 3000,
- .max_power = 15000,
- .time_window_min = 28 * MSECS_PER_SEC,
- .time_window_max = 32 * MSECS_PER_SEC,
- .granularity = 250,
- },
- .pl2 = {
- .min_power = 55000,
- .max_power = 55000,
- .time_window_min = 28 * MSECS_PER_SEC,
- .time_window_max = 32 * MSECS_PER_SEC,
- .granularity = 1000,
- }
- }"
-
- ## Charger Performance Control (Control, mA)
- register "controls.charger_perf" = "{
- [0] = { 255, 1700 },
- [1] = { 24, 1500 },
- [2] = { 16, 1000 },
- [3] = { 8, 500 }
- }"
- device generic 0 alias dptf_policy on end
- end
- end
- device ref cnvi_wifi on
- chip drivers/wifi/generic
- register "wake" = "GPE0_PME_B0"
- device generic 0 on end
- end
- end
- device ref pcie_rp3 on
- chip soc/intel/common/block/pcie/rtd3
- register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
- register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
- register "srcclk_pin" = "6"
- register "reset_delay_ms" = "50"
- register "enable_delay_ms" = "20"
- device generic 0 alias emmc_rtd3 on end
- end
- # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6
- register "pch_pcie_rp[PCH_RP(3)]" = "{
- .clk_src = 6,
- .clk_req = 6,
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
- }"
- end #PCIE3 BH799BB
- device ref tcss_dma0 on
- chip drivers/intel/usb4/retimer
- register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
- use tcss_usb3_port1 as dfp[0].typec_port
- device generic 0 on end
- end
- end
- device ref tcss_dma1 on
- chip drivers/intel/usb4/retimer
- register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
- use tcss_usb3_port3 as dfp[0].typec_port
- device generic 0 on end
- end
- end
- device ref pcie_rp6 off end #PCIE6 WWAN
- device ref pcie_rp8 on
- chip soc/intel/common/block/pcie/rtd3
- register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
- register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
- register "srcclk_pin" = "3"
- device generic 0 on end
- end
- end #PCIE8 SD card
- device ref pcie_rp9 on
- # Enable NVMe PCIE 9 using clk 0
- register "pch_pcie_rp[PCH_RP(9)]" = "{
- .clk_src = 0,
- .clk_req = 0,
- .flags = PCIE_RP_LTR | PCIE_RP_AER,
- }"
- end #PCIE9-12 SSD
- device ref i2c0 on
- chip drivers/i2c/generic
- register "hid" = ""10EC5682""
- register "name" = ""RT58""
- register "desc" = ""Headset Codec""
- register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
- # Set the jd_src to RT5668_JD1 for jack detection
- register "property_count" = "1"
- register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
- register "property_list[0].name" = ""realtek,jd-src""
- register "property_list[0].integer" = "1"
- device i2c 1a alias audio_codec on
- probe AUDIO MAX98360_ALC5682I_I2S
- probe AUDIO MAX98360_ALC5682I_VS_I2S
- end
- end
- end #I2C0
- device ref i2c1 on
- chip drivers/i2c/hid
- register "generic.hid" = ""ELAN9050""
- register "generic.desc" = ""ELAN Touchscreen""
- register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
- register "generic.detect" = "1"
- register "generic.reset_gpio" =
- "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
- register "generic.reset_delay_ms" = "200"
- register "generic.reset_off_delay_ms" = "1"
- register "generic.enable_gpio" =
- "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
- register "generic.enable_delay_ms" = "6"
- register "generic.stop_gpio" =
- "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
- register "generic.stop_off_delay_ms" = "1"
- register "generic.has_power_resource" = "1"
- register "hid_desc_reg_offset" = "0x01"
- device i2c 0x10 on end
- end
- chip drivers/i2c/hid
- register "generic.hid" = ""GTCH7503""
- register "generic.desc" = ""G2TOUCH Touchscreen""
- register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
- register "generic.detect" = "1"
- register "generic.reset_gpio" =
- "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
- register "generic.reset_delay_ms" = "50"
- register "generic.enable_gpio" =
- "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
- register "generic.enable_delay_ms" = "1"
- register "generic.has_power_resource" = "1"
- register "hid_desc_reg_offset" = "0x01"
- device i2c 0x40 on end
- end
- end
- device ref i2c3 on
- chip drivers/i2c/tpm
- register "hid" = ""GOOG0005""
- register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
- device i2c 50 on end
- end
- end
- device ref i2c5 on
- chip drivers/i2c/generic
- register "hid" = ""ELAN0000""
- register "desc" = ""ELAN Touchpad""
- register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
- register "wake" = "GPE0_DW2_14"
- register "detect" = "1"
- device i2c 15 on end
- end
- chip drivers/i2c/hid
- register "generic.hid" = ""GXTP7288""
- register "generic.desc" = ""Goodix Touchpad""
- register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
- register "generic.wake" = "GPE0_DW2_14"
- register "generic.detect" = "1"
- register "hid_desc_reg_offset" = "0x01"
- device i2c 2c on end
- end
- end
- device ref hda on
- chip drivers/generic/max98357a
- register "hid" = ""MX98360A""
- register "sdmode_gpio" =
- "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
- register "sdmode_delay" = "5"
- device generic 0 on
- probe AUDIO MAX98360_ALC5682I_I2S
- probe AUDIO MAX98360_ALC5682I_VS_I2S
- end
- end
- end
- device ref gspi1 on
- chip drivers/spi/acpi
- register "name" = ""CRFP""
- register "hid" = "ACPI_DT_NAMESPACE_HID"
- register "uid" = "1"
- register "compat_string" = ""google,cros-ec-spi""
- register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
- register "wake" = "GPE0_DW2_15"
- register "has_power_resource" = "1"
- register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
- register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
- register "enable_delay_ms" = "3"
- device spi 0 hidden end
- end # FPMCU
- end
- device ref pch_espi on
- chip ec/google/chromeec
- use conn0 as mux_conn[0]
- use conn1 as mux_conn[1]
- device pnp 0c09.0 on end
- end
- end
- device ref pmc hidden
- chip drivers/intel/pmc_mux
- device generic 0 on
- chip drivers/intel/pmc_mux/conn
- use usb2_port1 as usb2_port
- use tcss_usb3_port1 as usb3_port
- device generic 0 alias conn0 on end
- end
- chip drivers/intel/pmc_mux/conn
- use usb2_port3 as usb2_port
- use tcss_usb3_port3 as usb3_port
- device generic 1 alias conn1 on end
- end
- end
- end
- end
- device ref tcss_xhci on
- chip drivers/usb/acpi
- device ref tcss_root_hub on
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-C Port C0 (MLB)""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))"
- device ref tcss_usb3_port1 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-C Port C2 (MLB)""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
- device ref tcss_usb3_port3 on end
- end
- end
- end
- end
- device ref xhci on
- chip drivers/usb/acpi
- device ref xhci_root_hub on
- chip drivers/usb/acpi
- register "desc" = ""USB2 Type-C Port C0 (MLB)""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))"
- device ref usb2_port1 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB2 Type-C Port C2 (MLB)""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
- device ref usb2_port3 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB2 WWAN""
- register "type" = "UPC_TYPE_INTERNAL"
- device ref usb2_port4 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB2 Camera""
- register "type" = "UPC_TYPE_INTERNAL"
- device ref usb2_port6 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB2 Type-A Port (MLB)""
- register "type" = "UPC_TYPE_A"
- register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
- device ref usb2_port8 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB2 Type-A Port A0 (DB)""
- register "type" = "UPC_TYPE_A"
- register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
- device ref usb2_port9 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB2 Bluetooth""
- register "type" = "UPC_TYPE_INTERNAL"
- register "reset_gpio" =
- "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
- device ref usb2_port10 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A Port A0 (DB)""
- register "type" = "UPC_TYPE_USB3_A"
- register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
- device ref usb3_port1 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A Port (MLB)""
- register "type" = "UPC_TYPE_USB3_A"
- register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
- device ref usb3_port2 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""USB3 WWAN""
- register "type" = "UPC_TYPE_INTERNAL"
- device ref usb3_port4 on end
- end
- end
- end
- end
- end
-end
diff --git a/src/mainboard/google/brya/variants/primus4es/variant.c b/src/mainboard/google/brya/variants/primus4es/variant.c
deleted file mode 100644
index e78dfdc5db..0000000000
--- a/src/mainboard/google/brya/variants/primus4es/variant.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/variants.h>
-#include <boardid.h>
-#include <device/device.h>
-#include <drivers/i2c/hid/chip.h>
-#include <fw_config.h>
-#include <gpio.h>
-
-static void devtree_update_emmc_rtd3(uint32_t board_ver)
-{
- struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3);
- if (board_ver > 1)
- return;
-
- emmc_rtd3->enabled = 0;
-}
-
-static void devtree_update_audio_codec(void)
-{
- struct device *audio_codec = DEV_PTR(audio_codec);
- struct drivers_i2c_generic_config *config = audio_codec->chip_info;
-
- if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S)))
- config->hid = "RTL5682";
-}
-
-static const struct pad_config nvme_disable_pads[] = {
- PAD_NC(GPP_B2, NONE), /* B2 : VRALERT# ==> M2_SSD_PLA_L */
- PAD_NC(GPP_B4, NONE), /* B4 : PROC_GP3 ==> SSD_PERST_L */
- PAD_NC(GPP_D3, NONE), /* D3 : ISH_GP3 ==> M2_SSD_PLN_L */
- PAD_NC(GPP_D5, NONE), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
- PAD_NC(GPP_D11, NONE), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
-};
-
-static const struct pad_config emmc_disable_pads[] = {
- PAD_NC(GPP_B3, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */
- PAD_NC(GPP_E20, NONE), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
- PAD_NC(GPP_F19, NONE), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
-};
-
-static void disable_unused_gpios(void)
-{
- int emmc_detected = gpio_get(GPP_T2);
-
- if (emmc_detected == 1)
- gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads));
- else
- gpio_configure_pads(emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads));
-}
-
-void variant_devtree_update(void)
-{
- uint32_t board_ver = board_id();
- disable_unused_gpios();
- devtree_update_emmc_rtd3(board_ver);
- devtree_update_audio_codec();
-}