diff options
20 files changed, 30 insertions, 18 deletions
diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index 7efd9888da..8ee2453419 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -42,7 +42,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 5ebc76dc1e..fb553cee17 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -37,7 +37,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/amd/f2950/romstage.c b/src/mainboard/amd/f2950/romstage.c index 341a8eab9f..7a28cfd8ce 100644 --- a/src/mainboard/amd/f2950/romstage.c +++ b/src/mainboard/amd/f2950/romstage.c @@ -40,7 +40,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 288a647ff2..3111f2c6e8 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -33,7 +33,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 215d0d9d33..db08887299 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -45,7 +45,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index a40f75948b..410c978eba 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -35,7 +35,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 81975cf49d..82d3a36370 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -35,7 +35,6 @@ int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index f5d5de415a..67b5266bac 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -38,7 +38,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index 52936ad837..7feb5d9b89 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -41,7 +41,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include <northbridge/amd/lx/pll_reset.c> -#include <lib/generic_sdram.c> #include <cpu/amd/geode_lx/cpureginit.c> #include <cpu/amd/geode_lx/syspreinit.c> #include <cpu/amd/geode_lx/msrinit.c> diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index 3ea6013b55..bfb7cb513b 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -42,7 +42,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include <northbridge/amd/lx/pll_reset.c> -#include <lib/generic_sdram.c> #include <cpu/amd/geode_lx/cpureginit.c> #include <cpu/amd/geode_lx/syspreinit.c> #include <cpu/amd/geode_lx/msrinit.c> diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 2647ec8dd5..4e4004bb16 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -69,7 +69,6 @@ static int smc_send_config(unsigned char config_data) #endif #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index e36d4ca8de..b88a6a4ded 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -108,7 +108,6 @@ static int smc_send_config(unsigned char config_data) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 65ddcb7100..49b333b590 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -44,7 +44,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 897de07a5a..a8885700ef 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -109,7 +109,6 @@ static int smc_send_config(unsigned char config_data) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 962e15d0f0..4c06ada723 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -89,7 +89,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 750f755859..e653c9f03e 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -86,7 +86,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index a0c1e17b1e..1dba4a3716 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -34,7 +34,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index a8f64cf35c..ebef4f69c8 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -39,7 +39,6 @@ int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/lx/pll_reset.c" -#include "lib/generic_sdram.c" #include "cpu/amd/geode_lx/cpureginit.c" #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" diff --git a/src/northbridge/amd/lx/Makefile.inc b/src/northbridge/amd/lx/Makefile.inc index 19d9e44db6..190c0598e4 100644 --- a/src/northbridge/amd/lx/Makefile.inc +++ b/src/northbridge/amd/lx/Makefile.inc @@ -5,5 +5,6 @@ ramstage-y += northbridgeinit.c ramstage-y += grphinit.c romstage-y += raminit.c +romstage-y += generic_sdram.c endif diff --git a/src/northbridge/amd/lx/generic_sdram.c b/src/northbridge/amd/lx/generic_sdram.c new file mode 100644 index 0000000000..21239c6c17 --- /dev/null +++ b/src/northbridge/amd/lx/generic_sdram.c @@ -0,0 +1,29 @@ +#include <console/console.h> +#include <northbridge/amd/lx/raminit.h> + +/* Setup SDRAM */ +void sdram_initialize(int controllers, const struct mem_controller *ctrl) +{ + int i; + /* Set the registers we can set once to reasonable values */ + for (i = 0; i < controllers; i++) { + printk(BIOS_DEBUG, "Ram1.%02x\n", i); + sdram_set_registers(ctrl + i); + } + + /* Now setup those things we can auto detect */ + for (i = 0; i < controllers; i++) { + printk(BIOS_DEBUG, "Ram2.%02x\n", i); + sdram_set_spd_registers(ctrl + i); + } + + /* Now that everything is setup enable the SDRAM. + * Some chipsets do the work for us while on others + * we need to it by hand. + */ + printk(BIOS_DEBUG, "Ram3\n"); + + sdram_enable(controllers, ctrl); + + printk(BIOS_DEBUG, "Ram4\n"); +} |