diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/hades/overridetree.cb | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/src/mainboard/google/brya/variants/hades/overridetree.cb b/src/mainboard/google/brya/variants/hades/overridetree.cb index 9c9171c458..1412a1ff6a 100644 --- a/src/mainboard/google/brya/variants/hades/overridetree.cb +++ b/src/mainboard/google/brya/variants/hades/overridetree.cb @@ -211,10 +211,27 @@ chip soc/intel/alderlake end end device ref pcie_rp3 on - # Enable PCIE 3 using clk 4 + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + # Enable SD Card PCIE 3 using clk 4 register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 4, .clk_req = 4, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE3 SD card + device ref pcie_rp4 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 on + # Enable PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip drivers/net @@ -225,23 +242,6 @@ chip soc/intel/alderlake device pci 00.0 on end end end #RTL8111H Ethernet NIC - device ref pcie_rp4 off end - device ref pcie_rp6 off end - device ref pcie_rp7 off end - device ref pcie_rp8 on - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" - register "srcclk_pin" = "3" - device generic 0 on end - end - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE8 SD card device ref pcie_rp9 on # Enable NVMe PCIE 9 using clk 1 register "pch_pcie_rp[PCH_RP(9)]" = "{ |