diff options
| -rw-r--r-- | src/drivers/genesyslogic/gl9763e/gl9763e.c | 4 | ||||
| -rw-r--r-- | src/drivers/genesyslogic/gl9763e/gl9763e.h | 5 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c index d19cc4ae46..cd581b9380 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.c +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c @@ -33,6 +33,10 @@ static void gl9763e_init(struct device *dev) /* Set clock source for RX path */ pci_update_config32(dev, SD_CLKRX_DLY, ~CLK_SRC_MASK, AFTER_OUTPUT_BUFF); } + /* Modify DS delay */ + pci_update_config32(dev, SD_CLKRX_DLY, ~HS400_RX_DELAY_MASK, HS400_RX_DELAY); + /* Disable Slow mode */ + pci_and_config32(dev, EMMC_CTL, ~SLOW_MODE); /* Set VHS to read-only */ pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_R); } diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.h b/src/drivers/genesyslogic/gl9763e/gl9763e.h index 5cdaa68b10..7f5dbf9c05 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.h +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.h @@ -18,6 +18,9 @@ #define PLL_CTL 0x938 #define PLL_CTL_SSC BIT(19) +#define EMMC_CTL 0x960 +#define SLOW_MODE BIT(3) + #define PLL_CTL_2 0x93C #define PLL_CTL_2_MAX_SSC_MASK (0xFFFF << 16) #define MAX_SSC_30000PPM (0xF5C3 << 16) @@ -29,3 +32,5 @@ #define SD_CLKRX_DLY 0x934 #define CLK_SRC_MASK (0x3 << 24) #define AFTER_OUTPUT_BUFF (0x0 << 24) +#define HS400_RX_DELAY_MASK (0xF << 28) +#define HS400_RX_DELAY (0x5 << 28) |