diff options
| -rw-r--r-- | src/soc/qualcomm/common/include/soc/qspi_common.h | 12 | ||||
| -rw-r--r-- | src/soc/qualcomm/common/qspi.c | 24 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7280/bootblock.c | 7 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7280/clock.c | 10 |
5 files changed, 7 insertions, 48 deletions
diff --git a/src/soc/qualcomm/common/include/soc/qspi_common.h b/src/soc/qualcomm/common/include/soc/qspi_common.h index a0c8e46812..6e4b779aee 100644 --- a/src/soc/qualcomm/common/include/soc/qspi_common.h +++ b/src/soc/qualcomm/common/include/soc/qspi_common.h @@ -26,7 +26,6 @@ struct qcom_qspi_regs { u32 current_mem_addr; u32 hw_version; u32 rd_fifo[16]; - u32 sampling_clk_cfg; }; check_member(qcom_qspi_regs, rd_fifo, 0x50); @@ -98,16 +97,7 @@ static struct qcom_qspi_regs * const qcom_qspi = (void *)QSPI_BASE; #define QSPI_MAX_PACKET_COUNT 0xFFC0 -/* - * quadspi_init(): Configure SPI - * - * @param hz: SPI frequency in Hz - * @param sdelay: sampling delay in sdelay/8 cycle units example, if sdelay=1, - * then will delay sampling clock by 1/8 cycle. Note that - * setting sdelay to 4-7 would result in a negative sampling - * delay compared to 0. - */ -void quadspi_init(uint32_t hz, uint32_t sdelay); +void quadspi_init(uint32_t hz); int qspi_claim_bus(const struct spi_slave *slave); int qspi_setup_bus(const struct spi_slave *slave); void qspi_release_bus(const struct spi_slave *slave); diff --git a/src/soc/qualcomm/common/qspi.c b/src/soc/qualcomm/common/qspi.c index eb0c062a81..3340c00dd6 100644 --- a/src/soc/qualcomm/common/qspi.c +++ b/src/soc/qualcomm/common/qspi.c @@ -221,26 +221,11 @@ static void queue_data(uint8_t *data, uint32_t data_bytes, queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write); } -/* - * The way to encode the sampling delay is: - * - * QSPI_SAMPLE_CLK_CONFIG delay (cycle) - * ---------------------------------------- - * 0xFFFh = 1111 1111 1111b 7/8 - * 0xDB6h = 1101 1011 0110b 6/8 - * 0xB6Dh = 1011 0110 1101b 5/8 - * 0x924h = 1001 0010 0100b 4/8 - * 0x6DBh = 0110 1101 1011b 3/8 - * 0x492h = 0100 1001 0010b 2/8 - * 0x249h = 0010 0100 1001b 1/8 - * 0x000h = 0000 0000 0000b None - */ -static void reg_init(uint32_t sdelay) +static void reg_init(void) { uint32_t spi_mode; uint32_t tx_data_oe_delay, tx_data_delay; uint32_t mstr_config; - uint32_t sampling_delay; spi_mode = 0; @@ -251,6 +236,7 @@ static void reg_init(uint32_t sdelay) (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | (spi_mode << SPI_MODE_SHIFT) | (PIN_HOLDN) | + (FB_CLK_EN) | (DMA_ENABLE) | (FULL_CYCLE_MODE); @@ -260,16 +246,14 @@ static void reg_init(uint32_t sdelay) write32(&qcom_qspi->mstr_int_sts, 0xFFFFFFFF); write32(&qcom_qspi->rd_fifo_cfg, 0x0); write32(&qcom_qspi->rd_fifo_rst, RESET_FIFO); - sampling_delay = sdelay << 9 | sdelay << 6 | sdelay << 3 | sdelay << 0; - write32(&qcom_qspi->sampling_clk_cfg, sampling_delay); } -void quadspi_init(uint32_t hz, uint32_t sdelay) +void quadspi_init(uint32_t hz) { assert(dcache_line_bytes() == CACHE_LINE_SIZE); clock_configure_qspi(hz * 4); configure_gpios(); - reg_init(sdelay); + reg_init(); } int qspi_claim_bus(const struct spi_slave *slave) diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index c108157573..365b7d4460 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -8,6 +8,6 @@ void bootblock_soc_init(void) { clock_init(); - quadspi_init(37500 * KHz, 0); + quadspi_init(37500 * KHz); qupv3_fw_init(); } diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c index 0926127baf..bdabea1fbb 100644 --- a/src/soc/qualcomm/sc7280/bootblock.c +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -8,11 +8,6 @@ void bootblock_soc_init(void) { clock_init(); - /* - * Through experimentation, we have determined - * that a delay of 1/8 cycle is best for herobrine. - * See b/190231148 - */ - quadspi_init(75000 * KHz, 1); + quadspi_init(50000 * KHz); qupv3_fw_init(); } diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c index 7b017c4d80..4441e48083 100644 --- a/src/soc/qualcomm/sc7280/clock.c +++ b/src/soc/qualcomm/sc7280/clock.c @@ -28,16 +28,6 @@ static struct clock_freq_config qspi_core_cfg[] = { .div = QCOM_CLOCK_DIV(3), }, { - .hz = 240 * MHz, - .src = SRC_GPLL0_MAIN_600MHZ, - .div = QCOM_CLOCK_DIV(2.5), - }, - { - .hz = 300 * MHz, - .src = SRC_GPLL0_MAIN_600MHZ, - .div = QCOM_CLOCK_DIV(2), - }, - { .hz = 400 * MHz, .src = SRC_GPLL0_MAIN_600MHZ, .div = QCOM_CLOCK_DIV(1.5), |