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-rw-r--r--src/cpu/dmp/vortex86ex/biosdata_ex.S26
-rw-r--r--src/cpu/x86/lapic/apic_timer.c4
-rw-r--r--src/cpu/x86/lapic/boot_cpu.c2
-rw-r--r--src/cpu/x86/lapic/lapic_cpu_init.c21
-rw-r--r--src/cpu/x86/lapic/secondary.S2
-rw-r--r--src/cpu/x86/mtrr/mtrr.c2
-rw-r--r--src/cpu/x86/smm/smihandler.c4
-rw-r--r--src/cpu/x86/smm/smm_module_handler.c4
-rw-r--r--src/cpu/x86/smm/smmrelocate.S12
-rw-r--r--src/cpu/x86/tsc/delay_tsc.c2
10 files changed, 40 insertions, 39 deletions
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S
index 59d7ff19be..6686bb7467 100644
--- a/src/cpu/dmp/vortex86ex/biosdata_ex.S
+++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S
@@ -38,7 +38,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
500/375/33 B4 53 0F 02 AF 09
*/
-#if CONFIG_PLL_200_200_33
+#if IS_ENABLED(CONFIG_PLL_200_200_33)
// 200/200/33 30 03 0F 02 8F 07
byte_fffb6 = 0x30
byte_fffb7 = 0x03
@@ -46,7 +46,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_300_300_33
+#elif IS_ENABLED(CONFIG_PLL_300_300_33)
// 300/300/33 48 03 0F 02 1F 07
byte_fffb6 = 0x48
byte_fffb7 = 0x03
@@ -54,7 +54,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_300_300_100
+#elif IS_ENABLED(CONFIG_PLL_300_300_100)
// 300/300/100 48 03 23 02 7F 07
byte_fffb6 = 0x48
byte_fffb7 = 0x03
@@ -62,7 +62,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_400_200_33
+#elif IS_ENABLED(CONFIG_PLL_400_200_33)
// 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing
byte_fffb6 = 0x60
byte_fffb7 = 0x43
@@ -70,7 +70,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_400_200_100
+#elif IS_ENABLED(CONFIG_PLL_400_200_100)
// 400/200/100 60 43 23 02 4F 07
byte_fffb6 = 0x60
byte_fffb7 = 0x43
@@ -78,7 +78,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_400_400_33
+#elif IS_ENABLED(CONFIG_PLL_400_400_33)
// 400/400/33 60 03 0F 02 BF 09
byte_fffb6 = 0x60
byte_fffb7 = 0x03
@@ -86,7 +86,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x09
-#elif CONFIG_PLL_500_250_33
+#elif IS_ENABLED(CONFIG_PLL_500_250_33)
// 500/250/33 50 42 0F 02 DF 07
byte_fffb6 = 0x50
byte_fffb7 = 0x42
@@ -94,7 +94,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_500_500_33
+#elif IS_ENABLED(CONFIG_PLL_500_500_33)
// 500/500/33 78 03 0F 02 4F 09
byte_fffb6 = 0x78
byte_fffb7 = 0x03
@@ -102,7 +102,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x09
-#elif CONFIG_PLL_400_300_33
+#elif IS_ENABLED(CONFIG_PLL_400_300_33)
// 400/300/33 90 53 0F 02 3F 07
byte_fffb6 = 0x90
byte_fffb7 = 0x53
@@ -110,7 +110,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_400_300_100
+#elif IS_ENABLED(CONFIG_PLL_400_300_100)
// 400/300/100 90 53 23 02 9F 07
byte_fffb6 = 0x90
byte_fffb7 = 0x53
@@ -118,7 +118,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x07
-#elif CONFIG_PLL_444_333_33
+#elif IS_ENABLED(CONFIG_PLL_444_333_33)
// 444/333/33 A0 53 0F 02 5F 08
byte_fffb6 = 0xa0
byte_fffb7 = 0x53
@@ -126,7 +126,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x08
-#elif CONFIG_PLL_466_350_33
+#elif IS_ENABLED(CONFIG_PLL_466_350_33)
// 466/350/33 A8 53 0F 02 DF 09
byte_fffb6 = 0xa8
byte_fffb7 = 0x53
@@ -134,7 +134,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF
byte_fffbc = 0x02
byte_fffbe = 0xff
byte_fffbf = 0x09
-#elif CONFIG_PLL_500_375_33
+#elif IS_ENABLED(CONFIG_PLL_500_375_33)
// 500/375/33 B4 53 0F 02 AF 09
byte_fffb6 = 0xb4
byte_fffb7 = 0x53
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index cddc5ad575..254bb07b11 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -29,7 +29,7 @@
* memory init.
*/
-#if CONFIG_UDELAY_LAPIC_FIXED_FSB
+#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0
static inline u32 get_timer_fsb(void)
{
return CONFIG_UDELAY_LAPIC_FIXED_FSB;
@@ -136,7 +136,7 @@ void udelay(u32 usecs)
} while ((start - value) < ticks);
}
-#if CONFIG_LAPIC_MONOTONIC_TIMER && !defined(__PRE_RAM__)
+#if IS_ENABLED(CONFIG_LAPIC_MONOTONIC_TIMER) && !defined(__PRE_RAM__)
#include <timer.h>
static struct monotonic_counter {
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 2942ff68fb..7ba21fe90c 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -14,7 +14,7 @@
#include <smp/node.h>
#include <cpu/x86/msr.h>
-#if CONFIG_SMP
+#if IS_ENABLED(CONFIG_SMP)
int boot_cpu(void)
{
int bsp;
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 427e537ce6..83be53b22d 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -36,7 +36,7 @@
#include <cpu/intel/speedstep.h>
#include <thread.h>
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@@ -148,8 +148,9 @@ static int lapic_start_cpu(unsigned long apicid)
}
return 0;
}
-#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX \
- && !CONFIG_CPU_INTEL_MODEL_2065X
+#if !IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) \
+ && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_206AX) \
+ && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_2065X)
mdelay(10);
#endif
@@ -324,7 +325,7 @@ int start_cpu(struct device *cpu)
return result;
}
-#if CONFIG_AP_IN_SIPI_WAIT
+#if IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT)
/**
* Sending INIT IPI to self is equivalent of asserting #INIT with a bit of
@@ -556,17 +557,17 @@ void initialize_cpus(struct bus *cpu_bus)
/* Find the device structure for the boot CPU */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
// why here? In case some day we can start core1 in amd_sibling_init
copy_secondary_start_to_lowest_1M();
#endif
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))
smm_init();
#endif
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
/* start all aps at first, so we can init ECC all together */
if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);
@@ -575,7 +576,7 @@ void initialize_cpus(struct bus *cpu_bus)
/* Initialize the bootstrap processor */
cpu_initialize(0);
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);
@@ -588,13 +589,13 @@ void initialize_cpus(struct bus *cpu_bus)
* smm_init() will queue a pending SMI on all cpus
* and smm_other_cpus() will start them one by one */
smm_init();
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
last_cpu_index = 0;
smm_other_cpus(cpu_bus, info->cpu);
#endif
}
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
recover_lowest_1M();
#endif
}
diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
index 0c4c0d061c..a36502b1ac 100644
--- a/src/cpu/x86/lapic/secondary.S
+++ b/src/cpu/x86/lapic/secondary.S
@@ -14,7 +14,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1
.text
.globl _secondary_start, _secondary_start_end, _secondary_gdt_addr
.balign 4096
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 609d1e76db..ef1bb31317 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,7 +36,7 @@
#include <arch/cpu.h>
#include <arch/acpi.h>
#include <memrange.h>
-#if CONFIG_X86_AMD_FIXED_MTRRS
+#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
#include <cpu/amd/mtrr.h>
#define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM)
#else
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index 6999f566e2..fa5658e25e 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -19,7 +19,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
#include <spi-generic.h>
#endif
@@ -185,7 +185,7 @@ void smi_handler(u32 smm_revision)
/* Allow drivers to initialize variables in SMM context. */
if (do_driver_init) {
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
spi_init();
#endif
do_driver_init = 0;
diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
index cfb2b91668..c622e45c3d 100644
--- a/src/cpu/x86/smm/smm_module_handler.c
+++ b/src/cpu/x86/smm/smm_module_handler.c
@@ -18,7 +18,7 @@
#include <cpu/x86/smm.h>
#include <rmodule.h>
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
#include <spi-generic.h>
#endif
@@ -158,7 +158,7 @@ asmlinkage void smm_handler_start(void *arg)
/* Allow drivers to initialize variables in SMM context. */
if (do_driver_init) {
-#if CONFIG_SPI_FLASH_SMM
+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
spi_init();
#endif
do_driver_init = 0;
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 2fe01565c4..2a950f3eb7 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -21,19 +21,19 @@
// can it be cleaned up so this include is not required?
// It's needed right now because we get our DEFAULT_PMBASE from
// here.
-#if CONFIG_SOUTHBRIDGE_INTEL_I82801GX
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
-#elif CONFIG_SOUTHBRIDGE_INTEL_I82801DX
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)
#include "../../../southbridge/intel/i82801dx/i82801dx.h"
-#elif CONFIG_SOC_INTEL_SCH
+#elif IS_ENABLED(CONFIG_SOC_INTEL_SCH)
#include "../../../soc/intel/sch/sch.h"
-#elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)
#include "../../../southbridge/intel/i82801ix/i82801ix.h"
#else
#error "Southbridge needs SMM handler support."
#endif
-#if CONFIG_SMM_TSEG
+#if IS_ENABLED(CONFIG_SMM_TSEG)
#error "Don't use this file with TSEG."
#endif /* CONFIG_SMM_TSEG */
@@ -155,7 +155,7 @@ smm_relocate:
/* End of southbridge specific section. */
-#if CONFIG_DEBUG_SMM_RELOCATION
+#if IS_ENABLED(CONFIG_DEBUG_SMM_RELOCATION)
/* print [SMM-x] so we can determine if CPUx went to SMM */
movw $CONFIG_TTYS0_BASE, %dx
mov $'[', %al
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index b2e20f422d..ec2f1d7211 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -136,7 +136,7 @@ void udelay(unsigned int us)
}
}
-#if CONFIG_TSC_MONOTONIC_TIMER
+#if IS_ENABLED(CONFIG_TSC_MONOTONIC_TIMER)
#include <timer.h>
static struct monotonic_counter {
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-07 15:29:12 +0000