diff options
| -rw-r--r-- | src/drivers/amd/agesa/mtrr_fixme.c | 2 | ||||
| -rw-r--r-- | src/drivers/net/ne2k.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/sata.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/ramstage.c | 4 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 2 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5420/dp.c | 10 |
6 files changed, 11 insertions, 11 deletions
diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index a880ce7e01..c589553698 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -20,7 +20,7 @@ static void set_range_uc(u32 base, u32 size) for (i = 0; i < max_var_mtrrs; i++) { msr = rdmsr(MTRR_PHYS_MASK(i)); if (!(msr.lo & MTRR_PHYS_MASK_VALID)) - break; + break; } if (i == max_var_mtrrs) die("Run out of unused MTRRs\n"); diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 971f31dd83..635315b359 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -84,7 +84,7 @@ static void eth_pio_write(unsigned char *src, unsigned int dst, unsigned int cnt outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); while (cnt--) { - outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA); + outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA); } /* #warning "Add timeout" diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 24c805ac81..5e5215b249 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -71,7 +71,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, 0x92, reg16); if (config->sata_ahci) { - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); /* Enable CR memory space decoding */ reg16 = pci_read_config16(dev, 0x04); diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 48f2193e47..42d1f9f080 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -68,11 +68,11 @@ static void fill_in_pattrs(void) dev = pcidev_on_root(LPC_DEV, LPC_FUNC); attrs->revid = pci_read_config8(dev, REVID); /* The revision to stepping IDs have two values per metal stepping. */ - if (attrs->revid >= RID_D_STEPPING_START) { + if (attrs->revid >= RID_D_STEPPING_START) { attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2; attrs->stepping += STEP_D1; - } else if (attrs->revid >= RID_C_STEPPING_START) { + } else if (attrs->revid >= RID_C_STEPPING_START) { attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; attrs->stepping += STEP_C0; diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 23a9403acf..10d03e0c8e 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -828,7 +828,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, /* 4. enable read/write test */ if (wr == TE_OP_READ_CHECK) { - if ((testaudpat == 1) || (testaudpat == 2)) { + if ((testaudpat == 1) || (testaudpat == 2)) { /* if audio pattern, enable read only */ /* (disable write after read), */ /* AUDMODE=0x48[15]=0 */ diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index 758e09b05d..13a8feff41 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -336,8 +336,8 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable) ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET, data); if (ret != EXYNOS_DP_SUCCESS) { - printk(BIOS_ERR, "DP write_to_dpcd failed\n"); - return -1; + printk(BIOS_ERR, "DP write_to_dpcd failed\n"); + return -1; } @@ -467,9 +467,9 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); if (ret != EXYNOS_DP_SUCCESS) { - printk(BIOS_ERR, "DP read lane status failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; - return ret; + printk(BIOS_ERR, "DP read lane status failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + return ret; } if (lane_stat & DP_LANE_STAT_CR_DONE) { |