diff options
| -rw-r--r-- | src/include/cpu/amd/msr.h | 5 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/tsc/tsc_freq.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/glinda/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/phoenix/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/tsc_freq.c | 2 |
8 files changed, 8 insertions, 11 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 76e6a8d665..1fd7ec7dbc 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -40,10 +40,7 @@ /* P-state Status Register */ #define PS_STS_REG 0xC0010063 #define PSTATE_0_MSR 0xC0010064 -#define PSTATE_1_MSR 0xC0010065 -#define PSTATE_2_MSR 0xC0010066 -#define PSTATE_3_MSR 0xC0010067 -#define PSTATE_4_MSR 0xC0010068 +#define PSTATE_MSR(pstate) (PSTATE_0_MSR + (pstate)) #define MSR_PATCH_LOADER 0xC0010020 #define MSR_COFVID_STS 0xC0010071 diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 631f388fdf..46eaadca57 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -200,7 +200,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c index 55c86653ce..fbbf399731 100644 --- a/src/soc/amd/common/block/cpu/tsc/tsc_freq.c +++ b/src/soc/amd/common/block/cpu/tsc/tsc_freq.c @@ -22,7 +22,7 @@ unsigned long tsc_freq_mhz(void) return mhz; high_state = rdmsr(PS_LIM_REG).lo & 0x7; - msr = rdmsr(PSTATE_0_MSR + high_state); + msr = rdmsr(PSTATE_MSR(high_state)); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 31723b1b4f..675ab20f12 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -203,7 +203,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 044b345df1..fb4d103aee 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -202,7 +202,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 09c4a15401..25ebc66afd 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -203,7 +203,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index f6fb9f259d..138e743d0c 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -202,7 +202,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; for (pstate = 0; pstate <= max_pstate; pstate++) { - pstate_def = rdmsr(PSTATE_0_MSR + pstate); + pstate_def = rdmsr(PSTATE_MSR(pstate)); pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) >> PSTATE_DEF_HI_ENABLE_SHIFT; diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index 01f2321f8c..0be93aa571 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -23,7 +23,7 @@ unsigned long tsc_freq_mhz(void) boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7; - msr = rdmsr(PSTATE_0_MSR + boost_states); + msr = rdmsr(PSTATE_MSR(boost_states)); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); |