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-rw-r--r--src/mainboard/sunw/ultra40/Options.lb9
-rw-r--r--src/mainboard/sunw/ultra40/auto.c2
-rw-r--r--src/mainboard/sunw/ultra40/cache_as_ram_auto.c2
-rw-r--r--src/mainboard/sunw/ultra40/chip.h4
-rw-r--r--src/mainboard/sunw/ultra40/mptable.c4
-rw-r--r--src/northbridge/amd/gx2/northbridge.c47
-rw-r--r--targets/olpc/rev_a/Config.1M.lb2
-rw-r--r--targets/sunw/ultra40/Config.lb4
8 files changed, 61 insertions, 13 deletions
diff --git a/src/mainboard/sunw/ultra40/Options.lb b/src/mainboard/sunw/ultra40/Options.lb
index c3f8ba3f8c..32748f5f1d 100644
--- a/src/mainboard/sunw/ultra40/Options.lb
+++ b/src/mainboard/sunw/ultra40/Options.lb
@@ -176,10 +176,11 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="s2895"
-default MAINBOARD_VENDOR="Tyan"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
+default MAINBOARD_PART_NUMBER="ultra40"
+default MAINBOARD_VENDOR="sunw"
+
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x108e
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x40
###
### LinuxBIOS layout values
diff --git a/src/mainboard/sunw/ultra40/auto.c b/src/mainboard/sunw/ultra40/auto.c
index bf65cbe6a7..6ab2ac5b9e 100644
--- a/src/mainboard/sunw/ultra40/auto.c
+++ b/src/mainboard/sunw/ultra40/auto.c
@@ -174,7 +174,7 @@ static void main(unsigned long bist)
sio_gpio_setup();
- setup_s2895_resource_map();
+ setup_ultra40_resource_map();
needs_reset = setup_coherent_ht_domain();
diff --git a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
index 299f345b71..0ec0b7bac3 100644
--- a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
+++ b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
@@ -236,7 +236,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- setup_s2895_resource_map();
+ setup_ultra40_resource_map();
needs_reset = setup_coherent_ht_domain();
diff --git a/src/mainboard/sunw/ultra40/chip.h b/src/mainboard/sunw/ultra40/chip.h
index 350f4a6369..bd7b8634bc 100644
--- a/src/mainboard/sunw/ultra40/chip.h
+++ b/src/mainboard/sunw/ultra40/chip.h
@@ -1,6 +1,6 @@
-extern struct chip_operations mainboard_tyan_s2895_ops;
+extern struct chip_operations mainboard_sunw_ultra40_ops;
-struct mainboard_tyan_s2895_config {
+struct mainboard_sunw_ultra40_config {
// int fixup_scsi;
// int fixup_vga;
};
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index a41cbcd12f..c63dbd2387 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -35,8 +35,8 @@ extern unsigned sbdnb;
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
- static const char oem[8] = "TYAN ";
- static const char productid[12] = "S2895 ";
+ static const char oem[8] = "SUNW ";
+ static const char productid[12] = "ultra40 ";
struct mp_config_table *mc;
unsigned char bus_num;
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index a0ad84669f..82175a5a66 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -283,9 +283,56 @@ static void northbridge_init(device_t dev)
irq_init_steering(dev, nb->irqmap);
}
+/* due to vsa interactions, we need not not touch the nb settings ... */
+/* this is a test -- we are not sure it will work -- but it ought to */
+static void set_resources(struct device *dev)
+{
+ struct resource *resource, *last;
+ unsigned link;
+ uint8_t line;
+
+#if 0
+ last = &dev->resource[dev->resources];
+
+ for(resource = &dev->resource[0]; resource < last; resource++) {
+ pci_set_resource(dev, resource);
+ }
+#endif
+ for(link = 0; link < dev->links; link++) {
+ struct bus *bus;
+ bus = &dev->link[link];
+ if (bus->children) {
+ assign_resources(bus);
+ }
+ }
+
+#if 0
+ /* set a default latency timer */
+ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
+
+ /* set a default secondary latency timer */
+ if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+ pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
+ }
+
+ /* zero the irq settings */
+ line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+ if (line) {
+ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
+ }
+ /* set the cache line size, so far 64 bytes is good for everyone */
+ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
+#endif
+}
+
+
+
static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources,
+#if 0
.set_resources = pci_dev_set_resources,
+#endif
+ .set_resources = set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = 0,
diff --git a/targets/olpc/rev_a/Config.1M.lb b/targets/olpc/rev_a/Config.1M.lb
index 4450e1798b..aa398538c5 100644
--- a/targets/olpc/rev_a/Config.1M.lb
+++ b/targets/olpc/rev_a/Config.1M.lb
@@ -5,7 +5,7 @@ mainboard olpc/rev_a
# Don't let LinuxBIOS compress the payload
# option CONFIG_COMPRESSED_ROM_STREAM=0
-option CONFIG_PRECOMPRESSED_ROM_STREAM=1
+#option CONFIG_PRECOMPRESSED_ROM_STREAM=1
# leave 64k for vsa
option ROM_SIZE=1024*1024-64*1024
diff --git a/targets/sunw/ultra40/Config.lb b/targets/sunw/ultra40/Config.lb
index 0b8d91b12f..ccb7f771cb 100644
--- a/targets/sunw/ultra40/Config.lb
+++ b/targets/sunw/ultra40/Config.lb
@@ -29,7 +29,7 @@ romimage "normal"
# payload ../../../payloads/filo.zelf
# payload ../../../payloads/tg3.zelf
# payload ../../../payloads/tg3--filo_hda2_vga.zelf
- payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
+ payload /etc/hosts
# payload ../../../payloads/forcedeth_vga.zelf
# payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf
# payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf
@@ -58,7 +58,7 @@ romimage "fallback"
# payload ../../../payloads/filo.zelf
# payload ../../../payloads/tg3.zelf
# payload ../../../payloads/tg3--filo_hda2_vga.zelf
- payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
+ payload /etc/hosts
# payload ../../../payloads/forcedeth_vga.zelf
# payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf
# payload ../../../payloads/tg3_vga.zelf
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-21 05:13:23 +0000