aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--util/inteltool/inteltool.c128
-rw-r--r--util/inteltool/inteltool.h28
-rw-r--r--util/inteltool/memory.c62
-rw-r--r--util/inteltool/pcie.c75
4 files changed, 189 insertions, 104 deletions
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 56bbc4a458..2d99863621 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -30,36 +30,54 @@
#include <unistd.h>
#endif
+/*
+ * http://pci-ids.ucw.cz/read/PC/8086
+ * http://en.wikipedia.org/wiki/Intel_Tick-Tock
+ * http://en.wikipedia.org/wiki/List_of_Intel_chipsets
+ * http://en.wikipedia.org/wiki/Intel_Xeon_chipsets
+ */
static const struct {
uint16_t vendor_id, device_id;
char *name;
} supported_chips_list[] = {
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
+ /* Host bridges/DRAM controllers (Northbridges) */
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "443LX" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "443BX" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "443BX without AGP" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "810" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_DC, "810-DC100" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_DC, "810E DC-133" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "830M" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "845" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "865" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "915G/P/GV/GL/PL/910GL" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "945P" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "945GM" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "945GSE" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965PM, "965PM" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q965, "Q963/82Q965" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "975X" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65E, "HM65 Express" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
+ /* Host bridges /DRAM controllers integrated in CPUs */
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" },
+ /* Southbridges (LPC controllers) */
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
@@ -81,14 +99,58 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "631xESB/632xESB/3100" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
+ { PCI_VENDOR_ID_INTEL, 0x3b00, "3400 Desktop" },
+ { PCI_VENDOR_ID_INTEL, 0x3b01, "3400 Mobile" },
+ { PCI_VENDOR_ID_INTEL, 0x3b02, "P55" },
+ { PCI_VENDOR_ID_INTEL, 0x3b03, "PM55" },
+ { PCI_VENDOR_ID_INTEL, 0x3b06, "H55" },
+ { PCI_VENDOR_ID_INTEL, 0x3b07, "QM57" },
+ { PCI_VENDOR_ID_INTEL, 0x3b08, "H57" },
+ { PCI_VENDOR_ID_INTEL, 0x3b09, "HM55" },
+ { PCI_VENDOR_ID_INTEL, 0x3b0a, "Q57" },
+ { PCI_VENDOR_ID_INTEL, 0x3b0b, "HM57" },
+ { PCI_VENDOR_ID_INTEL, 0x3b0d, "3400 Mobile SFF" },
+ { PCI_VENDOR_ID_INTEL, 0x3b0e, "B55" },
+ { PCI_VENDOR_ID_INTEL, 0x3b0f, "QS57" },
+ { PCI_VENDOR_ID_INTEL, 0x3b12, "3400" },
+ { PCI_VENDOR_ID_INTEL, 0x3b14, "3420" },
+ { PCI_VENDOR_ID_INTEL, 0x3b16, "3450" },
+ { PCI_VENDOR_ID_INTEL, 0x3b1e, "B55" },
+ { PCI_VENDOR_ID_INTEL, 0x1c44, "Z68" },
+ { PCI_VENDOR_ID_INTEL, 0x1c46, "P67" },
+ { PCI_VENDOR_ID_INTEL, 0x1c47, "UM67" },
+ { PCI_VENDOR_ID_INTEL, 0x1c49, "HM65" },
+ { PCI_VENDOR_ID_INTEL, 0x1c4a, "H67" },
+ { PCI_VENDOR_ID_INTEL, 0x1c4b, "HM67" },
+ { PCI_VENDOR_ID_INTEL, 0x1c4c, "Q65" },
+ { PCI_VENDOR_ID_INTEL, 0x1c4d, "QS67" },
+ { PCI_VENDOR_ID_INTEL, 0x1c4e, "Q67" },
+ { PCI_VENDOR_ID_INTEL, 0x1c4f, "QM67" },
+ { PCI_VENDOR_ID_INTEL, 0x1c50, "B65" },
+ { PCI_VENDOR_ID_INTEL, 0x1c52, "C202" },
+ { PCI_VENDOR_ID_INTEL, 0x1c54, "C204" },
+ { PCI_VENDOR_ID_INTEL, 0x1c56, "C206" },
+ { PCI_VENDOR_ID_INTEL, 0x1c5c, "H61" },
+ { PCI_VENDOR_ID_INTEL, 0x1d40, "X79" },
+ { PCI_VENDOR_ID_INTEL, 0x1d41, "X79" },
+ { PCI_VENDOR_ID_INTEL, 0x1e44, "Z77" },
+ { PCI_VENDOR_ID_INTEL, 0x1e46, "Z75" },
+ { PCI_VENDOR_ID_INTEL, 0x1e47, "Q77" },
+ { PCI_VENDOR_ID_INTEL, 0x1e48, "Q75" },
+ { PCI_VENDOR_ID_INTEL, 0x1e49, "B75" },
+ { PCI_VENDOR_ID_INTEL, 0x1e4a, "H77" },
+ { PCI_VENDOR_ID_INTEL, 0x1e53, "C216" },
+ { PCI_VENDOR_ID_INTEL, 0x1e55, "QM77" },
+ { PCI_VENDOR_ID_INTEL, 0x1e56, "QS77" },
+ { PCI_VENDOR_ID_INTEL, 0x1e57, "HM77" },
+ { PCI_VENDOR_ID_INTEL, 0x1e58, "UM77" },
+ { PCI_VENDOR_ID_INTEL, 0x1e59, "HM76" },
+ { PCI_VENDOR_ID_INTEL, 0x1e5d, "HM75" },
+ { PCI_VENDOR_ID_INTEL, 0x1e5e, "HM70" },
+ { PCI_VENDOR_ID_INTEL, 0x1e5f, "NM70" },
+ { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
};
#ifndef __DARWIN__
@@ -309,7 +371,7 @@ int main(int argc, char *argv[])
* left-shifted "Extended Model" fields.
* http://download.intel.com/design/processor/applnots/24161832.pdf
*/
- printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n",
+ printf("CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n",
(id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
@@ -321,10 +383,10 @@ int main(int argc, char *argv[])
if (sb->device_id == supported_chips_list[i].device_id)
sbname = supported_chips_list[i].name;
- printf("Intel Northbridge: %04x:%04x (%s)\n",
+ printf("Northbridge: %04x:%04x (%s)\n",
nb->vendor_id, nb->device_id, nbname);
- printf("Intel Southbridge: %04x:%04x (%s)\n",
+ printf("Southbridge: %04x:%04x (%s)\n",
sb->vendor_id, sb->device_id, sbname);
/* Now do the deed */
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index aa8a292a5b..7ef2d8d309 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -63,27 +63,27 @@
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
#define PCI_DEVICE_ID_INTEL_82810 0x7120
-#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
-#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124
+#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
+#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
#define PCI_DEVICE_ID_INTEL_82830M 0x3575
#define PCI_DEVICE_ID_INTEL_82845 0x1a30
#define PCI_DEVICE_ID_INTEL_82865 0x2570
#define PCI_DEVICE_ID_INTEL_82915 0x2580
#define PCI_DEVICE_ID_INTEL_82945P 0x2770
#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
-#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac
-#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
-#define PCI_DEVICE_ID_INTEL_Q965 0x2990
+#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac
+#define PCI_DEVICE_ID_INTEL_82965PM 0x2a00
+#define PCI_DEVICE_ID_INTEL_82Q965 0x2990
#define PCI_DEVICE_ID_INTEL_82975X 0x277c
#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
#define PCI_DEVICE_ID_INTEL_82G33 0x29c0
#define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
-#define PCI_DEVICE_ID_INTEL_X44 0x29e0
+#define PCI_DEVICE_ID_INTEL_82X38 0x29e0
#define PCI_DEVICE_ID_INTEL_32X0 0x29f0
-#define PCI_DEVICE_ID_INTEL_GS45 0x2a40
-#define PCI_DEVICE_ID_INTEL_X58 0x3405
-#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
-#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
+#define PCI_DEVICE_ID_INTEL_82X4X 0x2a40
+#define PCI_DEVICE_ID_INTEL_82X58 0x3405
+#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
+#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
#define PCI_DEVICE_ID_INTEL_I63XX 0x2670
#define PCI_DEVICE_ID_INTEL_I5000X 0x25c0
@@ -92,7 +92,7 @@
#define PCI_DEVICE_ID_INTEL_I5000P 0x25d8
/* untested, but almost identical to D-series */
-#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
+#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
@@ -102,7 +102,11 @@
/* 82371AB/EB/MB use the same device ID value. */
#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
-#define PCI_DEVICE_ID_INTEL_HM65E 0x0104
+/* Intel starts counting these generations with the integration of the DRAM controller */
+#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
+#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */
+#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */
+#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */
#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index d66ee4884d..62d72177b0 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -108,20 +108,20 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
case PCI_DEVICE_ID_INTEL_82945GM:
case PCI_DEVICE_ID_INTEL_82945GSE:
case PCI_DEVICE_ID_INTEL_82945P:
- case PCI_DEVICE_ID_INTEL_82975X:
+ case PCI_DEVICE_ID_INTEL_82975X:
mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
break;
- case PCI_DEVICE_ID_INTEL_PM965:
- case PCI_DEVICE_ID_INTEL_82Q35:
- case PCI_DEVICE_ID_INTEL_82G33:
- case PCI_DEVICE_ID_INTEL_82Q33:
- mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
- mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
- break;
- case PCI_DEVICE_ID_INTEL_Q965:
+ case PCI_DEVICE_ID_INTEL_82965PM:
+ case PCI_DEVICE_ID_INTEL_82Q35:
+ case PCI_DEVICE_ID_INTEL_82G33:
+ case PCI_DEVICE_ID_INTEL_82Q33:
+ mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
+ mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+ break;
+ case PCI_DEVICE_ID_INTEL_82Q965:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
- mchbar_phys = pci_read_long(nb, 0x48);
+ mchbar_phys = pci_read_long(nb, 0x48);
/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
* If it isn't, try to set it. This may fail, because there is
@@ -131,36 +131,45 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
if(!(mchbar_phys & 1))
{
- printf("Access to the MCHBAR is currently disabled, "\
- "attempting to enable.\n");
+ printf("Access to the MCHBAR is currently disabled, "
+ "attempting to enable.\n");
mchbar_phys |= 0x1;
pci_write_long(nb, 0x48, mchbar_phys);
- if(pci_read_long(nb, 0x48) & 1)
+ if(pci_read_long(nb, 0x48) & 1)
printf("Enabled successfully.\n");
else
printf("Enable FAILED!\n");
}
mchbar_phys &= 0xfffffffe;
- mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
- break;
+ mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+ break;
case PCI_DEVICE_ID_INTEL_82443LX:
case PCI_DEVICE_ID_INTEL_82443BX:
case PCI_DEVICE_ID_INTEL_82810:
- case PCI_DEVICE_ID_INTEL_82810E_MC:
- case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82810E_DC:
+ case PCI_DEVICE_ID_INTEL_82810_DC:
case PCI_DEVICE_ID_INTEL_82830M:
printf("This northbridge does not have MCHBAR.\n");
return 1;
- case PCI_DEVICE_ID_INTEL_GS45:
- case PCI_DEVICE_ID_INTEL_X44:
+ case PCI_DEVICE_ID_INTEL_82X4X:
+ case PCI_DEVICE_ID_INTEL_82X38:
case PCI_DEVICE_ID_INTEL_32X0:
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
- break;
- case PCI_DEVICE_ID_INTEL_HM65E:
- mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000;
+ break;
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
+ mchbar_phys = pci_read_long(nb, 0x48);
+ mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+ mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
+ mch_registers = NULL; /* No public documentation */
+ break;
+ case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
mch_registers = sandybridge_mch_registers;
size = ARRAY_SIZE(sandybridge_mch_registers);
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
+ mchbar_phys = pci_read_long(nb, 0x48);
+ mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+ mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
break;
default:
printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
@@ -183,28 +192,29 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
if (mch_registers != NULL) {
+ printf("%d registers:\n", size);
for (i = 0; i < size; i++) {
switch (mch_registers[i].size) {
case 8:
- printf("mchbase+0x%04x: 0x%08lx (%s)\n",
+ printf("mchbase+0x%04x: 0x%016lx (%s)\n",
mch_registers[i].addr,
*(uint64_t *)(mchbar+mch_registers[i].addr),
mch_registers[i].name);
break;
case 4:
- printf("mchbase+0x%04x: 0x%08x (%s)\n",
+ printf("mchbase+0x%04x: 0x%08x (%s)\n",
mch_registers[i].addr,
*(uint32_t *)(mchbar+mch_registers[i].addr),
mch_registers[i].name);
break;
case 2:
- printf("mchbase+0x%04x: 0x%04x (%s)\n",
+ printf("mchbase+0x%04x: 0x%04x (%s)\n",
mch_registers[i].addr,
*(uint16_t *)(mchbar+mch_registers[i].addr),
mch_registers[i].name);
break;
case 1:
- printf("mchbase+0x%04x: 0x%02x (%s)\n",
+ printf("mchbase+0x%04x: 0x%02x (%s)\n",
mch_registers[i].addr,
*(uint8_t *)(mchbar+mch_registers[i].addr),
mch_registers[i].name);
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index a7429a0202..e454f44b16 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -94,22 +94,22 @@ int print_epbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82975X:
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
break;
- case PCI_DEVICE_ID_INTEL_PM965:
- case PCI_DEVICE_ID_INTEL_Q965:
- case PCI_DEVICE_ID_INTEL_82Q35:
- case PCI_DEVICE_ID_INTEL_82G33:
- case PCI_DEVICE_ID_INTEL_82Q33:
- case PCI_DEVICE_ID_INTEL_X44:
+ case PCI_DEVICE_ID_INTEL_82965PM:
+ case PCI_DEVICE_ID_INTEL_82Q965:
+ case PCI_DEVICE_ID_INTEL_82Q35:
+ case PCI_DEVICE_ID_INTEL_82G33:
+ case PCI_DEVICE_ID_INTEL_82Q33:
+ case PCI_DEVICE_ID_INTEL_82X38:
case PCI_DEVICE_ID_INTEL_32X0:
- case PCI_DEVICE_ID_INTEL_GS45:
+ case PCI_DEVICE_ID_INTEL_82X4X:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
- epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
- epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
- break;
+ epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
+ epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
+ break;
case PCI_DEVICE_ID_INTEL_82810:
- case PCI_DEVICE_ID_INTEL_82810DC:
- case PCI_DEVICE_ID_INTEL_82810E_MC:
+ case PCI_DEVICE_ID_INTEL_82810_DC:
+ case PCI_DEVICE_ID_INTEL_82810E_DC:
case PCI_DEVICE_ID_INTEL_82830M:
case PCI_DEVICE_ID_INTEL_82865:
printf("This northbridge does not have EPBAR.\n");
@@ -156,32 +156,41 @@ int print_dmibar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82975X:
dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
break;
- case PCI_DEVICE_ID_INTEL_PM965:
- case PCI_DEVICE_ID_INTEL_Q965:
+ case PCI_DEVICE_ID_INTEL_82965PM:
+ case PCI_DEVICE_ID_INTEL_82Q965:
case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33:
- case PCI_DEVICE_ID_INTEL_X44:
+ case PCI_DEVICE_ID_INTEL_82X38:
case PCI_DEVICE_ID_INTEL_32X0:
- case PCI_DEVICE_ID_INTEL_GS45:
+ case PCI_DEVICE_ID_INTEL_82X4X:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
break;
case PCI_DEVICE_ID_INTEL_82810:
- case PCI_DEVICE_ID_INTEL_82810DC:
- case PCI_DEVICE_ID_INTEL_82810E_MC:
+ case PCI_DEVICE_ID_INTEL_82810_DC:
+ case PCI_DEVICE_ID_INTEL_82810E_DC:
case PCI_DEVICE_ID_INTEL_82865:
printf("This northbridge does not have DMIBAR.\n");
return 1;
- case PCI_DEVICE_ID_INTEL_X58:
+ case PCI_DEVICE_ID_INTEL_82X58:
dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
break;
- case PCI_DEVICE_ID_INTEL_HM65E:
- dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000;
+ case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
+ dmibar_phys = pci_read_long(nb, 0x68);
+ dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
+ dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */
+ dmi_registers = NULL; /* No public documentation */
+ break;
+ case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
dmi_registers = sandybridge_dmi_registers;
size = ARRAY_SIZE(sandybridge_dmi_registers);
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
+ dmibar_phys = pci_read_long(nb, 0x68);
+ dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
+ dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
break;
default:
printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
@@ -251,22 +260,22 @@ int print_pciexbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82975X:
pciexbar_reg = pci_read_long(nb, 0x48);
break;
- case PCI_DEVICE_ID_INTEL_PM965:
- case PCI_DEVICE_ID_INTEL_Q965:
- case PCI_DEVICE_ID_INTEL_82Q35:
- case PCI_DEVICE_ID_INTEL_82G33:
- case PCI_DEVICE_ID_INTEL_82Q33:
- case PCI_DEVICE_ID_INTEL_X44:
+ case PCI_DEVICE_ID_INTEL_82965PM:
+ case PCI_DEVICE_ID_INTEL_82Q965:
+ case PCI_DEVICE_ID_INTEL_82Q35:
+ case PCI_DEVICE_ID_INTEL_82G33:
+ case PCI_DEVICE_ID_INTEL_82Q33:
+ case PCI_DEVICE_ID_INTEL_82X38:
case PCI_DEVICE_ID_INTEL_32X0:
- case PCI_DEVICE_ID_INTEL_GS45:
+ case PCI_DEVICE_ID_INTEL_82X4X:
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
- pciexbar_reg = pci_read_long(nb, 0x60);
- pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
- break;
+ pciexbar_reg = pci_read_long(nb, 0x60);
+ pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
+ break;
case PCI_DEVICE_ID_INTEL_82810:
- case PCI_DEVICE_ID_INTEL_82810DC:
- case PCI_DEVICE_ID_INTEL_82810E_MC:
+ case PCI_DEVICE_ID_INTEL_82810_DC:
+ case PCI_DEVICE_ID_INTEL_82810E_DC:
case PCI_DEVICE_ID_INTEL_82865:
printf("Error: This northbridge does not have PCIEXBAR.\n");
return 1;
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 09:35:43 +0000