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-rw-r--r--util/inteltool/cpu.c67
-rw-r--r--util/inteltool/inteltool.c3
-rw-r--r--util/inteltool/inteltool.h3
-rw-r--r--util/inteltool/memory.c3
-rw-r--r--util/inteltool/pcie.c4
-rw-r--r--util/inteltool/powermgt.c69
6 files changed, 142 insertions, 7 deletions
diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index 9427fee9d5..7c0dec15e4 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -1,7 +1,7 @@
/*
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
- * Copyright (C) 2008 by coresystems GmbH
+ * Copyright (C) 2008-2010 by coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -97,6 +97,67 @@ int print_intel_core_msrs(void)
char *name;
} msr_entry_t;
+ static const msr_entry_t model6bx_global_msrs[] = {
+ { 0x0010, "IA32_TIME_STAMP_COUNTER" },
+ { 0x0017, "IA32_PLATFORM_ID" },
+ { 0x001b, "IA32_APIC_BASE" },
+ { 0x002a, "EBL_CR_POWERON" },
+ { 0x0033, "TEST_CTL" },
+ { 0x003f, "THERM_DIODE_OFFSET" },
+ //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
+ { 0x008b, "IA32_BIOS_SIGN_ID" },
+ { 0x00c1, "PERFCTR0" },
+ { 0x00c2, "PERFCTR1" },
+ { 0x011e, "BBL_CR_CTL3" },
+ { 0x0179, "IA32_MCG_CAP" },
+ { 0x017a, "IA32_MCG_STATUS" },
+ { 0x0198, "IA32_PERF_STATUS" },
+ { 0x0199, "IA32_PERF_CONTROL" },
+ { 0x019a, "IA32_CLOCK_MODULATION" },
+ { 0x01a0, "IA32_MISC_ENABLES" },
+ { 0x01d9, "IA32_DEBUGCTL" },
+ { 0x0200, "IA32_MTRR_PHYSBASE0" },
+ { 0x0201, "IA32_MTRR_PHYSMASK0" },
+ { 0x0202, "IA32_MTRR_PHYSBASE1" },
+ { 0x0203, "IA32_MTRR_PHYSMASK1" },
+ { 0x0204, "IA32_MTRR_PHYSBASE2" },
+ { 0x0205, "IA32_MTRR_PHYSMASK2" },
+ { 0x0206, "IA32_MTRR_PHYSBASE3" },
+ { 0x0207, "IA32_MTRR_PHYSMASK3" },
+ { 0x0208, "IA32_MTRR_PHYSBASE4" },
+ { 0x0209, "IA32_MTRR_PHYSMASK4" },
+ { 0x020a, "IA32_MTRR_PHYSBASE5" },
+ { 0x020b, "IA32_MTRR_PHYSMASK5" },
+ { 0x020c, "IA32_MTRR_PHYSBASE6" },
+ { 0x020d, "IA32_MTRR_PHYSMASK6" },
+ { 0x020e, "IA32_MTRR_PHYSBASE7" },
+ { 0x020f, "IA32_MTRR_PHYSMASK7" },
+ { 0x0250, "IA32_MTRR_FIX64K_00000" },
+ { 0x0258, "IA32_MTRR_FIX16K_80000" },
+ { 0x0259, "IA32_MTRR_FIX16K_A0000" },
+ { 0x0268, "IA32_MTRR_FIX4K_C0000" },
+ { 0x0269, "IA32_MTRR_FIX4K_C8000" },
+ { 0x026a, "IA32_MTRR_FIX4K_D0000" },
+ { 0x026b, "IA32_MTRR_FIX4K_D8000" },
+ { 0x026c, "IA32_MTRR_FIX4K_E0000" },
+ { 0x026d, "IA32_MTRR_FIX4K_E8000" },
+ { 0x026e, "IA32_MTRR_FIX4K_F0000" },
+ { 0x026f, "IA32_MTRR_FIX4K_F8000" },
+ { 0x02ff, "IA32_MTRR_DEF_TYPE" },
+ { 0x0400, "IA32_MC0_CTL" },
+ { 0x0401, "IA32_MC0_STATUS" },
+ { 0x0402, "IA32_MC0_ADDR" },
+ //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
+ { 0x040c, "IA32_MC4_CTL" },
+ { 0x040d, "IA32_MC4_STATUS" },
+ { 0x040e, "IA32_MC4_ADDR" },
+ //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
+ };
+
+ static const msr_entry_t model6bx_per_core_msrs[] = {
+ // single core only
+ };
+
static const msr_entry_t model6ex_global_msrs[] = {
{ 0x0017, "IA32_PLATFORM_ID" },
{ 0x002a, "EBL_CR_POWERON" },
@@ -259,6 +320,7 @@ int print_intel_core_msrs(void)
} cpu_t;
cpu_t cpulist[] = {
+ { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
};
@@ -315,7 +377,8 @@ int print_intel_core_msrs(void)
if (fd_msr < 0)
break;
#endif
- printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
+ if (cpu->num_per_core_msrs)
+ printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
for (i = 0; i < cpu->num_per_core_msrs; i++) {
msr = rdmsr(cpu->per_core_msrs[i].number);
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 64f55e87bf..6f7530067c 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -1,7 +1,7 @@
/*
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
- * Copyright (C) 2008 by coresystems GmbH
+ * Copyright (C) 2008-2010 by coresystems GmbH
* written by Stefan Reinauer <stepan@coresystems.de>
*
* This program is free software; you can redistribute it and/or modify
@@ -34,6 +34,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 8a5994dfab..db386d0c93 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -1,7 +1,7 @@
/*
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
- * Copyright (C) 2008 by coresystems GmbH
+ * Copyright (C) 2008-2010 by coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -47,6 +47,7 @@
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
+#define PCI_DEVICE_ID_INTEL_82830M 0x3575
#define PCI_DEVICE_ID_INTEL_82845 0x1a30
#define PCI_DEVICE_ID_INTEL_82945P 0x2770
#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index aad16fcb3c..b0db13ce20 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -1,7 +1,7 @@
/*
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
- * Copyright (C) 2008 by coresystems GmbH
+ * Copyright (C) 2008-2010 by coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -50,6 +50,7 @@ int print_mchbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_82443BX:
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82830M:
printf("This northbrigde does not have MCHBAR.\n");
return 1;
default:
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index bcb7f96b34..81e71e1a4f 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -1,7 +1,7 @@
/*
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
- * Copyright (C) 2008 by coresystems GmbH
+ * Copyright (C) 2008-2010 by coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -47,6 +47,7 @@ int print_epbar(struct pci_dev *nb)
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82830M:
printf("This northbrigde does not have EPBAR.\n");
return 1;
default:
@@ -97,6 +98,7 @@ int print_dmibar(struct pci_dev *nb)
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82830M:
printf("This northbrigde does not have DMIBAR.\n");
return 1;
default:
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index d479bfdc06..fbf9e3a07a 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -1,7 +1,7 @@
/*
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
- * Copyright (C) 2008 by coresystems GmbH
+ * Copyright (C) 2008-2010 by coresystems GmbH
* written by Stefan Reinauer <stepan@coresystems.de>
*
* This program is free software; you can redistribute it and/or modify
@@ -145,6 +145,68 @@ static const io_register_t ich8_pm_registers[] = {
{ 0x7c, 4, "RESERVED" },
};
+static const io_register_t ich4_pm_registers[] = {
+ { 0x00, 2, "PM1_STS" },
+ { 0x02, 2, "PM1_EN" },
+ { 0x04, 4, "PM1_CNT" },
+ { 0x08, 4, "PM1_TMR" },
+ { 0x0c, 4, "RESERVED" },
+ { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+ /* These registers return 0 on read, but reading them may cause
+ * the system to enter C2/C3/C4 state, which might hang the system.
+ */
+ { 0x14, 1, "LV2 (Mobile)" },
+ { 0x15, 1, "LV3 (Mobile)" },
+ { 0x16, 1, "LV4 (Mobile)" },
+#endif
+ { 0x17, 1, "RESERVED" },
+ { 0x18, 4, "RESERVED" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 1, "PM2_CNT (Mobile)" },
+ { 0x21, 1, "RESERVED" },
+ { 0x22, 2, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 4, "GPE0_STS" },
+ { 0x2C, 4, "GPE0_EN" },
+ { 0x30, 4, "SMI_EN" },
+ { 0x34, 4, "SMI_STS" },
+ { 0x38, 2, "ALT_GP_SMI_EN" },
+ { 0x3a, 2, "ALT_GP_SMI_STS" },
+ { 0x3c, 4, "RESERVED" },
+ { 0x40, 2, "MON_SMI" },
+ { 0x42, 2, "RESERVED" },
+ { 0x44, 2, "DEVACT_STS" },
+ { 0x46, 2, "RESERVED" },
+ { 0x48, 4, "DEVTRAP_EN" },
+ { 0x4c, 2, "BUS_ADDR_TRACK" },
+ { 0x4e, 2, "BUS_CYC_TRACK" },
+ { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
+ { 0x51, 1, "RESERVED" },
+ { 0x52, 2, "RESERVED" },
+ { 0x54, 4, "RESERVED" },
+ { 0x58, 4, "RESERVED" },
+ { 0x5c, 4, "RESERVED" },
+ /* Here start the TCO registers */
+ { 0x60, 1, "TCO_RLD" },
+ { 0x61, 1, "TCO_TMR" },
+ { 0x62, 1, "TCO_DAT_IN" },
+ { 0x63, 1, "TCO_DAT_OUT" },
+ { 0x64, 2, "TCO1_STS" },
+ { 0x66, 2, "TCO2_STS" },
+ { 0x68, 2, "TCO1_CNT" },
+ { 0x6a, 2, "TCO2_CNT" },
+ { 0x6c, 2, "TCO_MESSAGE" },
+ { 0x6e, 1, "TCO_WDSTATUS" },
+ { 0x6f, 1, "RESERVED" },
+ { 0x70, 1, "SW_IRQ_GEN" },
+ { 0x71, 1, "RESERVED" },
+ { 0x72, 2, "RESERVED" },
+ { 0x74, 4, "RESERVED" },
+ { 0x78, 4, "RESERVED" },
+ { 0x7c, 4, "RESERVED" },
+};
+
static const io_register_t ich0_pm_registers[] = {
{ 0x00, 2, "PM1_STS" },
{ 0x02, 2, "PM1_EN" },
@@ -269,6 +331,11 @@ int print_pmbase(struct pci_dev *sb)
pm_registers = ich8_pm_registers;
size = ARRAY_SIZE(ich8_pm_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH4:
+ pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+ pm_registers = ich4_pm_registers;
+ size = ARRAY_SIZE(ich4_pm_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH0:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich0_pm_registers;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 01:17:49 +0000