diff options
| -rw-r--r-- | src/northbridge/intel/gm45/acpi/hostbridge.asl | 19 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 42 |
2 files changed, 54 insertions, 7 deletions
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index 2a8a137726..ff86b3fca8 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -188,6 +188,12 @@ Name (MCRS, ResourceTemplate() 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, IO_APIC_ADDR,,, PM01) + /* PCI Memory Region above 4G TOUUD -> 1 << cpu_addr_bits */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM02) + /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, @@ -195,6 +201,9 @@ Name (MCRS, ResourceTemplate() 0x00005000,,, TPMR) }) +External (A4GS, IntObj) +External (A4GB, IntObj) + /* Current Resource Settings */ Method (_CRS, 0, Serialized) { @@ -211,5 +220,15 @@ Method (_CRS, 0, Serialized) PMIN = ^MCHC.TLUD << 20 PLEN = PMAX - PMIN + 1 + if (A4GS != 0) { + CreateQwordField(MCRS, ^PM02._MIN, MMIN) + CreateQwordField(MCRS, ^PM02._MAX, MMAX) + CreateQwordField(MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + MLEN = A4GS + MMIN = A4GB + MMAX = MMIN + MLEN - 1 + } + Return (MCRS) } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 561c2fce8e..b533de9198 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -1,19 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <boot/tables.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/smm_reloc.h> +#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <stdint.h> -#include <device/device.h> -#include <boot/tables.h> -#include <acpi/acpi.h> -#include <cpu/intel/smm_reloc.h> #include "chip.h" #include "gm45.h" +static uint64_t get_touud(void) +{ + uint64_t touud = pci_read_config16(__pci_0_00_0, D0F0_TOUUD); + touud <<= 20; + return touud; +} + static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; @@ -43,8 +52,7 @@ static void mch_domain_read_resources(struct device *dev) struct device *mch = pcidev_on_root(0, 0); /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config16(mch, D0F0_TOUUD); - touud <<= 20; + touud = get_touud(); /* Top of Lower Usable DRAM */ tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; @@ -176,13 +184,33 @@ void northbridge_write_smram(u8 smram) pci_write_config8(dev, D0F0_SMRAM, smram); } +static void set_above_4g_pci(const struct device *dev) +{ + const uint64_t touud = get_touud(); + const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud; + + const char *scope = acpi_device_path(dev); + acpigen_write_scope(scope); + acpigen_write_name_qword("A4GB", touud); + acpigen_write_name_qword("A4GS", len); + acpigen_pop_len(); + + printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len); +} + +static void pci_domain_ssdt(const struct device *dev) +{ + generate_cpu_entries(dev); + set_above_4g_pci(dev); +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt = generate_cpu_entries, + .acpi_fill_ssdt = pci_domain_ssdt, .acpi_name = northbridge_acpi_name, }; |