diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2021-05-21 16:16:05 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-28 18:25:26 +0000 |
| commit | eab9290b5f77880bfefd0215ffb7e9844c76b5a2 (patch) | |
| tree | eade09511983ecf8364b765f83fa375d6828f3bc /util | |
| parent | 05b6b37a7c8703416d6ebfaaa860f3b2dad33fa0 (diff) | |
vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake
Update FSP headers for Tiger Lake platform generated based on FSP
version 4133 to include post PRQ UPDs.
BUG=b:188452018
BRANCH=none
TEST=build voxel
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
0 files changed, 0 insertions, 0 deletions