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authorMarx Wang <marx.wang@intel.com>2020-02-07 16:44:14 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-25 10:11:02 +0000
commit9318d6d6251dcc5ae243a377d15d407a066ec46f (patch)
tree4ed813f2fc7dfd0ea9829cb6e297849a0561e7e8 /util
parent75cd6d2a97a3d5630e74ca099ddb702be143415e (diff)
soc/intel/cannonlake: Add TDC config for CML
Add Thermal Design Current (TDC) defaults for CML: 1. TdcEnable 2. TdcPowerLimit BUG=b:148912093 BRANCH=None TEST=build coreboot and Intel FSP with fw_debug enabled, flash image to the device, capture the log from the serial port during boot-up and check TdcEnable and TdcPowerLimit for each domain in captured log Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: Ie4b17e5b4ce41c1adb436ae5646f0d8578a440e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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