diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-11-19 14:02:29 -0700 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-12-11 19:36:23 +0000 |
| commit | 13ec029145d60fcb6de460046f1edc162b5ca095 (patch) | |
| tree | 46735c8a79a9de2ec0871f1b847915a0f258eeef /util | |
| parent | 5446bdb270be409eaf5a0a60d86ebeb2ec4358ad (diff) | |
util/amdfwtool: Fix EFS generation polarity
The DWORD used to indicate the Embedded Firmware Structure's generation
uses 1 to indicate a first-gen structure, e.g. a SPI device's erased
value of 0xffffffff. A 0 in bit 0 is how Client PSPs will interpret
the structure as designed for second-gen.
This change and the original addition should have no effects on
any current products as none interpret offset 0x24.
BUG=b:158755102
TEST=inspect EFS in coreboot.rom
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'util')
| -rw-r--r-- | util/amdfwtool/amdfwtool.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 9cf6a4f8c0..401cf20d6c 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -323,6 +323,13 @@ amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_INVALID }, }; +struct second_gen_efs { /* todo: expand for Server products */ + int gen:1; /* Client products only use bit 0 */ + int reserved:31; +} __attribute__((packed)); + +#define EFS_SECOND_GEN 0 + typedef struct _embedded_firmware { uint32_t signature; /* 0x55aa55aa */ uint32_t imc_entry; @@ -333,7 +340,7 @@ typedef struct _embedded_firmware { uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; - uint32_t second_gen_efs; + struct second_gen_efs efs_gen; uint32_t bios3_entry; uint32_t reserved_2Ch; uint32_t promontory_fw_ptr; @@ -1182,13 +1189,13 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, } switch (soc_id) { case PLATFORM_STONEYRIDGE: - amd_romsig->second_gen_efs = 0; amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; break; case PLATFORM_RAVEN: case PLATFORM_PICASSO: - amd_romsig->second_gen_efs = 0; + /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. + * Leave as 0xffffffff for first gen */ amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1205,7 +1212,7 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, break; case PLATFORM_RENOIR: case PLATFORM_LUCIENNE: - amd_romsig->second_gen_efs = 1; + amd_romsig->efs_gen.gen = EFS_SECOND_GEN; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; switch (efs_spi_micron_flag) { |