diff options
author | Nick Vaccaro <nvaccaro@google.com> | 2020-05-12 12:13:07 -0700 |
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committer | Nick Vaccaro <nvaccaro@google.com> | 2020-05-21 23:58:29 +0000 |
commit | 105e02d4fd99dba55d603d010802eebdebeee535 (patch) | |
tree | c0ffb2222ff2954d2c2269087494d8e35af6b5dd /util/xcompile | |
parent | 712311f56e2f9fec0124ca7903078dc180abf81c (diff) |
mb/google/volteer: fix error in generic SPD
The SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex SPD
contained an incorrect SDRAM Max Cycle Time (0 instead of 0x0f).
After fixing that error, I noticed that two generic SPDs could
be collapsed into one, so I removed one of the duplicate generic
SPDs (SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_16Row_DDP_4267.spd.hex),
and changed Makefile to collapse volteer's DRAM ID 2 into ID 0.
BUG=b:156126658, b:156058720
TEST=Flash and boot a ripto to kernel. Also verified that ripto
can boot successfully to the kernel at 4267 MT/sec with FSP built
in debug mode with RMT enabled.
Change-Id: Ib52bf674ebf91854d3d078015aa640aa7ee98a6f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41345
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/xcompile')
0 files changed, 0 insertions, 0 deletions