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authorFelix Held <felix-coreboot@felixheld.de>2023-08-04 19:40:02 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-08-08 19:47:26 +0000
commit4eac0d4d830d0cb85bbc265c58ae5dd91711d72e (patch)
tree33b6b8721689f06d39573c570bb455b99f20cf6c /util/spdtool
parent3cef7d3f121427f4358755b4efbc375ddb1f7aa8 (diff)
soc/amd/common/data_fabric/domain: read IO decode windows from registers
Before add_io_regions only reported one fixed IO range to the resource allocator that covered the whole IO range from 0x0000 to 0xffff. Instead read the data fabric IO space decode base and limit address register pairs to get the actual IO port decoding from the data fabric registers. This will also help with adding support for multiple PCI root domains to the common data fabric domain code so that Genoa can use it. In that case each PCI root domain will only decode a part of the whole IO port range. Beware that the data fabric IO base and limit fields can contain values that correspond to IO port addresses far outside of the addressable IO port range. In case of Picasso, the IO limit read from the only enabled DF IO range register would be 0x1ffffff after converting the raw data to an IO port address. To not give the resource allocator wrong constraints make sure that the IO limit we report will be at maximum 0xffff. TEST=On Mandolin (Picasso) and Birman (Phoenix) the full range of IO port addresses still gets reported as a domain IO resource producer like before the patch: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I087d96f7bdaae0d7b53089f6abaf0500a4b064e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
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