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| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-17 14:07:35 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-21 16:29:55 +0000 |
| commit | 7e9cb9281581fdf1b75ef5e6f32a1ec322e11c8f (patch) | |
| tree | 920d7598a47db1ce343d54505d8bbc526c7d71b2 /util/romcc | |
| parent | ce4c9ec4f61cfba8a25adf74ad40d582859ea8b8 (diff) | |
soc/intel/skylake: Add support for all UART port index
Select LPSS UART Base address based on LPSS UART port index.
Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/romcc')
0 files changed, 0 insertions, 0 deletions