diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-28 16:14:56 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-27 09:00:16 +0000 |
| commit | 945b698f82279fdb42f83f6a3eb2e6f74db2869c (patch) | |
| tree | 3eac3bd7ec5032441081d89a370acddf8f3e5f5b /util/romcc/tests | |
| parent | c2092569d5d21e0cdd3690d8021c2d46dfeaeabd (diff) | |
util/romcc: Drop romcc support
Finally all boards use a GCC compiled bootblock!
Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37337
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/romcc/tests')
128 files changed, 0 insertions, 23679 deletions
diff --git a/util/romcc/tests/fail_test1.c b/util/romcc/tests/fail_test1.c deleted file mode 100644 index 4f0b47d043..0000000000 --- a/util/romcc/tests/fail_test1.c +++ /dev/null @@ -1,5 +0,0 @@ -static void main(void) -{ - int i; - i|=0x80; -} diff --git a/util/romcc/tests/fail_test10.c b/util/romcc/tests/fail_test10.c deleted file mode 100644 index 58e9d8f2a1..0000000000 --- a/util/romcc/tests/fail_test10.c +++ /dev/null @@ -1,18 +0,0 @@ - - -struct result { - int a, b, c, d; -}; - -struct big_arg { - int a, b; -}; -static struct result main(int a, int b, struct big_arg d) -{ - struct result result; - result.a = 1; - result.b = 1; - result.c = b + 1; - result.d = a + 1; - -} diff --git a/util/romcc/tests/fail_test11.c b/util/romcc/tests/fail_test11.c deleted file mode 100644 index 0b3bf5f4e9..0000000000 --- a/util/romcc/tests/fail_test11.c +++ /dev/null @@ -1,20 +0,0 @@ - - -struct big_arg { - int x, y; -}; -struct result { - struct big_arg a; - int c, d; -}; - -static struct result main(int a, int b, int c, int d) -{ - struct result result; - result.a.x = d + 1; - result.a.y = c + 1; - result.c = b + 1; - result.d = a + 1; - - return result; -} diff --git a/util/romcc/tests/fail_test2.c b/util/romcc/tests/fail_test2.c deleted file mode 100644 index 6a02486a8d..0000000000 --- a/util/romcc/tests/fail_test2.c +++ /dev/null @@ -1,18 +0,0 @@ -static void main(void) -{ - - unsigned min; - int value, latency; - - - latency = -2; - - if (latency > (((min) >> 8) & 0xff)) { - value = 0xa; - } - - if (value < 0) return; - - ((min) = (((min) & ~0xff))); - -} diff --git a/util/romcc/tests/fail_test3.c b/util/romcc/tests/fail_test3.c deleted file mode 100644 index 84822839db..0000000000 --- a/util/romcc/tests/fail_test3.c +++ /dev/null @@ -1,10 +0,0 @@ -static void main(void) -{ - volatile unsigned long *val = (volatile unsigned long *)0x1234; - int i; - if (val[0] > 25) { - i = 7; - } - val[1] = i; - -} diff --git a/util/romcc/tests/fail_test4.c b/util/romcc/tests/fail_test4.c deleted file mode 100644 index a2d3bece66..0000000000 --- a/util/romcc/tests/fail_test4.c +++ /dev/null @@ -1,14 +0,0 @@ -static void main(void) -{ - static const int foo = 2; - switch(foo) { - case 1: - break; - case 2: - break; - case 1: - break; - default: - break; - } -} diff --git a/util/romcc/tests/fail_test5.c b/util/romcc/tests/fail_test5.c deleted file mode 100644 index efa4e76d91..0000000000 --- a/util/romcc/tests/fail_test5.c +++ /dev/null @@ -1,14 +0,0 @@ -static void main(void) -{ - static const int foo = 2; - switch(foo) { - case 1: - break; - default: - break; - case 2: - break; - default: - break; - } -} diff --git a/util/romcc/tests/fail_test6.c b/util/romcc/tests/fail_test6.c deleted file mode 100644 index cc7bcf52c6..0000000000 --- a/util/romcc/tests/fail_test6.c +++ /dev/null @@ -1,11 +0,0 @@ - - -static void hlt(void) -{ -} - -static void main(void) -{ - void *foo; - foo = hlt; -} diff --git a/util/romcc/tests/fail_test7.c b/util/romcc/tests/fail_test7.c deleted file mode 100644 index e7a0db93d3..0000000000 --- a/util/romcc/tests/fail_test7.c +++ /dev/null @@ -1,10 +0,0 @@ - - -static void hlt(void) -{ -} - -static void main(void) -{ - &hlt; -} diff --git a/util/romcc/tests/fail_test8.c b/util/romcc/tests/fail_test8.c deleted file mode 100644 index 10ade55f75..0000000000 --- a/util/romcc/tests/fail_test8.c +++ /dev/null @@ -1,10 +0,0 @@ - - -static void hlt(void) -{ -} - -static void main(void) -{ - hlt; -} diff --git a/util/romcc/tests/fail_test9.c b/util/romcc/tests/fail_test9.c deleted file mode 100644 index d216a6d528..0000000000 --- a/util/romcc/tests/fail_test9.c +++ /dev/null @@ -1,8 +0,0 @@ -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -#warning "romcc should die gracefully here" diff --git a/util/romcc/tests/hello_world.c b/util/romcc/tests/hello_world.c deleted file mode 100644 index cba88a9a6d..0000000000 --- a/util/romcc/tests/hello_world.c +++ /dev/null @@ -1,128 +0,0 @@ -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#if CONFIG_TTYS0_BAUD == 115200 -#define CONFIG_TTYS0_DIV (1) -#else -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) -#endif - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - - -void __console_tx_char(unsigned char byte) -{ - uart_tx_byte(byte); - -} - -void __console_tx_string(char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_char(ch); - } -} - - -void print_debug_char(unsigned char byte) { __console_tx_char(byte); } -void print_debug(char *str) { __console_tx_string(str); } - -void main(void) -{ - static const char msg[] = "hello world\r\n"; - uart_init(); -#if 0 - print_debug(msg); -#endif -#if 1 - print_debug("hello world\r\n"); - print_debug("how are you today\r\n"); -#endif - while(1) { - ; - } -} diff --git a/util/romcc/tests/hello_world1.c b/util/romcc/tests/hello_world1.c deleted file mode 100644 index cba88a9a6d..0000000000 --- a/util/romcc/tests/hello_world1.c +++ /dev/null @@ -1,128 +0,0 @@ -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#if CONFIG_TTYS0_BAUD == 115200 -#define CONFIG_TTYS0_DIV (1) -#else -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) -#endif - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - - -void __console_tx_char(unsigned char byte) -{ - uart_tx_byte(byte); - -} - -void __console_tx_string(char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_char(ch); - } -} - - -void print_debug_char(unsigned char byte) { __console_tx_char(byte); } -void print_debug(char *str) { __console_tx_string(str); } - -void main(void) -{ - static const char msg[] = "hello world\r\n"; - uart_init(); -#if 0 - print_debug(msg); -#endif -#if 1 - print_debug("hello world\r\n"); - print_debug("how are you today\r\n"); -#endif - while(1) { - ; - } -} diff --git a/util/romcc/tests/hello_world2.c b/util/romcc/tests/hello_world2.c deleted file mode 100644 index c6e8092ed3..0000000000 --- a/util/romcc/tests/hello_world2.c +++ /dev/null @@ -1,127 +0,0 @@ -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#if CONFIG_TTYS0_BAUD == 115200 -#define CONFIG_TTYS0_DIV (1) -#else -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) -#endif - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - - -void __console_tx_char(unsigned char byte) -{ - uart_tx_byte(byte); - -} - -void __console_tx_string(char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_char(ch); - } -} - - -void print_debug_char(unsigned char byte) { __console_tx_char(byte); } -void print_debug(char *str) { __console_tx_string(str); } - -void main(void) -{ - static const char msg[] = "hello world\r\n"; - uart_init(); -#if 0 - print_debug(msg); -#endif -#if 1 - print_debug("hello world\r\n"); -#endif - while(1) { - ; - } -} diff --git a/util/romcc/tests/include/linux_console.h b/util/romcc/tests/include/linux_console.h deleted file mode 100644 index 5f9dec21f9..0000000000 --- a/util/romcc/tests/include/linux_console.h +++ /dev/null @@ -1,136 +0,0 @@ -#ifndef LINUX_CONSOLE_H -#define LINUX_CONSOLE_H - -#include "linux_syscall.h" - -static const char *addr_of_char(unsigned char ch) -{ - static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - return byte + ch; -} - -static void console_tx_byte(unsigned char ch) -{ - write(STDOUT_FILENO, addr_of_char(ch), 1); -} - -static inline void console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - console_tx_byte(digit); -} - -static void console_tx_char(unsigned char byte) -{ - console_tx_byte(byte); -} - -static void console_tx_hex8(unsigned char value) -{ - console_tx_nibble((value >> 4U) & 0x0fU); - console_tx_nibble(value & 0x0fU); -} - -static void console_tx_hex16(unsigned short value) -{ - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_hex32(unsigned int value) -{ - console_tx_nibble((value >> 28U) & 0x0FU); - console_tx_nibble((value >> 24U) & 0x0FU); - console_tx_nibble((value >> 20U) & 0x0FU); - console_tx_nibble((value >> 16U) & 0x0FU); - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_string(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - console_tx_byte(ch); - } -} - -static void print_emerg_char(unsigned char byte) { console_tx_char(byte); } -static void print_emerg_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_emerg_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_emerg_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_emerg(const char *str) { console_tx_string(str); } - -static void print_warn_char(unsigned char byte) { console_tx_char(byte); } -static void print_warn_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_warn_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_warn_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_warn(const char *str) { console_tx_string(str); } - -static void print_info_char(unsigned char byte) { console_tx_char(byte); } -static void print_info_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_info_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_info_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_info(const char *str) { console_tx_string(str); } - -static void print_debug_char(unsigned char byte) { console_tx_char(byte); } -static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_debug(const char *str) { console_tx_string(str); } - -static void print_spew_char(unsigned char byte) { console_tx_char(byte); } -static void print_spew_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_spew_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_spew_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_spew(const char *str) { console_tx_string(str); } - -static void die(const char *str) -{ - print_emerg(str); - do { - asm volatile (" "); - } while(1); -} -#endif /* LINUX_CONSOLE_H */ diff --git a/util/romcc/tests/include/linux_syscall.h b/util/romcc/tests/include/linux_syscall.h deleted file mode 100644 index 487095f712..0000000000 --- a/util/romcc/tests/include/linux_syscall.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef LINUX_SYSCALL_H -#define LINUX_SYSCALL_H - -/* When I support other platforms use #ifdefs here */ -#include "linuxi386_syscall.h" - -#endif /* LINUX_SYSCALL_H */ diff --git a/util/romcc/tests/include/linuxi386_syscall.h b/util/romcc/tests/include/linuxi386_syscall.h deleted file mode 100644 index 30b4a2c6e0..0000000000 --- a/util/romcc/tests/include/linuxi386_syscall.h +++ /dev/null @@ -1,299 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static inline struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} - -static struct syscall_result syscall0(unsigned long nr) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr)); - return syscall_return(res); -} - -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - -static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2)); - return syscall_return(res); - -} - - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); - return syscall_return(res); - -} - -static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, unsigned long arg5) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), - "S" (arg4), "D" (arg5)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_fork 2 -#define NR_read 3 -#define NR_write 4 -#define NR_open 5 -#define NR_close 6 -#define NR_waitpid 7 -#define NR_creat 8 -#define NR_link 9 -#define NR_unlink 10 -#define NR_execve 11 -#define NR_chdir 12 -#define NR_time 13 -#define NR_mknod 14 -#define NR_chmod 15 -#define NR_lchown 16 -#define NR_break 17 -#define NR_oldstat 18 -#define NR_lseek 19 -#define NR_getpid 20 -#define NR_mount 21 -#define NR_umount 22 -#define NR_setuid 23 -#define NR_getuid 24 -#define NR_stime 25 -#define NR_ptrace 26 -#define NR_alarm 27 -#define NR_oldfstat 28 -#define NR_pause 29 -#define NR_utime 30 -#define NR_stty 31 -#define NR_gtty 32 -#define NR_access 33 -#define NR_nice 34 -#define NR_ftime 35 -#define NR_sync 36 -#define NR_kill 37 -#define NR_rename 38 -#define NR_mkdir 39 -#define NR_rmdir 40 -#define NR_dup 41 -#define NR_pipe 42 -#define NR_times 43 -#define NR_prof 44 -#define NR_brk 45 -#define NR_setgid 46 -#define NR_getgid 47 -#define NR_signal 48 -#define NR_geteuid 49 -#define NR_getegid 50 -#define NR_acct 51 -#define NR_umount2 52 -#define NR_lock 53 -#define NR_ioctl 54 -#define NR_fcntl 55 -#define NR_mpx 56 -#define NR_setpgid 57 -#define NR_ulimit 58 -#define NR_oldolduname 59 -#define NR_umask 60 -#define NR_chroot 61 -#define NR_ustat 62 -#define NR_dup2 63 -#define NR_getppid 64 -#define NR_getpgrp 65 -#define NR_setsid 66 -#define NR_sigaction 67 -#define NR_sgetmask 68 -#define NR_ssetmask 69 -#define NR_setreuid 70 -#define NR_setregid 71 -#define NR_sigsuspend 72 -#define NR_sigpending 73 -#define NR_sethostname 74 -#define NR_setrlimit 75 -#define NR_getrlimit 76 -#define NR_getrusage 77 -#define NR_gettimeofday 78 -#define NR_settimeofday 79 -#define NR_getgroups 80 -#define NR_setgroups 81 -#define NR_select 82 -#define NR_symlink 83 -#define NR_oldlstat 84 -#define NR_readlink 85 -#define NR_uselib 86 -#define NR_swapon 87 -#define NR_reboot 88 -#define NR_readdir 89 -#define NR_mmap 90 -#define NR_munmap 91 -#define NR_truncate 92 -#define NR_ftruncate 93 -#define NR_fchmod 94 -#define NR_fchown 95 -#define NR_getpriority 96 -#define NR_setpriority 97 -#define NR_profil 98 -#define NR_statfs 99 -#define NR_fstatfs 100 -#define NR_ioperm 101 -#define NR_socketcall 102 -#define NR_syslog 103 -#define NR_setitimer 104 -#define NR_getitimer 105 -#define NR_stat 106 -#define NR_lstat 107 -#define NR_fstat 108 -#define NR_olduname 109 -#define NR_iopl 110 -#define NR_vhangup 111 -#define NR_idle 112 -#define NR_vm86old 113 -#define NR_wait4 114 -#define NR_swapoff 115 -#define NR_sysinfo 116 -#define NR_ipc 117 -#define NR_fsync 118 -#define NR_sigreturn 119 -#define NR_clone 120 -#define NR_setdomainname 121 -#define NR_uname 122 -#define NR_modify_ldt 123 -#define NR_adjtimex 124 -#define NR_mprotect 125 -#define NR_sigprocmask 126 -#define NR_create_module 127 -#define NR_init_module 128 -#define NR_delete_module 129 -#define NR_get_kernel_syms 130 -#define NR_quotactl 131 -#define NR_getpgid 132 -#define NR_fchdir 133 -#define NR_bdflush 134 -#define NR_sysfs 135 -#define NR_personality 136 -#define NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define NR_setfsuid 138 -#define NR_setfsgid 139 -#define NR__llseek 140 -#define NR_getdents 141 -#define NR__newselect 142 -#define NR_flock 143 -#define NR_msync 144 -#define NR_readv 145 -#define NR_writev 146 -#define NR_getsid 147 -#define NR_fdatasync 148 -#define NR__sysctl 149 -#define NR_mlock 150 -#define NR_munlock 151 -#define NR_mlockall 152 -#define NR_munlockall 153 -#define NR_sched_setparam 154 -#define NR_sched_getparam 155 -#define NR_sched_setscheduler 156 -#define NR_sched_getscheduler 157 -#define NR_sched_yield 158 -#define NR_sched_get_priority_max 159 -#define NR_sched_get_priority_min 160 -#define NR_sched_rr_get_interval 161 -#define NR_nanosleep 162 -#define NR_mremap 163 -#define NR_setresuid 164 -#define NR_getresuid 165 -#define NR_vm86 166 -#define NR_query_module 167 -#define NR_poll 168 -#define NR_nfsservctl 169 -#define NR_setresgid 170 -#define NR_getresgid 171 -#define NR_prctl 172 -#define NR_rt_sigreturn 173 -#define NR_rt_sigaction 174 -#define NR_rt_sigprocmask 175 -#define NR_rt_sigpending 176 -#define NR_rt_sigtimedwait 177 -#define NR_rt_sigqueueinfo 178 -#define NR_rt_sigsuspend 179 -#define NR_pread 180 -#define NR_pwrite 181 -#define NR_chown 182 -#define NR_getcwd 183 -#define NR_capget 184 -#define NR_capset 185 -#define NR_sigaltstack 186 -#define NR_sendfile 187 -#define NR_getpmsg 188 /* some people actually want streams */ -#define NR_putpmsg 189 /* some people actually want streams */ -#define NR_vfork 190 - -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -typedef long ssize_t; -typedef unsigned long size_t; - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} diff --git a/util/romcc/tests/ldscript.ld b/util/romcc/tests/ldscript.ld deleted file mode 100644 index fed99ea6fd..0000000000 --- a/util/romcc/tests/ldscript.ld +++ /dev/null @@ -1,21 +0,0 @@ - -ENTRY(_start) - -SECTIONS -{ - . = 0x20000; - __cpu_reset = 0xdeadbeef; - .text . : { - . = ALIGN(16); - _start = . ; - *(.rom.text); - *(.text) - . = ALIGN(16); - } - .data . : { - . = ALIGN(16); - *(.rom.data); - *(.data) - . = ALIGN(16); - } -}
\ No newline at end of file diff --git a/util/romcc/tests/linux_console.h b/util/romcc/tests/linux_console.h deleted file mode 100644 index 1b6466eca1..0000000000 --- a/util/romcc/tests/linux_console.h +++ /dev/null @@ -1,136 +0,0 @@ -#ifndef LINUX_CONSOLE_H -#define LINUX_CONSOLE_H - -#include "linux_syscall.h" - -static const char *addr_of_char(unsigned char ch) -{ - static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - return byte + ch; -} - -static void console_tx_byte(unsigned char ch) -{ - write(STDOUT_FILENO, addr_of_char(ch), 1); -} - -static void console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - console_tx_byte(digit); -} - -static void console_tx_char(unsigned char byte) -{ - console_tx_byte(byte); -} - -static void console_tx_hex8(unsigned char value) -{ - console_tx_nibble((value >> 4U) & 0x0fU); - console_tx_nibble(value & 0x0fU); -} - -static void console_tx_hex16(unsigned short value) -{ - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_hex32(unsigned short value) -{ - console_tx_nibble((value >> 28U) & 0x0FU); - console_tx_nibble((value >> 24U) & 0x0FU); - console_tx_nibble((value >> 20U) & 0x0FU); - console_tx_nibble((value >> 16U) & 0x0FU); - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_string(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - console_tx_byte(ch); - } -} - -static void print_emerg_char(unsigned char byte) { console_tx_char(byte); } -static void print_emerg_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_emerg_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_emerg_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_emerg(const char *str) { console_tx_string(str); } - -static void print_warn_char(unsigned char byte) { console_tx_char(byte); } -static void print_warn_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_warn_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_warn_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_warn(const char *str) { console_tx_string(str); } - -static void print_info_char(unsigned char byte) { console_tx_char(byte); } -static void print_info_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_info_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_info_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_info(const char *str) { console_tx_string(str); } - -static void print_debug_char(unsigned char byte) { console_tx_char(byte); } -static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_debug(const char *str) { console_tx_string(str); } - -static void print_spew_char(unsigned char byte) { console_tx_char(byte); } -static void print_spew_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_spew_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_spew_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_spew(const char *str) { console_tx_string(str); } - -static void die(const char *str) -{ - print_emerg(str); - do { - asm volatile (" "); - } while(1); -} -#endif /* LINUX_CONSOLE_H */ diff --git a/util/romcc/tests/linux_syscall.h b/util/romcc/tests/linux_syscall.h deleted file mode 100644 index 487095f712..0000000000 --- a/util/romcc/tests/linux_syscall.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef LINUX_SYSCALL_H -#define LINUX_SYSCALL_H - -/* When I support other platforms use #ifdefs here */ -#include "linuxi386_syscall.h" - -#endif /* LINUX_SYSCALL_H */ diff --git a/util/romcc/tests/linux_test1.c b/util/romcc/tests/linux_test1.c deleted file mode 100644 index cb435e2a99..0000000000 --- a/util/romcc/tests/linux_test1.c +++ /dev/null @@ -1,8 +0,0 @@ -#include "linux_syscall.h" - -static void main(void) -{ - static const char msg[] = "hello world\n"; - write(STDOUT_FILENO, msg, sizeof(msg)); - _exit(0); -} diff --git a/util/romcc/tests/linux_test10.c b/util/romcc/tests/linux_test10.c deleted file mode 100644 index ef8c930187..0000000000 --- a/util/romcc/tests/linux_test10.c +++ /dev/null @@ -1,57 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - -struct stuff { - signed int a : 5; - signed int b : 6; - signed int c : 2; - unsigned int d : 3; -}; - -static void test(void) -{ - struct stuff var; -#if 0 - int a, b, c, d; - - a = 1; - b = 2; - c = 3; - d = 7; - - var.a = a; - var.b = b; - var.c = c; - var.d = d; - - a = var.a; - b = var.b; - c = var.c; - d = var.d; - - print_debug(" a: "); - print_debug_hex32(a); - print_debug(" b: "); - print_debug_hex32(b); - print_debug(" c: "); - print_debug_hex32(c); - print_debug(" d: "); - print_debug_hex32(d); -#else - var.a = 1; - var.b = 2; - var.c = 3; - var.d = 7; - - print_debug(" a: "); - print_debug_hex32(var.a); - print_debug(" b: "); - print_debug_hex32(var.b); - print_debug(" c: "); - print_debug_hex32(var.c); - print_debug(" d: "); - print_debug_hex32(var.d); -#endif - print_debug("\n"); - _exit(0); -} diff --git a/util/romcc/tests/linux_test11.c b/util/romcc/tests/linux_test11.c deleted file mode 100644 index 9c1183fd87..0000000000 --- a/util/romcc/tests/linux_test11.c +++ /dev/null @@ -1,11 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - -static void test(void) -{ - signed char x; - x = -1; - print_debug_hex32(x); - print_debug("\n"); - _exit(0); -} diff --git a/util/romcc/tests/linux_test12.c b/util/romcc/tests/linux_test12.c deleted file mode 100644 index 5503aa05f0..0000000000 --- a/util/romcc/tests/linux_test12.c +++ /dev/null @@ -1,70 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - -#define MACRO(hello, hello2) 1 - -#ifndef A -#define A 135 -#endif -#define B A -#define C B -#define D C -#define E D -#define F E -#define G F -#define H G -#define I H - -#define FOO() "hah?\n" -#define BAR(X) ( X " There\n" ) -#define BAZ(X) #X -#define SUM(X, Y) ((X) + (Y)) -#define REALLY_SUM(...) SUM(__VA_ARGS__) - - -#define hash_hash # /* comment */ ## # -#define mkstr(a) # a -#define in_between(a) mkstr(a) -#define join(c, d) in_between(c hash_hash d) - -#define ECHO(X) X -#define print_debug(X) ECHO(print_debug(X)) - -static void test(void) -{ - print_debug(FOO()); - print_debug(BAR("Hi!!")); - print_debug(BAZ(This should be shown as a string... "enclosed in quotes") "\n"); - print_debug("This is a quote\" see\n"); - print_debug(BAR(BAZ(I))); - - print_debug_hex32(REALLY_SUM(1,2)); - print_debug("\n"); - - print_debug(join(x, y) "\n"); - - print_debug("romcc: "); - print_debug_hex8(__ROMCC__); - print_debug("."); - print_debug_hex8(__ROMCC_MINOR__); - print_debug("\n"); - - print_debug(__FILE__); - print_debug(":"); - print_debug(__func__); - print_debug(":"); - print_debug_hex32(__LINE__); - print_debug("\n"); - - print_debug("Compiled at: "); - print_debug(__DATE__); - print_debug(" "); - print_debug(__TIME__); - print_debug("\n"); - - print_debug("Compile time: "); - print_debug(__TIME__); - print_debug("\n"); - - _exit(0); -} diff --git a/util/romcc/tests/linux_test13.c b/util/romcc/tests/linux_test13.c deleted file mode 100644 index 9bc80eac7d..0000000000 --- a/util/romcc/tests/linux_test13.c +++ /dev/null @@ -1,47 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - -struct mem_controller { - unsigned short channel0[4]; -}; - -static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) -{ - unsigned dimm_mask; - int i; - - print_debug("1\n"); - dimm_mask = 0; - for(i = 0; i < 4; i++) { - int byte; - unsigned device; - - print_debug("2\n"); - device = ctrl->channel0[i]; - if (device) { - print_debug("3\n"); - byte = ctrl->channel0[i] + 2; - if (byte == 7) { - dimm_mask |= (1 << i); - } - } - print_debug("4\n"); - } - print_debug("5\n"); - return dimm_mask; -} - - -static void main(void) -{ - static const struct mem_controller cpu[] = { - { - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - }, - }; - long dimm_mask; - print_debug("A\n"); - dimm_mask = spd_detect_dimms(cpu); - print_debug("B\n"); - _exit(0); -} diff --git a/util/romcc/tests/linux_test2.c b/util/romcc/tests/linux_test2.c deleted file mode 100644 index c4fbf0a238..0000000000 --- a/util/romcc/tests/linux_test2.c +++ /dev/null @@ -1,673 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - - -static void setup_coherent_ht_domain(void) -{ - static const unsigned int register_values[] = { -#if 1 - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4), - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000, -#else -#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x07) << 8) | \ - ((WHERE) & 0xFF)) - - /* Routing Table Node i - * F0:0x40 i = 0, - * F0:0x44 i = 1, - * F0:0x48 i = 2, - * F0:0x4c i = 3, - * F0:0x50 i = 4, - * F0:0x54 i = 5, - * F0:0x58 i = 6, - * F0:0x5c i = 7 - * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [11: 8] Response Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [19:16] Broadcast route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - */ - PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x48), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x4c), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x50), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x54), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101, - - /* Hypetransport Transaction Control Register - * F0:0x68 - * [ 0: 0] Disable read byte probe - * 0 = Probes issues - * 1 = Probes not issued - * [ 1: 1] Disable Read Doubleword probe - * 0 = Probes issued - * 1 = Probes not issued - * [ 2: 2] Disable write byte probes - * 0 = Probes issued - * 1 = Probes not issued - * [ 3: 3] Disable Write Doubleword Probes - * 0 = Probes issued - * 1 = Probes not issued. - * [ 4: 4] Disable Memroy Controller Target Start - * 0 = TgtStart packets are generated - * 1 = TgtStart packets are not generated. - * [ 5: 5] CPU1 Enable - * 0 = Second CPU disabled or not present - * 1 = Second CPU enabled. - * [ 6: 6] CPU Request PassPW - * 0 = CPU requests do not pass posted writes - * 1 = CPU requests pass posted writes. - * [ 7: 7] CPU read Respons PassPW - * 0 = CPU Responses do not pass posted writes - * 1 = CPU responses pass posted writes. - * [ 8: 8] Disable Probe Memory Cancel - * 0 = Probes may generate MemCancels - * 1 = Probes may not generate MemCancels - * [ 9: 9] Disable Remote Probe Memory Cancel. - * 0 = Probes hitting dirty blocks generate memory cancel packets - * 1 = Only probed caches on the same node as the memory controller - * generate cancel packets. - * [10:10] Disable Fill Probe - * 0 = Probes issued for cache fills - * 1 = Probes not issued for cache fills. - * [11:11] Response PassPw - * 0 = Downstream response PassPW based on original request - * 1 = Downstream response PassPW set to 1 - * [12:12] Change ISOC to Ordered - * 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization - * 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering. - * [14:13] Buffer Release Priority select - * 00 = 64 - * 01 = 16 - * 10 = 8 - * 11 = 2 - * [15:15] Limit Coherent HT Configuration Space Range - * 0 = No coherent HT configuration space restrictions - * 1 = Limit coherent HT configuration space based on node count - * [16:16] Local Interrupt Conversion Enable. - * 0 = ExtInt/NMI interrupts unaffected. - * 1 = ExtInt/NMI broadcast interrupts converted to LINT0/1 - * [17:17] APIC Extended Broadcast Enable. - * 0 = APIC broadcast is 0F - * 1 = APIC broadcast is FF - * [18:18] APIC Extended ID Enable - * 0 = APIC ID is 4 bits. - * 1 = APIC ID is 8 bits. - * [19:19] APIC Extended Spurious Vector Enable - * 0 = Lower 4 bits of spurious vector are read-only 1111 - * 1 = Lower 4 bits of spurious vecotr are writeable. - * [20:20] Sequence ID Source Node Enable - * 0 = Normal operation - * 1 = Keep SeqID on routed packets for debugging. - * [22:21] Downstream non-posted request limit - * 00 = No limit - * 01 = Limited to 1 - * 10 = Limited to 4 - * 11 = Limited to 8 - * [23:23] RESERVED - * [25:24] Medium-Priority Bypass Count - * - Maximum # of times a medium priority access can pass a low - * priority access before Medium-Priority mode is disabled for one access. - * [27:26] High-Priority Bypass Count - * - Maximum # of times a high prioirty access can pass a medium or low - * priority access before High-prioirty mode is disabled for one access. - * [28:28] Enable High Priority CPU Reads - * 0 = Cpu reads are medium prioirty - * 1 = Cpu reads are high prioirty - * [29:29] Disable Low Priority Writes - * 0 = Non-isochronous writes are low priority - * 1 = Non-isochronous writes are medium prioirty - * [30:30] Disable High Priority Isochronous writes - * 0 = Isochronous writes are high priority - * 1 = Isochronous writes are medium priority - * [31:31] Disable Medium Priority Isochronous writes - * 0 = Isochronous writes are medium are high - * 1 = With bit 30 set makes Isochrouns writes low priority. - */ - PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00840f, - /* HT Initialization Control Register - * F0:0x6C - * [ 0: 0] Routing Table Disable - * 0 = Packets are routed according to routing tables - * 1 = Packets are routed according to the default link field - * [ 1: 1] Request Disable (BSP should clear this) - * 0 = Request packets may be generated - * 1 = Request packets may not be generated. - * [ 3: 2] Default Link (Read-only) - * 00 = LDT0 - * 01 = LDT1 - * 10 = LDT2 - * 11 = CPU on same node - * [ 4: 4] Cold Reset - * - Scratch bit cleared by a cold reset - * [ 5: 5] BIOS Reset Detect - * - Scratch bit cleared by a cold reset - * [ 6: 6] INIT Detect - * - Scratch bit cleared by a warm or cold reset not by an INIT - * - */ - PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4), - /* LDTi Capabilities Registers - * F0:0x80 i = 0, - * F0:0xA0 i = 1, - * F0:0xC0 i = 2, - */ - /* LDTi Link Control Registrs - * F0:0x84 i = 0, - * F0:0xA4 i = 1, - * F0:0xC4 i = 2, - * [ 1: 1] CRC Flood Enable - * 0 = Do not generate sync packets on CRC error - * 1 = Generate sync packets on CRC error - * [ 2: 2] CRC Start Test (Read-Only) - * [ 3: 3] CRC Force Frame Error - * 0 = Do not generate bad CRC - * 1 = Generate bad CRC - * [ 4: 4] Link Failure - * 0 = No link failure detected - * 1 = Link failure detected - * [ 5: 5] Initialization Complete - * 0 = Initialization not complete - * 1 = Initialization complete - * [ 6: 6] Receiver off - * 0 = Recevier on - * 1 = Receiver off - * [ 7: 7] Transmitter Off - * 0 = Transmitter on - * 1 = Transmitter off - * [ 9: 8] CRC_Error - * 00 = No error - * [0] = 1 Error on byte lane 0 - * [1] = 1 Error on byte lane 1 - * [12:12] Isochrnous Enable (Read-Only) - * [13:13] HT Stop Tristate Enable - * 0 = Driven during an LDTSTOP_L - * 1 = Tristated during and LDTSTOP_L - * [14:14] Extended CTL Time - * 0 = CTL is asserted for 16 bit times during link initialization - * 1 = CTL is asserted for 50us during link initialization - * [18:16] Max Link Width In (Read-Only?) - * 000 = 8 bit link - * 001 = 16bit link - * [19:19] Doubleword Flow Control in (Read-Only) - * 0 = This link does not support doubleword flow control - * 1 = This link supports doubleword flow control - * [22:20] Max Link Width Out (Read-Only?) - * 000 = 8 bit link - * 001 = 16bit link - * [23:23] Doubleworld Flow Control out (Read-Only) - * 0 = This link does not support doubleword flow control - * 1 = This link supports doubleworkd flow control - * [26:24] Link Width In - * 000 = Use 8 bits - * 001 = Use 16 bits - * 010 = reserved - * 011 = Use 32 bits - * 100 = Use 2 bits - * 101 = Use 4 bits - * 110 = reserved - * 111 = Link physically not connected - * [27:27] Doubleword Flow Control In Enable - * 0 = Doubleword flow control disabled - * 1 = Doubleword flow control enabled (Not currently supported) - * [30:28] Link Width Out - * 000 = Use 8 bits - * 001 = Use 16 bits - * 010 = reserved - * 011 = Use 32 bits - * 100 = Use 2 bits - * 101 = Use 4 bits - * 110 = reserved - * 111 = Link physically not connected - * [31:31] Doubleworld Flow Control Out Enable - * 0 = Doubleworld flow control disabled - * 1 = Doubleword flow control enabled (Not currently supported) - */ - PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020, - /* LDTi Frequency/Revision Registers - * F0:0x88 i = 0, - * F0:0xA8 i = 1, - * F0:0xC8 i = 2, - * [ 4: 0] Minor Revision - * Contains the HT Minor revision - * [ 7: 5] Major Revision - * Contains the HT Major revision - * [11: 8] Link Frequency (Takes effect the next time the link is reconnected) - * 0000 = 200Mhz - * 0001 = reserved - * 0010 = 400Mhz - * 0011 = reserved - * 0100 = 600Mhz - * 0101 = 800Mhz - * 0110 = 1000Mhz - * 0111 = reserved - * 1000 = reserved - * 1001 = reserved - * 1010 = reserved - * 1011 = reserved - * 1100 = reserved - * 1101 = reserved - * 1110 = reserved - * 1111 = 100 Mhz - * [15:12] Error (Not currently Implemented) - * [31:16] Indicates the frequency capabilities of the link - * [16] = 1 encoding 0000 of freq supported - * [17] = 1 encoding 0001 of freq supported - * [18] = 1 encoding 0010 of freq supported - * [19] = 1 encoding 0011 of freq supported - * [20] = 1 encoding 0100 of freq supported - * [21] = 1 encoding 0101 of freq supported - * [22] = 1 encoding 0110 of freq supported - * [23] = 1 encoding 0111 of freq supported - * [24] = 1 encoding 1000 of freq supported - * [25] = 1 encoding 1001 of freq supported - * [26] = 1 encoding 1010 of freq supported - * [27] = 1 encoding 1011 of freq supported - * [28] = 1 encoding 1100 of freq supported - * [29] = 1 encoding 1101 of freq supported - * [30] = 1 encoding 1110 of freq supported - * [31] = 1 encoding 1111 of freq supported - */ - PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000200, - /* LDTi Feature Capability - * F0:0x8C i = 0, - * F0:0xAC i = 1, - * F0:0xCC i = 2, - */ - /* LDTi Buffer Count Registers - * F0:0x90 i = 0, - * F0:0xB0 i = 1, - * F0:0xD0 i = 2, - */ - /* LDTi Bus Number Registers - * F0:0x94 i = 0, - * F0:0xB4 i = 1, - * F0:0xD4 i = 2, - * For NonCoherent HT specifies the bus number downstream (behind the host bridge) - * [ 0: 7] Primary Bus Number - * [15: 8] Secondary Bus Number - * [23:15] Subordiante Bus Number - * [31:24] reserved - */ - PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000, - /* LDTi Type Registers - * F0:0x98 i = 0, - * F0:0xB8 i = 1, - * F0:0xD8 i = 2, - */ - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -#if MEMORY_1024MB - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000, -#endif -#if MEMORY_512MB - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000, -#endif - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003, -#if MEMORY_1024MB - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000, -#endif -#if MEMORY_512MB - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000, -#endif - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03, -#if MEMORY_1024MB - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003, -#endif -#if MEMORY_512MB - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003, -#endif - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, -#endif - }; - int i; - int max; - print_debug("setting up coherent ht domain....\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - unsigned long reg; -#if 1 - print_debug_hex32(register_values[i]); - print_debug(" <-"); - print_debug_hex32(register_values[i+2]); - print_debug("\n"); -#endif -#if 0 - reg = pci_read_config32(register_values[i]); - reg &= register_values[i+1]; - reg |= register_values[i+2] & ~register_values[i+1]; - pci_write_config32(register_values[i], reg); -#endif - } - print_debug("done.\n"); -} - -static void main(void) -{ - static const char msg[] = "hello world\n"; -#if 0 - write(STDOUT_FILENO, msg, sizeof(msg)); -#endif -#if 1 - setup_coherent_ht_domain(); -#endif - _exit(0); -} diff --git a/util/romcc/tests/linux_test3.c b/util/romcc/tests/linux_test3.c deleted file mode 100644 index 4c7a882f75..0000000000 --- a/util/romcc/tests/linux_test3.c +++ /dev/null @@ -1,28 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" -static void goto_test(void) -{ - int i; - print_debug("goto_test\n"); - - i = 0; - goto bottom; - { - top: - print_debug("i = "); - print_debug_hex8(i); - print_debug("\n"); - - i = i + 1; - } - bottom: - if (i < 10) { - goto top; - } -} - -static void main(void) -{ - goto_test(); - _exit(0); -} diff --git a/util/romcc/tests/linux_test4.c b/util/romcc/tests/linux_test4.c deleted file mode 100644 index 71f4d6541e..0000000000 --- a/util/romcc/tests/linux_test4.c +++ /dev/null @@ -1,46 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - -struct socket_desc { - short up; - short down; - short across; -}; - -static void main(void) -{ - static const struct socket_desc cpu_socketsA[] = { - { .up = 2, .down = -1, .across = 1 }, /* Node 0 */ - { .up = 3, .down = -1, .across = 0 }, /* Node 1 */ - { .up = -1, .down = 0, .across = 3 }, /* Node 2 */ - { .up = -1, .down = 1, .across = 2 } /* Node 3 */ - }; - static const struct socket_desc cpu_socketsB[4] = { - { 2, -1, 1 }, /* Node 0 */ - { 3, -1, 0 }, /* Node 1 */ - { -1, 0, 3 }, /* Node 2 */ - { -1, 1, 2 } /* Node 3 */ - }; - int i; - print_debug("cpu_socketA\n"); - for(i = 0; i < sizeof(cpu_socketsA)/sizeof(cpu_socketsA[0]); i++) { - print_debug(".up="); - print_debug_hex16(cpu_socketsA[i].up); - print_debug(" .down="); - print_debug_hex16(cpu_socketsA[i].down); - print_debug(" .across="); - print_debug_hex16(cpu_socketsA[i].across); - print_debug("\n"); - } - print_debug("\ncpu_socketB\n"); - for(i = 0; i < sizeof(cpu_socketsB)/sizeof(cpu_socketsB[0]); i++) { - print_debug(".up="); - print_debug_hex16(cpu_socketsB[i].up); - print_debug(" .down="); - print_debug_hex16(cpu_socketsB[i].down); - print_debug(" .across="); - print_debug_hex16(cpu_socketsB[i].across); - print_debug("\n"); - } - _exit(0); -} diff --git a/util/romcc/tests/linux_test5.c b/util/romcc/tests/linux_test5.c deleted file mode 100644 index e94d5d71e7..0000000000 --- a/util/romcc/tests/linux_test5.c +++ /dev/null @@ -1,358 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - -inline int log2(int value) -{ - /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 - * when the value presented to it is zero. - * Otherwise __builtin_bsr returns the zero based index of - * the highest bit set. - */ - return __builtin_bsr(value); -} - - -static int smbus_read_byte(unsigned device, unsigned address) -{ - static const unsigned char dimm[] = { -0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01, -0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40, -0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - -0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01, -0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40, -0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }; - return dimm[(device << 8) + address]; -} - -#define SMBUS_MEM_DEVICE_START 0x00 -#define SMBUS_MEM_DEVICE_END 0x01 -#define SMBUS_MEM_DEVICE_INC 1 - -/* Function 2 */ -#define DRAM_CONFIG_HIGH 0x94 -#define DCH_MEMCLK_SHIFT 20 -#define DCH_MEMCLK_MASK 7 -#define DCH_MEMCLK_100MHZ 0 -#define DCH_MEMCLK_133MHZ 2 -#define DCH_MEMCLK_166MHZ 5 -#define DCH_MEMCLK_200MHZ 7 - -/* Function 3 */ -#define NORTHBRIDGE_CAP 0xE8 -#define NBCAP_128Bit 0x0001 -#define NBCAP_MP 0x0002 -#define NBCAP_BIG_MP 0x0004 -#define NBCAP_ECC 0x0004 -#define NBCAP_CHIPKILL_ECC 0x0010 -#define NBCAP_MEMCLK_SHIFT 5 -#define NBCAP_MEMCLK_MASK 3 -#define NBCAP_MEMCLK_100MHZ 3 -#define NBCAP_MEMCLK_133MHZ 2 -#define NBCAP_MEMCLK_166MHZ 1 -#define NBCAP_MEMCLK_200MHZ 0 -#define NBCAP_MEMCTRL 0x0100 - -typedef unsigned char uint8_t; -typedef unsigned int uint32_t; - -static unsigned spd_to_dimm(unsigned device) -{ - return (device - SMBUS_MEM_DEVICE_START); -} - -static void disable_dimm(unsigned index) -{ - print_debug("disabling dimm"); - print_debug_hex8(index); - print_debug("\n"); -#if 0 - pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0); - pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+1)<<2), 0); -#endif -} - - -struct mem_param { - uint8_t cycle_time; - uint32_t dch_memclk; -}; - -static const struct mem_param *get_mem_param(unsigned min_cycle_time) -{ - static const struct mem_param speed[] = { - { - .cycle_time = 0xa0, - .dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT, - }, - { - .cycle_time = 0x75, - .dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT, - }, - { - .cycle_time = 0x60, - .dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT, - }, - { - .cycle_time = 0x50, - .dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT, - }, - { - .cycle_time = 0x00, - }, - }; - const struct mem_param *param; - for(param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } - return param; -} - -#if 1 -static void debug(int c) -{ - print_debug_char(c); - print_debug_char('\n'); -} -#endif -static const struct mem_param *spd_set_memclk(void) -{ - /* Compute the minimum cycle time for these dimms */ - const struct mem_param *param; - unsigned min_cycle_time, min_latency; - unsigned device; - uint32_t value; - - static const int latency_indices[] = { 26, 23, 9 }; - static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ - }; - - -#if 0 - value = pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP); -#else - value = 0x50; -#endif - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - min_latency = 2; - -#if 1 - print_debug("min_cycle_time: "); - print_debug_hex8(min_cycle_time); - print_debug(" min_latency: "); - print_debug_hex8(min_latency); - print_debug("\n"); -#endif - - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. - */ - for(device = SMBUS_MEM_DEVICE_START; - device <= SMBUS_MEM_DEVICE_END; - device += SMBUS_MEM_DEVICE_INC) - { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - - debug('A'); - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: - * bit 0 == CAS Latency = 1.0 - * bit 1 == CAS Latency = 1.5 - * bit 2 == CAS Latency = 2.0 - * bit 3 == CAS Latency = 2.5 - * bit 4 == CAS Latency = 3.0 - * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD - * bit 7 == TBD - */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = smbus_read_byte(device, 18); - if (latencies <= 0) continue; - - debug('B'); - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for(index = 0; index < 3; index++, latency++) { - int value; - debug('C'); - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { - continue; - } - debug('D'); - value = smbus_read_byte(device, latency_indices[index]); - if (value < 0) continue; - - debug('E'); - /* Only increase the latency if we decreas the clock */ - if ((value >= min_cycle_time) && (value < new_cycle_time)) { - new_cycle_time = value; - new_latency = latency; -#if 1 - print_debug("device: "); - print_debug_hex8(device); - print_debug(" new_cycle_time: "); - print_debug_hex8(new_cycle_time); - print_debug(" new_latency: "); - print_debug_hex8(new_latency); - print_debug("\n"); -#endif - } - debug('G'); - } - debug('H'); -#if 1 - print_debug("device: "); - print_debug_hex8(device); - print_debug(" new_cycle_time: "); - print_debug_hex8(new_cycle_time); - print_debug(" new_latency: "); - print_debug_hex8(new_latency); - print_debug("\n"); -#endif - if (new_latency > 4){ - continue; - } - debug('I'); - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } -#if 1 - print_debug("device: "); - print_debug_hex8(device); - print_debug(" min_cycle_time: "); - print_debug_hex8(min_cycle_time); - print_debug(" min_latency: "); - print_debug_hex8(min_latency); - print_debug("\n"); -#endif - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - for(device = SMBUS_MEM_DEVICE_START; - device <= SMBUS_MEM_DEVICE_END; - device += SMBUS_MEM_DEVICE_INC) - { - int latencies; - int latency; - int index; - int value; - int dimm; - latencies = smbus_read_byte(device, 18); - if (latencies <= 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for(index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { - continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; - } - - /* Read the min_cycle_time for this latency */ - value = smbus_read_byte(device, latency_indices[index]); - - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - disable_dimm(spd_to_dimm(device)); - } -#if 1 - print_debug("min_cycle_time: "); - print_debug_hex8(min_cycle_time); - print_debug(" min_latency: "); - print_debug_hex8(min_latency); - print_debug("\n"); -#endif - /* Now that I know the minimum cycle time lookup the memory parameters */ - param = get_mem_param(min_cycle_time); - -#if 0 - /* Update DRAM Config High with our selected memory speed */ - value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH); - value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT); - value |= param->dch_memclk; - pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH, value); - - static const unsigned latencies[] = { 1, 5, 2 }; - /* Update DRAM Timing Low wiht our selected cas latency */ - value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW); - value &= ~7; - value |= latencies[min_latency - 2]; - pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, value); -#endif - - return param; -} - -static void main(void) -{ - const struct mem_param *param; - param = spd_set_memclk(); - _exit(0); -} diff --git a/util/romcc/tests/linux_test6.c b/util/romcc/tests/linux_test6.c deleted file mode 100644 index 2ae6cd1c9a..0000000000 --- a/util/romcc/tests/linux_test6.c +++ /dev/null @@ -1,17 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - -static void main(void) -{ - static const int value[] = { 1, 0 }; - const char *str; - if (value[1]) { - print_debug("A\n"); - str = "Unbuffered\n"; - } else { - print_debug("B\n"); - str = "Registered\n"; - } - print_debug(str); - _exit(0); -} diff --git a/util/romcc/tests/linux_test7.c b/util/romcc/tests/linux_test7.c deleted file mode 100644 index 409b6cbb44..0000000000 --- a/util/romcc/tests/linux_test7.c +++ /dev/null @@ -1,35 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - - -static void main(void) -{ - static const int cpu[] = { 0, 1, 2, 3 }; - int i; - for(i = 0; i < sizeof(cpu)/sizeof(cpu[0]); i++) { - static const unsigned int register_values[] = { - 0x0000c144, 0x0000f8f8, 0x00000000, - 0x0000c14C, 0x0000f8f8, 0x00000001, - 0x0000c154, 0x0000f8f8, 0x00000002, - 0x0000c15C, 0x0000f8f8, 0x00000003, - 0x0000c164, 0x0000f8f8, 0x00000004, - 0x0000c16C, 0x0000f8f8, 0x00000005, - 0x0000c174, 0x0000f8f8, 0x00000006, - 0x0000c17C, 0x0000f8f8, 0x00000007, - }; - int j; - int max = sizeof(register_values)/sizeof(register_values[0]); - for(j = 0; j < max; j += 3) { - print_debug("val["); - print_debug_hex8(j); - print_debug("]: "); - print_debug_hex32(register_values[j]); - print_debug_char(' '); - print_debug_hex32(register_values[j+1]); - print_debug_char(' '); - print_debug_hex32(register_values[j+2]); - print_debug_char('\n'); - } - } - _exit(0); -} diff --git a/util/romcc/tests/linux_test8.c b/util/romcc/tests/linux_test8.c deleted file mode 100644 index dfd377635d..0000000000 --- a/util/romcc/tests/linux_test8.c +++ /dev/null @@ -1,39 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - -struct mem_param { - unsigned char cycle_time; - unsigned char divisor; - unsigned char tRC; - unsigned char tRFC; - unsigned dch_memclk; - unsigned short dch_tref4k, dch_tref8k; - unsigned char dtl_twr; - char name[8]; -}; - -static void test(void) -{ - static const struct mem_param param0 = { - .name = "166Mhz\n", - .cycle_time = 0x60, - .divisor = (6<<1), - .tRC = 0x3C, - .tRFC = 0x48, - .dch_memclk = 5 << 20, - .dch_tref4k = 0x02, - .dch_tref8k = 0x0A, - .dtl_twr = 3, - }; - int value; - unsigned clocks; - const struct mem_param *param; - param = ¶m0; - value = 0x48; - /* This used to generate 32bit loads instead of 8 bit loads */ - clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1); - print_debug("clocks: "); - print_debug_hex32(clocks); - print_debug("\n"); - _exit(0); -} diff --git a/util/romcc/tests/linux_test9.c b/util/romcc/tests/linux_test9.c deleted file mode 100644 index 2a900a55fc..0000000000 --- a/util/romcc/tests/linux_test9.c +++ /dev/null @@ -1,13 +0,0 @@ -#include "linux_syscall.h" -#include "linux_console.h" - -static void test(void) -{ - unsigned char i; - for(i = 127; i != 5; i++) { - print_debug("i: "); - print_debug_hex32((unsigned )i); - print_debug("\n"); - } - _exit(0); -} diff --git a/util/romcc/tests/linuxi386_syscall.h b/util/romcc/tests/linuxi386_syscall.h deleted file mode 100644 index 96a5936c3c..0000000000 --- a/util/romcc/tests/linuxi386_syscall.h +++ /dev/null @@ -1,299 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} - -static struct syscall_result syscall0(unsigned long nr) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr)); - return syscall_return(res); -} - -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - -static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2)); - return syscall_return(res); - -} - - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); - return syscall_return(res); - -} - -static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, unsigned long arg5) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), - "S" (arg4), "D" (arg5)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_fork 2 -#define NR_read 3 -#define NR_write 4 -#define NR_open 5 -#define NR_close 6 -#define NR_waitpid 7 -#define NR_creat 8 -#define NR_link 9 -#define NR_unlink 10 -#define NR_execve 11 -#define NR_chdir 12 -#define NR_time 13 -#define NR_mknod 14 -#define NR_chmod 15 -#define NR_lchown 16 -#define NR_break 17 -#define NR_oldstat 18 -#define NR_lseek 19 -#define NR_getpid 20 -#define NR_mount 21 -#define NR_umount 22 -#define NR_setuid 23 -#define NR_getuid 24 -#define NR_stime 25 -#define NR_ptrace 26 -#define NR_alarm 27 -#define NR_oldfstat 28 -#define NR_pause 29 -#define NR_utime 30 -#define NR_stty 31 -#define NR_gtty 32 -#define NR_access 33 -#define NR_nice 34 -#define NR_ftime 35 -#define NR_sync 36 -#define NR_kill 37 -#define NR_rename 38 -#define NR_mkdir 39 -#define NR_rmdir 40 -#define NR_dup 41 -#define NR_pipe 42 -#define NR_times 43 -#define NR_prof 44 -#define NR_brk 45 -#define NR_setgid 46 -#define NR_getgid 47 -#define NR_signal 48 -#define NR_geteuid 49 -#define NR_getegid 50 -#define NR_acct 51 -#define NR_umount2 52 -#define NR_lock 53 -#define NR_ioctl 54 -#define NR_fcntl 55 -#define NR_mpx 56 -#define NR_setpgid 57 -#define NR_ulimit 58 -#define NR_oldolduname 59 -#define NR_umask 60 -#define NR_chroot 61 -#define NR_ustat 62 -#define NR_dup2 63 -#define NR_getppid 64 -#define NR_getpgrp 65 -#define NR_setsid 66 -#define NR_sigaction 67 -#define NR_sgetmask 68 -#define NR_ssetmask 69 -#define NR_setreuid 70 -#define NR_setregid 71 -#define NR_sigsuspend 72 -#define NR_sigpending 73 -#define NR_sethostname 74 -#define NR_setrlimit 75 -#define NR_getrlimit 76 -#define NR_getrusage 77 -#define NR_gettimeofday 78 -#define NR_settimeofday 79 -#define NR_getgroups 80 -#define NR_setgroups 81 -#define NR_select 82 -#define NR_symlink 83 -#define NR_oldlstat 84 -#define NR_readlink 85 -#define NR_uselib 86 -#define NR_swapon 87 -#define NR_reboot 88 -#define NR_readdir 89 -#define NR_mmap 90 -#define NR_munmap 91 -#define NR_truncate 92 -#define NR_ftruncate 93 -#define NR_fchmod 94 -#define NR_fchown 95 -#define NR_getpriority 96 -#define NR_setpriority 97 -#define NR_profil 98 -#define NR_statfs 99 -#define NR_fstatfs 100 -#define NR_ioperm 101 -#define NR_socketcall 102 -#define NR_syslog 103 -#define NR_setitimer 104 -#define NR_getitimer 105 -#define NR_stat 106 -#define NR_lstat 107 -#define NR_fstat 108 -#define NR_olduname 109 -#define NR_iopl 110 -#define NR_vhangup 111 -#define NR_idle 112 -#define NR_vm86old 113 -#define NR_wait4 114 -#define NR_swapoff 115 -#define NR_sysinfo 116 -#define NR_ipc 117 -#define NR_fsync 118 -#define NR_sigreturn 119 -#define NR_clone 120 -#define NR_setdomainname 121 -#define NR_uname 122 -#define NR_modify_ldt 123 -#define NR_adjtimex 124 -#define NR_mprotect 125 -#define NR_sigprocmask 126 -#define NR_create_module 127 -#define NR_init_module 128 -#define NR_delete_module 129 -#define NR_get_kernel_syms 130 -#define NR_quotactl 131 -#define NR_getpgid 132 -#define NR_fchdir 133 -#define NR_bdflush 134 -#define NR_sysfs 135 -#define NR_personality 136 -#define NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define NR_setfsuid 138 -#define NR_setfsgid 139 -#define NR__llseek 140 -#define NR_getdents 141 -#define NR__newselect 142 -#define NR_flock 143 -#define NR_msync 144 -#define NR_readv 145 -#define NR_writev 146 -#define NR_getsid 147 -#define NR_fdatasync 148 -#define NR__sysctl 149 -#define NR_mlock 150 -#define NR_munlock 151 -#define NR_mlockall 152 -#define NR_munlockall 153 -#define NR_sched_setparam 154 -#define NR_sched_getparam 155 -#define NR_sched_setscheduler 156 -#define NR_sched_getscheduler 157 -#define NR_sched_yield 158 -#define NR_sched_get_priority_max 159 -#define NR_sched_get_priority_min 160 -#define NR_sched_rr_get_interval 161 -#define NR_nanosleep 162 -#define NR_mremap 163 -#define NR_setresuid 164 -#define NR_getresuid 165 -#define NR_vm86 166 -#define NR_query_module 167 -#define NR_poll 168 -#define NR_nfsservctl 169 -#define NR_setresgid 170 -#define NR_getresgid 171 -#define NR_prctl 172 -#define NR_rt_sigreturn 173 -#define NR_rt_sigaction 174 -#define NR_rt_sigprocmask 175 -#define NR_rt_sigpending 176 -#define NR_rt_sigtimedwait 177 -#define NR_rt_sigqueueinfo 178 -#define NR_rt_sigsuspend 179 -#define NR_pread 180 -#define NR_pwrite 181 -#define NR_chown 182 -#define NR_getcwd 183 -#define NR_capget 184 -#define NR_capset 185 -#define NR_sigaltstack 186 -#define NR_sendfile 187 -#define NR_getpmsg 188 /* some people actually want streams */ -#define NR_putpmsg 189 /* some people actually want streams */ -#define NR_vfork 190 - -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -typedef long ssize_t; -typedef unsigned long size_t; - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c deleted file mode 100644 index 564786b51c..0000000000 --- a/util/romcc/tests/raminit_test.c +++ /dev/null @@ -1,1292 +0,0 @@ -#define HAVE_STRING_SUPPORT 0 -#define HAVE_CAST_SUPPORT 1 -#define HAVE_STATIC_ARRAY_SUPPORT 1 -#define HAVE_POINTER_SUPPORT 1 -#define HAVE_MACRO_ARG_SUPPORT 0 - -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} - -void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} - -unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where) -{ - return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3); -} - -static unsigned char pcibios_read_config_byte( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inb(0xCFC + (where & 3)); -} - -static unsigned short pcibios_read_config_word( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inw(0xCFC + (where & 2)); -} - -static unsigned int pcibios_read_config_dword( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inl(0xCFC); -} - - -static void pcibios_write_config_byte( - unsigned char bus, unsigned devfn, unsigned where, unsigned char value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); -} - -static void pcibios_write_config_word( - unsigned char bus, unsigned devfn, unsigned where, unsigned short value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); -} - -static void pcibios_write_config_dword( - unsigned char bus, unsigned devfn, unsigned where, unsigned int value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outl(value, 0xCFC); -} - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - -void __console_tx_char(unsigned char byte) -{ - uart_tx_byte(byte); -} -void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_char(digit); -} -void __console_tx_hex8(unsigned char byte) -{ - __console_tx_nibble(byte >> 4); - __console_tx_nibble(byte & 0x0f); -} - -void __console_tx_hex32(unsigned char value) -{ - __console_tx_nibble((value >> 28) & 0x0f); - __console_tx_nibble((value >> 24) & 0x0f); - __console_tx_nibble((value >> 20) & 0x0f); - __console_tx_nibble((value >> 16) & 0x0f); - __console_tx_nibble((value >> 12) & 0x0f); - __console_tx_nibble((value >> 8) & 0x0f); - __console_tx_nibble((value >> 4) & 0x0f); - __console_tx_nibble(value & 0x0f); -} - -#if HAVE_STRING_SUPPORT -void __console_tx_string(char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_char(ch); - } -} -#else -void __console_tx_string(char *str) -{ -} -#endif - - -void print_emerg_char(unsigned char byte) { __console_tx_char(byte); } -void print_emerg_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_emerg_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_emerg(char *str) { __console_tx_string(str); } - -void print_alert_char(unsigned char byte) { __console_tx_char(byte); } -void print_alert_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_alert_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_alert(char *str) { __console_tx_string(str); } - -void print_crit_char(unsigned char byte) { __console_tx_char(byte); } -void print_crit_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_crit_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_crit(char *str) { __console_tx_string(str); } - -void print_err_char(unsigned char byte) { __console_tx_char(byte); } -void print_err_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_err_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_err(char *str) { __console_tx_string(str); } - -void print_warning_char(unsigned char byte) { __console_tx_char(byte); } -void print_warning_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_warning_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_warning(char *str) { __console_tx_string(str); } - -void print_notice_char(unsigned char byte) { __console_tx_char(byte); } -void print_notice_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_notice_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_notice(char *str) { __console_tx_string(str); } - -void print_info_char(unsigned char byte) { __console_tx_char(byte); } -void print_info_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_info_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_info(char *str) { __console_tx_string(str); } - -void print_debug_char(unsigned char byte) { __console_tx_char(byte); } -void print_debug_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_debug(char *str) { __console_tx_string(str); } - -void print_spew_char(unsigned char byte) { __console_tx_char(byte); } -void print_spew_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_spew_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_spew(char *str) { __console_tx_string(str); } - -#define PIIX4_DEVFN 0x90 -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - - -#define PM_BUS 0 -#define PM_DEVFN (PIIX4_DEVFN+3) - -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 - -void smbus_enable(void) -{ - /* iobase addr */ - pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x90, SMBUS_IO_BASE | 1); - /* smbus enable */ - pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0xd2, (0x4 << 1) | 1); - /* iospace enable */ - pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1); -} - -void smbus_setup(void) -{ - outb(0, SMBUS_IO_BASE + SMBHSTSTAT); -} - -static void smbus_wait_until_ready(void) -{ - while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - }while((byte &1) == 1); - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char host_status_register; - unsigned char byte; - int result; - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - - result = byte; - if (host_status_register != 0x02) { - result = -1; - } - return result; -} - -#define I440GX_BUS 0 -#define I440GX_DEVFN ((0x00 << 3) + 0) - -#define USE_ECC 0 - -#define CAS_LATENCY 3 - - /* CAS latency 2 */ -#if (CAS_LATENCY == 2) -#define CAS_NB 0x17 - /* - * 7 == 0111 - * 1 == 0001 - */ -#define CAS_MODE 0x2a - /* - * a == 1010 - * 2 == 0010 - */ -#endif - - /* CAS latency 3 */ -#if (CAS_LATENCY == 3) -#define CAS_NB 0x13 - /* - * 3 == 0011 - * 1 == 0001 - */ -#define CAS_MODE 0x3a - /* - * a == 1010 - * 3 == 0011 - */ -#endif - -#ifndef CAS_NB -#error "Nothing defined" -#endif - -/* Default values for config registers */ - -static void set_nbxcfg(void) -{ - /* NBXCFG 0x50 - 0x53 */ - /* f == 1111 - * 0 == 0000 - * 0 == 0000 - * 0 == 0000 - * 0 == 0000 - * 1 == 0001 - * 8 == 1000 - * c == 1100 - * SDRAM Row without ECC: - * row 0 == 1 No ECC - * row 1 == 1 No ECC - * row 2 == 1 No ECC - * row 3 == 1 No ECC - * row 4 == 1 No ECC - * row 5 == 1 No ECC - * row 6 == 1 No ECC - * row 7 == 1 No ECC - * Host Bus Fast Data Ready Enable == 0 Disabled - * IDSEL_REDIRECT == 0 (430TX compatibility disable?) - * WSC# Hanshake Disable == 0 enable (Use External IOAPIC) - * Host/DRAM Frequence == 00 100Mhz - * AGP to PCI Access Enable == 0 Disable - * PCI Agent to Aperture Access Disable == 0 Enable (Ignored) - * Aperture Access Global Enable == 0 Disable - * DRAM Data Integrity Mode == 11 (Error Checking/Correction) - * ECC Diagnostic Mode Enable == 0 Not Enabled - * MDA present == 0 Not Present - * USWC Write Post During During I/O Bridge Access Enable == 1 Enabled - * In Order Queue Depth (IQD) (RO) == ?? - */ - pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c); -} - -static void set_dramc(void) -{ - /* 0 == 0000 - * 8 == 1000 - * Not registered SDRAM - * refresh disabled - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, 0x8); -} - -static void set_pam(void) -{ - /* PAM - Programmable Attribute Map Registers */ - /* Ideally we want to enable all of these as DRAM and teach - * linux it is o.k. to use them... - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x59, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5a, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5b, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5d, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5e, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5f, 0x00); -} - -static void set_drb(void) -{ - /* DRB - DRAM Row Boundary Registers */ - /* Conservative setting 8MB of ram on first DIMM... */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x61, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x62, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x63, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x64, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x65, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x66, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67, 0x01); -} - -static void set_fdhc(void) -{ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x68, 0x00); -} -static void set_mbsc(void) -{ - /* MBSC - Memory Buffer Strength Control */ - /* 00c00003e820 - * [47:44] 0 == 0000 - * [43:40] 0 == 0000 - * [39:36] c == 1100 - * [35:32] 0 == 0000 - * [31:28] 0 == 0000 - * [27:24] 0 == 0000 - * [23:20] 0 == 0000 - * [19:16] 3 == 0011 - * [15:12] e == 1110 - * [11: 8] 8 == 1000 - * [ 7: 4] 2 == 0010 - * [ 3: 0] 0 == 0000 - * MAA[14:0]#, WEA#, SRASA#, SCASA# Buffer Strengths == 3x - * MAB[14,13,10,12:11,9:0]#, WEB#, SRASB#, SCASB# Buffer Strengths == 3x - * MD[63:0]# Buffer Strength Control 2 == 3x - * MD[63:0]# Buffer Strength Control 1 == 3x - * MECC[7:0] Buffer Strength Control 2 == 3x - * MECC[7:0] Buffer Strength Control 1 == 3x - * CSB7# Buffer Strength == 3x - * CSA7# Buffer Strength == 3x - * CSB6# Buffer Strength == 3x - * CSA6# Buffer Strength == 3x - * CSA5#/CSB5# Buffer Strength == 2x - * CSA4#/CSB4# Buffer Strength == 2x - * CSA3#/CSB3# Buffer Strength == 2x - * CSA2#/CSB2# Buffer Strength == 2x - * CSA1#/CSB1# Buffer Strength == 2x - * CSA0#/CSB0# Buffer Strength == 2x - * DQMA5 Buffer Strength == 2x - * DQMA1 Buffer Strength == 3x - * DQMB5 Buffer Strength == 2x - * DQMB1 Buffer Strength == 2x - * DQMA[7:6,4:2,0] Buffer Strength == 3x - * GCKE Buffer Strength == 1x - * FENA Buffer Strength == 3x - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x69, 0xB3); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6a, 0xee); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6b, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6c, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6d, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6e, 0x03); -} - -static void set_smram(void) -{ - /* 0x72 SMRAM */ - /* 1 == 0001 - * a == 1010 - * SMM Compatible base segment == 010 (Hardcoded value) - */ -} - -static void set_esramc(void) -{ - /* 0x73 ESMRAMC */ -} - -static void set_rps(void) -{ - /* RPS - Row Page Size Register */ - /* 0x0055 - * [15:12] 0 == 0000 - * [11: 8] 0 == 0000 - * [ 7: 4] 5 == 0101 - * [ 3: 0] 5 == 0101 - * DRB[0] == 4KB - * DRB[1] == 4KB - * DRB[2] == 4KB - * DRB[3] == 4KB - * DRB[4] == 2KB - * DRB[5] == 2KB - * DRB[6] == 2KB - * DRB[7] == 2KB - */ - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x74, 0x5555); -} - -static void set_sdramc(void) -{ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, CAS_NB); -} - -static void set_pgpol(void) -{ - /* PGPOL - Paging Policy Register */ - /* 0xff07 - * [15:12] f == 1111 - * [11: 8] f == 1111 - * [ 7: 4] 0 == 0000 - * [ 3: 0] 7 == 0111 - * row0 == 4banks - * row1 == 4banks - * row2 == 4banks - * row3 == 4banks - * row4 == 4banks - * row5 == 4banks - * row6 == 4banks - * row7 == 4banks - * Dram Idle Timer (DIT) == 32 clocks - */ - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x78, 0xff07); -} - -static void set_mbfs(void) -{ - /* MBFS - Memory Buffer Frequencey Select Register */ - /* 0xffff7f - * [23:20] f == 1111 - * [19:16] f == 1111 - * [15:12] f == 1111 - * [11: 8] f == 1111 - * [ 7: 4] 7 == 0111 - * [ 3: 0] f == 1111 - * MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled - * MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled - * MD[63:0] Control 2 == 100 Mhz Buffer Enable - * MD[63:0] Control 1 == 100 Mhz B - * MECC[7:0] Control 2 == 100 Mhz B - * - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xca, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcb, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcc, 0x7f); -} - -static void set_dwtc(void) -{ - /* DWTC - DRAM Write Thermal Throttle Control */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe0, 0xb4); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe1, 0xbe); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe2, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe3, 0xd7); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe4, 0x97); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe5, 0x3e); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe6, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe7, 0x80); -} - -static void set_drtc(void) -{ - /* DRTC - DRAM Read Thermal Throttle Control */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe8, 0x2c); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe9, 0xd3); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xea, 0xf7); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xeb, 0xcf); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xec, 0x9d); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xed, 0x3e); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xee, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xef, 0x00); -} - -static void set_pmcr(void) -{ - /* PMCR -- BIOS sets 0x90 into it. - * 0x10 is REQUIRED. - * we have never used it. So why did this ever work? - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90); - -} -void sdram_set_registers(void) -{ - set_nbxcfg(); - set_dramc(); - set_pam(); - set_drb(); - set_fdhc(); - set_mbsc(); - set_smram(); - set_esramc(); - set_rps(); - set_sdramc(); - set_pgpol(); - set_mbfs(); - set_dwtc(); - set_drtc(); - set_pmcr(); -} - -int log2(int value) -{ - /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 - * when the value presented to it is zero. - * Otherwise __builtin_bsr returns the zero based index of - * the highest bit set. - */ - return __builtin_bsr(value); -} - - -static void spd_set_drb(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRB registers which holds the ending memory address assigned - * to each DIMM. - */ - unsigned end_of_memory; - unsigned device; - unsigned drb_reg; - - end_of_memory = 0; /* in multiples of 8MiB */ - device = SMBUS_MEM_DEVICE_START; - drb_reg = 0x60; - while (device <= SMBUS_MEM_DEVICE_END) { - unsigned side1_bits, side2_bits; - int byte, byte2; - - side1_bits = side2_bits = -1; - - /* rows */ - byte = smbus_read_byte(device, 3); - if (byte >= 0) { - side1_bits += byte & 0xf; - - /* columns */ - byte = smbus_read_byte(device, 4); - side1_bits += byte & 0xf; - - /* banks */ - byte = smbus_read_byte(device, 17); - side1_bits += log2(byte); - - /* Get the moduel data width and convert it to a power of two */ - /* low byte */ - byte = smbus_read_byte(device, 6); - - /* high byte */ - byte2 = smbus_read_byte(device, 7); -#if HAVE_CAST_SUPPORT - side1_bits += log2((((unsigned long)byte2 << 8)| byte)); -#else - side1_bits += log2((byte2 << 8) | byte); -#endif - - /* now I have the ram size in bits as a power of two (less 1) */ - /* Make it mulitples of 8MB */ - side1_bits -= 25; - - /* side two */ - - /* number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte > 1) { - /* for now only handle the symmetrical case */ - side2_bits = side1_bits; - } - } - - /* Compute the end address for the DRB register */ - /* Only process dimms < 2GB (2^8 * 8MB) */ - if (side1_bits < 8) { - end_of_memory += (1 << side1_bits); - } -#if HAVE_STRING_SUPPORT - print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n"); -#endif - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg, end_of_memory); - - if (side2_bits < 8 ) { - end_of_memory += (1 << side2_bits); - } -#if HAVE_STRING_SUPPORT - print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n"); -#endif - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg +1, end_of_memory); - - drb_reg += 2; - device += SMBUS_MEM_DEVICE_INC; - } -} - -void sdram_no_memory(void) -{ -#if HAVE_STRING_SUPPORT - print_err("No memory!!\n"); -#endif - while(1) ; -} - -static void spd_set_dramc(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRAMC register, which records if ram is registered or not, - * and controls the refresh rate. - * The refresh rate is not set here, as memory refresh - * cannot be enbaled until after memory is initialized. - * see spd_enable_refresh. - */ - /* auto detect if ram is registered or not. */ - /* The DRAMC register also contorls the refresh rate but we can't - * set that here because we must leave refresh disabled. - * see: spd_enable_refresh - */ - /* Find the first dimm and assume the rest are the same */ - /* FIXME Check for illegal/unsupported ram configurations and abort */ - unsigned device; - int byte; - unsigned dramc; - byte = -1; - device = SMBUS_MEM_DEVICE_START; - - while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) { - byte = smbus_read_byte(device, 21); - device += SMBUS_MEM_DEVICE_INC; - } - if (byte < 0) { - /* We couldn't find anything we must have no memory */ - sdram_no_memory(); - } - dramc = 0x8; - if ((byte & 0x12) != 0) { - /* this is a registered part. - * observation: for register parts, BIOS zeros (!) - * registers CA-CC. This has an undocumented meaning. - */ - /* But it does make sense the oppisite of registered - * sdram is buffered and 0xca - 0xcc control the buffers. - * Clearing them aparently disables them. - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xca, 0); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcb, 0); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcc, 0); - dramc = 0x10; - } - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, dramc); -} - -static void spd_enable_refresh(void) -{ - /* - * Effects: Uses serial presence detect to set the - * refresh rate in the DRAMC register. - * see spd_set_dramc for the other values. - * FIXME: Check for illegal/unsupported ram configurations and abort - */ -#if HAVE_STATIC_ARRAY_SUPPORT - static const unsigned char refresh_rates[] = { - 0x01, /* Normal 15.625 us -> 15.6 us */ - 0x05, /* Reduced(.25X) 3.9 us -> 7.8 us */ - 0x05, /* Reduced(.5X) 7.8 us -> 7.8 us */ - 0x02, /* Extended(2x) 31.3 us -> 31.2 us */ - 0x03, /* Extended(4x) 62.5 us -> 62.4 us */ - 0x04, /* Extended(8x) 125 us -> 124.8 us */ - }; -#endif - /* Find the first dimm and assume the rest are the same */ - int status; - int byte; - unsigned device; - unsigned refresh_rate; - byte = -1; - status = -1; - device = SMBUS_MEM_DEVICE_START; - while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) { - byte = smbus_read_byte(device, 12); - device += SMBUS_MEM_DEVICE_INC; - } - if (byte < 0) { - /* We couldn't find anything we must have no memory */ - sdram_no_memory(); - } - byte &= 0x7f; - /* Default refresh rate be conservative */ - refresh_rate = 5; - /* see if the ram refresh is a supported one */ - if (byte < 6) { -#if HAVE_STATIC_ARRAY_SUPPORT - refresh_rate = refresh_rates[byte]; -#endif - } - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); - byte &= 0xf8; - byte |= refresh_rate; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, byte); -} - -static void spd_set_sdramc(void) -{ - return; -} - -static void spd_set_rps(void) -{ - /* - * Effects: Uses serial presence detect to set the row size - * on a given DIMM - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - /* The RPS register holds the size of a ``page'' of DRAM on each DIMM */ - unsigned page_sizes; - unsigned index; - unsigned device; - unsigned char dramc; - /* default all page sizes to 2KB */ - page_sizes = 0; - index = 0; - device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; index += 4, device += SMBUS_MEM_DEVICE_INC) { - unsigned int status; - unsigned int byte; - int page_size; - - byte = smbus_read_byte(device, 3); - if (byte < 0) continue; - - /* I now have the row page size as a power of 2 */ - page_size = byte & 0xf; - /* make it in multiples of 2Kb */ - page_size -= 11; - - if (page_size <= 0) continue; - - /* FIXME: do something with page sizes greather than 8KB!! */ - page_sizes |= (page_size << index); - - /* side two */ - byte = smbus_read_byte(device, 5); - if (byte <= 1) continue; - - /* For now only handle the symmetrical case */ - page_sizes |= (page_size << (index +2)); - } - /* next block is for Ron's attempt to get registered to work. */ - /* we have just verified that we have to have this code. It appears that - * the registered SDRAMs do indeed set the RPS wrong. sheesh. - */ - /* at this point, page_sizes holds the RPS for all ram. - * we have verified that for registered DRAM the values are - * 1/2 the size they should be. So we test for registered - * and then double the sizes if needed. - */ - - dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); - if (dramc & 0x10) { - /* registered */ - - /* BIOS makes weird page size for registered! */ - /* what we have found is you need to set the EVEN banks to - * twice the size. Fortunately there is a very easy way to - * do this. First, read the WORD value of register 0x74. - */ - page_sizes += 0x1111; - } - - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x74, page_sizes); -} - -static void spd_set_pgpol(void) -{ - /* - * Effects: Uses serial presence detect to set the number of banks - * on a given DIMM - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - /* The PGPOL register stores the number of logical banks per DIMM, - * and number of clocks the DRAM controller waits in the idle - * state. - */ - unsigned device; - unsigned bank_sizes; - unsigned bank; - unsigned reg; - /* default all bank counts 2 */ - bank_sizes = 0; - bank = 0; - device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; - bank += 2, device += SMBUS_MEM_DEVICE_INC) { - int byte; - - /* logical banks */ - byte = smbus_read_byte(device, 17); - if (byte < 0) continue; - if (byte < 4) continue; - bank_sizes |= (1 << bank); - - /* side 2 */ - /* Number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte <= 1) continue; - /* for now only handle the symmetrical case */ - bank_sizes |= (1 << (bank +1)); - } - reg = bank_sizes << 8; - reg |= 0x7; /* 32 clocks idle time */ - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x78, reg); -} - -static void spd_set_nbxcfg(void) -{ - /* - * Effects: Uses serial presence detect to set the - * ECC support flags in the NBXCFG register - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - unsigned reg; - unsigned index; - unsigned device; - - /* Say all dimms have no ECC support */ - reg = 0xff; - index = 0; - - device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) { - int byte; - - byte = smbus_read_byte(device, 11); - if (byte < 0) continue; -#if !USE_ECC - byte = 0; /* Disable ECC */ -#endif - /* 0 == None, 1 == Parity, 2 == ECC */ - if (byte != 2) continue; - reg ^= (1 << index); - - /* side two */ - /* number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte <= 1) continue; - /* There is only the symmetrical case */ - reg ^= (1 << (index +1)); - } - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x53, reg); - /* Now see if reg is 0xff. If it is we are done. If not, - * we need to set 0x18 into register 0x50.l - * we will do this in two steps, first or in 0x80 to 0x50.b, - * then or in 0x1 to 0x51.b - */ -#if HAVE_STRING_SUPPORT - print_debug("spd_set_nbxcfg reg="); print_debug_hex8(reg); print_debug("\n"); -#endif - if (reg != 0xff) { - unsigned char byte; - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x50); - byte |= 0x80; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x50, byte); - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x51); - byte |= 1; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x51, byte); - /* try this. - * We should be setting bit 2 in register 76 and we're not - * technically we should see if CL=2 for the ram, - * but registered is so screwed up that it's kind of a lost - * cause. - */ - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); - byte |= 4; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, byte); -#if HAVE_STRING_SUPPORT - print_debug("spd_set_nbxcfg 0x76.b="); print_debug_hex8(byte); print_debug("\n"); -#endif - } -} - -void sdram_set_spd_registers(void) -{ - spd_set_drb(); - spd_set_dramc(); - spd_set_rps(); - spd_set_sdramc(); - spd_set_pgpol(); - spd_set_nbxcfg(); -} - -void sdram_first_normal_reference(void) -{ - return; -} - -void sdram_special_finishup(void) -{ - return; -} - -static void set_ram_command(unsigned command) -{ - unsigned char byte; - command &= 0x7; - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); - byte &= 0x1f; - byte |= (command << 5); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, byte); -#if HAVE_STRING_SUPPORT - print_debug("set_ram_command 0x76.b="); print_debug_hex8(byte); print_debug("\n"); -#endif -} - -#define RAM_COMMAND_NONE 0x0 -#define RAM_COMMAND_NOOP 0x1 -#define RAM_COMMAND_PRECHARGE 0x2 -#define RAM_COMMAND_MRS 0x3 -#define RAM_COMMAND_CBR 0x4 - -void sdram_set_command_none(void) -{ - set_ram_command(RAM_COMMAND_NONE); -} -void sdram_set_command_noop(void) -{ - set_ram_command(RAM_COMMAND_NOOP); -} -void sdram_set_command_precharge(void) -{ - set_ram_command(RAM_COMMAND_PRECHARGE); -} - -static unsigned long dimm_base(int n) -{ - unsigned char byte; - unsigned long result; - if (n == 0) { - return 0; - } - - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60 + (n - 1)); - result = byte; - result <<= 23; - return result; -} - -static void dimms_read(unsigned long offset) -{ - int i; - for(i = 0; i < 8; i++) { - unsigned long dummy; - unsigned long addr; - unsigned long next_base; - - next_base = dimm_base(i +1); - addr = dimm_base(i); - if (addr == next_base) { - continue; - } - addr += offset; -#if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr); - print_debug("\n"); -#endif -#if HAVE_POINTER_SUPPORT -#if HAVE_MACRO_ARG_SUPPORT - dummy = RAM(unsigned long, addr); -#else - dummy = *((volatile unsigned long *)(addr)); -#endif -#endif -#if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr ^ 0xddf8); - print_debug("\n"); -#endif -#if HAVE_POINTER_SUPPORT -#if HAVE_MACRO_ARG_SUPPORT - dummy = RAM(unsigned long, addr ^ 0xdff8); -#else - dummy = *((volatile unsigned long *)(addr ^ 0xdff8)); -#endif -#endif -#if HAVE_STRING_SUPPORT - print_debug("Read "); - print_debug_hex32(addr); - print_debug_hex32(addr ^ 0xddf8); - print_debug("\n"); -#endif - } -} - -void sdram_set_command_cbr(void) -{ - set_ram_command(RAM_COMMAND_CBR); -} - -void sdram_assert_command(void) -{ - dimms_read(0x400); -} - -void sdram_set_mode_register(void) -{ - unsigned char byte; - unsigned cas_mode; - set_ram_command(RAM_COMMAND_MRS); - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); - cas_mode = byte & 0x4; - cas_mode ^= 4; - cas_mode <<= 2; - cas_mode |= 0x2a; - cas_mode <<= 3; - dimms_read(cas_mode); -} - -void sdram_enable_refresh(void) -{ - spd_enable_refresh(); -} - - -unsigned long sdram_get_ecc_size_bytes(void) -{ - unsigned char byte; - unsigned long size; - /* FIXME handle the no ram case. */ - /* Read the RAM SIZE */ - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67); - /* Convert it to bytes */ - size = byte; - size <<= 23; -#if !USE_ECC - size = 0; -#endif - return size; -} - -/* Dummy udelay code acting as a place holder... */ -void udelay(int count) -{ - int i; - i = 5; -} - -void sdram_enable(void) -{ -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 1\n"); -#endif - - /* noop command */ - sdram_set_command_noop(); - udelay(200); - sdram_assert_command(); - - /* Precharge all */ - sdram_set_command_precharge(); - sdram_assert_command(); - - /* wait until the all banks idle state... */ -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 2\n"); -#endif - - /* Now we need 8 AUTO REFRESH / CBR cycles to be performed */ - - sdram_set_command_cbr(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 3\n"); -#endif - - /* mode register set */ - sdram_set_mode_register(); - /* MAx[14:0] lines, - * MAx[2:0 ] 010 == burst mode of 4 - * MAx[3:3 ] 1 == interleave wrap type - * MAx[4:4 ] == CAS# latency bit - * MAx[6:5 ] == 01 - * MAx[12:7] == 0 - */ - -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 4\n"); -#endif - - /* normal operation */ - sdram_set_command_none(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 5\n"); -#endif -} - -/* Setup SDRAM */ -void sdram_initialize(void) -{ -#if HAVE_STRING_SUPPORT - print_debug("Ram1\n"); -#endif - /* Set the registers we can set once to reasonable values */ - sdram_set_registers(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram2\n"); -#endif - /* Now setup those things we can auto detect */ - sdram_set_spd_registers(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram3\n"); -#endif - /* Now that everything is setup enable the SDRAM. - * Some chipsets do the work for use while on others - * we need to it by hand. - */ - sdram_enable(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram4\n"); -#endif - sdram_first_normal_reference(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram5\n"); -#endif - sdram_enable_refresh(); - sdram_special_finishup(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram6\n"); -#endif -} diff --git a/util/romcc/tests/raminit_test1.c b/util/romcc/tests/raminit_test1.c deleted file mode 100644 index 564786b51c..0000000000 --- a/util/romcc/tests/raminit_test1.c +++ /dev/null @@ -1,1292 +0,0 @@ -#define HAVE_STRING_SUPPORT 0 -#define HAVE_CAST_SUPPORT 1 -#define HAVE_STATIC_ARRAY_SUPPORT 1 -#define HAVE_POINTER_SUPPORT 1 -#define HAVE_MACRO_ARG_SUPPORT 0 - -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} - -void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} - -unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where) -{ - return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3); -} - -static unsigned char pcibios_read_config_byte( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inb(0xCFC + (where & 3)); -} - -static unsigned short pcibios_read_config_word( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inw(0xCFC + (where & 2)); -} - -static unsigned int pcibios_read_config_dword( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inl(0xCFC); -} - - -static void pcibios_write_config_byte( - unsigned char bus, unsigned devfn, unsigned where, unsigned char value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); -} - -static void pcibios_write_config_word( - unsigned char bus, unsigned devfn, unsigned where, unsigned short value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); -} - -static void pcibios_write_config_dword( - unsigned char bus, unsigned devfn, unsigned where, unsigned int value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outl(value, 0xCFC); -} - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - -void __console_tx_char(unsigned char byte) -{ - uart_tx_byte(byte); -} -void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_char(digit); -} -void __console_tx_hex8(unsigned char byte) -{ - __console_tx_nibble(byte >> 4); - __console_tx_nibble(byte & 0x0f); -} - -void __console_tx_hex32(unsigned char value) -{ - __console_tx_nibble((value >> 28) & 0x0f); - __console_tx_nibble((value >> 24) & 0x0f); - __console_tx_nibble((value >> 20) & 0x0f); - __console_tx_nibble((value >> 16) & 0x0f); - __console_tx_nibble((value >> 12) & 0x0f); - __console_tx_nibble((value >> 8) & 0x0f); - __console_tx_nibble((value >> 4) & 0x0f); - __console_tx_nibble(value & 0x0f); -} - -#if HAVE_STRING_SUPPORT -void __console_tx_string(char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_char(ch); - } -} -#else -void __console_tx_string(char *str) -{ -} -#endif - - -void print_emerg_char(unsigned char byte) { __console_tx_char(byte); } -void print_emerg_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_emerg_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_emerg(char *str) { __console_tx_string(str); } - -void print_alert_char(unsigned char byte) { __console_tx_char(byte); } -void print_alert_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_alert_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_alert(char *str) { __console_tx_string(str); } - -void print_crit_char(unsigned char byte) { __console_tx_char(byte); } -void print_crit_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_crit_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_crit(char *str) { __console_tx_string(str); } - -void print_err_char(unsigned char byte) { __console_tx_char(byte); } -void print_err_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_err_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_err(char *str) { __console_tx_string(str); } - -void print_warning_char(unsigned char byte) { __console_tx_char(byte); } -void print_warning_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_warning_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_warning(char *str) { __console_tx_string(str); } - -void print_notice_char(unsigned char byte) { __console_tx_char(byte); } -void print_notice_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_notice_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_notice(char *str) { __console_tx_string(str); } - -void print_info_char(unsigned char byte) { __console_tx_char(byte); } -void print_info_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_info_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_info(char *str) { __console_tx_string(str); } - -void print_debug_char(unsigned char byte) { __console_tx_char(byte); } -void print_debug_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_debug(char *str) { __console_tx_string(str); } - -void print_spew_char(unsigned char byte) { __console_tx_char(byte); } -void print_spew_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_spew_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_spew(char *str) { __console_tx_string(str); } - -#define PIIX4_DEVFN 0x90 -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - - -#define PM_BUS 0 -#define PM_DEVFN (PIIX4_DEVFN+3) - -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 - -void smbus_enable(void) -{ - /* iobase addr */ - pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x90, SMBUS_IO_BASE | 1); - /* smbus enable */ - pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0xd2, (0x4 << 1) | 1); - /* iospace enable */ - pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1); -} - -void smbus_setup(void) -{ - outb(0, SMBUS_IO_BASE + SMBHSTSTAT); -} - -static void smbus_wait_until_ready(void) -{ - while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - }while((byte &1) == 1); - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char host_status_register; - unsigned char byte; - int result; - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - - result = byte; - if (host_status_register != 0x02) { - result = -1; - } - return result; -} - -#define I440GX_BUS 0 -#define I440GX_DEVFN ((0x00 << 3) + 0) - -#define USE_ECC 0 - -#define CAS_LATENCY 3 - - /* CAS latency 2 */ -#if (CAS_LATENCY == 2) -#define CAS_NB 0x17 - /* - * 7 == 0111 - * 1 == 0001 - */ -#define CAS_MODE 0x2a - /* - * a == 1010 - * 2 == 0010 - */ -#endif - - /* CAS latency 3 */ -#if (CAS_LATENCY == 3) -#define CAS_NB 0x13 - /* - * 3 == 0011 - * 1 == 0001 - */ -#define CAS_MODE 0x3a - /* - * a == 1010 - * 3 == 0011 - */ -#endif - -#ifndef CAS_NB -#error "Nothing defined" -#endif - -/* Default values for config registers */ - -static void set_nbxcfg(void) -{ - /* NBXCFG 0x50 - 0x53 */ - /* f == 1111 - * 0 == 0000 - * 0 == 0000 - * 0 == 0000 - * 0 == 0000 - * 1 == 0001 - * 8 == 1000 - * c == 1100 - * SDRAM Row without ECC: - * row 0 == 1 No ECC - * row 1 == 1 No ECC - * row 2 == 1 No ECC - * row 3 == 1 No ECC - * row 4 == 1 No ECC - * row 5 == 1 No ECC - * row 6 == 1 No ECC - * row 7 == 1 No ECC - * Host Bus Fast Data Ready Enable == 0 Disabled - * IDSEL_REDIRECT == 0 (430TX compatibility disable?) - * WSC# Hanshake Disable == 0 enable (Use External IOAPIC) - * Host/DRAM Frequence == 00 100Mhz - * AGP to PCI Access Enable == 0 Disable - * PCI Agent to Aperture Access Disable == 0 Enable (Ignored) - * Aperture Access Global Enable == 0 Disable - * DRAM Data Integrity Mode == 11 (Error Checking/Correction) - * ECC Diagnostic Mode Enable == 0 Not Enabled - * MDA present == 0 Not Present - * USWC Write Post During During I/O Bridge Access Enable == 1 Enabled - * In Order Queue Depth (IQD) (RO) == ?? - */ - pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c); -} - -static void set_dramc(void) -{ - /* 0 == 0000 - * 8 == 1000 - * Not registered SDRAM - * refresh disabled - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, 0x8); -} - -static void set_pam(void) -{ - /* PAM - Programmable Attribute Map Registers */ - /* Ideally we want to enable all of these as DRAM and teach - * linux it is o.k. to use them... - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x59, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5a, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5b, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5d, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5e, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5f, 0x00); -} - -static void set_drb(void) -{ - /* DRB - DRAM Row Boundary Registers */ - /* Conservative setting 8MB of ram on first DIMM... */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x61, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x62, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x63, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x64, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x65, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x66, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67, 0x01); -} - -static void set_fdhc(void) -{ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x68, 0x00); -} -static void set_mbsc(void) -{ - /* MBSC - Memory Buffer Strength Control */ - /* 00c00003e820 - * [47:44] 0 == 0000 - * [43:40] 0 == 0000 - * [39:36] c == 1100 - * [35:32] 0 == 0000 - * [31:28] 0 == 0000 - * [27:24] 0 == 0000 - * [23:20] 0 == 0000 - * [19:16] 3 == 0011 - * [15:12] e == 1110 - * [11: 8] 8 == 1000 - * [ 7: 4] 2 == 0010 - * [ 3: 0] 0 == 0000 - * MAA[14:0]#, WEA#, SRASA#, SCASA# Buffer Strengths == 3x - * MAB[14,13,10,12:11,9:0]#, WEB#, SRASB#, SCASB# Buffer Strengths == 3x - * MD[63:0]# Buffer Strength Control 2 == 3x - * MD[63:0]# Buffer Strength Control 1 == 3x - * MECC[7:0] Buffer Strength Control 2 == 3x - * MECC[7:0] Buffer Strength Control 1 == 3x - * CSB7# Buffer Strength == 3x - * CSA7# Buffer Strength == 3x - * CSB6# Buffer Strength == 3x - * CSA6# Buffer Strength == 3x - * CSA5#/CSB5# Buffer Strength == 2x - * CSA4#/CSB4# Buffer Strength == 2x - * CSA3#/CSB3# Buffer Strength == 2x - * CSA2#/CSB2# Buffer Strength == 2x - * CSA1#/CSB1# Buffer Strength == 2x - * CSA0#/CSB0# Buffer Strength == 2x - * DQMA5 Buffer Strength == 2x - * DQMA1 Buffer Strength == 3x - * DQMB5 Buffer Strength == 2x - * DQMB1 Buffer Strength == 2x - * DQMA[7:6,4:2,0] Buffer Strength == 3x - * GCKE Buffer Strength == 1x - * FENA Buffer Strength == 3x - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x69, 0xB3); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6a, 0xee); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6b, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6c, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6d, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6e, 0x03); -} - -static void set_smram(void) -{ - /* 0x72 SMRAM */ - /* 1 == 0001 - * a == 1010 - * SMM Compatible base segment == 010 (Hardcoded value) - */ -} - -static void set_esramc(void) -{ - /* 0x73 ESMRAMC */ -} - -static void set_rps(void) -{ - /* RPS - Row Page Size Register */ - /* 0x0055 - * [15:12] 0 == 0000 - * [11: 8] 0 == 0000 - * [ 7: 4] 5 == 0101 - * [ 3: 0] 5 == 0101 - * DRB[0] == 4KB - * DRB[1] == 4KB - * DRB[2] == 4KB - * DRB[3] == 4KB - * DRB[4] == 2KB - * DRB[5] == 2KB - * DRB[6] == 2KB - * DRB[7] == 2KB - */ - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x74, 0x5555); -} - -static void set_sdramc(void) -{ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, CAS_NB); -} - -static void set_pgpol(void) -{ - /* PGPOL - Paging Policy Register */ - /* 0xff07 - * [15:12] f == 1111 - * [11: 8] f == 1111 - * [ 7: 4] 0 == 0000 - * [ 3: 0] 7 == 0111 - * row0 == 4banks - * row1 == 4banks - * row2 == 4banks - * row3 == 4banks - * row4 == 4banks - * row5 == 4banks - * row6 == 4banks - * row7 == 4banks - * Dram Idle Timer (DIT) == 32 clocks - */ - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x78, 0xff07); -} - -static void set_mbfs(void) -{ - /* MBFS - Memory Buffer Frequencey Select Register */ - /* 0xffff7f - * [23:20] f == 1111 - * [19:16] f == 1111 - * [15:12] f == 1111 - * [11: 8] f == 1111 - * [ 7: 4] 7 == 0111 - * [ 3: 0] f == 1111 - * MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled - * MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled - * MD[63:0] Control 2 == 100 Mhz Buffer Enable - * MD[63:0] Control 1 == 100 Mhz B - * MECC[7:0] Control 2 == 100 Mhz B - * - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xca, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcb, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcc, 0x7f); -} - -static void set_dwtc(void) -{ - /* DWTC - DRAM Write Thermal Throttle Control */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe0, 0xb4); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe1, 0xbe); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe2, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe3, 0xd7); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe4, 0x97); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe5, 0x3e); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe6, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe7, 0x80); -} - -static void set_drtc(void) -{ - /* DRTC - DRAM Read Thermal Throttle Control */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe8, 0x2c); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe9, 0xd3); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xea, 0xf7); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xeb, 0xcf); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xec, 0x9d); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xed, 0x3e); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xee, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xef, 0x00); -} - -static void set_pmcr(void) -{ - /* PMCR -- BIOS sets 0x90 into it. - * 0x10 is REQUIRED. - * we have never used it. So why did this ever work? - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90); - -} -void sdram_set_registers(void) -{ - set_nbxcfg(); - set_dramc(); - set_pam(); - set_drb(); - set_fdhc(); - set_mbsc(); - set_smram(); - set_esramc(); - set_rps(); - set_sdramc(); - set_pgpol(); - set_mbfs(); - set_dwtc(); - set_drtc(); - set_pmcr(); -} - -int log2(int value) -{ - /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 - * when the value presented to it is zero. - * Otherwise __builtin_bsr returns the zero based index of - * the highest bit set. - */ - return __builtin_bsr(value); -} - - -static void spd_set_drb(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRB registers which holds the ending memory address assigned - * to each DIMM. - */ - unsigned end_of_memory; - unsigned device; - unsigned drb_reg; - - end_of_memory = 0; /* in multiples of 8MiB */ - device = SMBUS_MEM_DEVICE_START; - drb_reg = 0x60; - while (device <= SMBUS_MEM_DEVICE_END) { - unsigned side1_bits, side2_bits; - int byte, byte2; - - side1_bits = side2_bits = -1; - - /* rows */ - byte = smbus_read_byte(device, 3); - if (byte >= 0) { - side1_bits += byte & 0xf; - - /* columns */ - byte = smbus_read_byte(device, 4); - side1_bits += byte & 0xf; - - /* banks */ - byte = smbus_read_byte(device, 17); - side1_bits += log2(byte); - - /* Get the moduel data width and convert it to a power of two */ - /* low byte */ - byte = smbus_read_byte(device, 6); - - /* high byte */ - byte2 = smbus_read_byte(device, 7); -#if HAVE_CAST_SUPPORT - side1_bits += log2((((unsigned long)byte2 << 8)| byte)); -#else - side1_bits += log2((byte2 << 8) | byte); -#endif - - /* now I have the ram size in bits as a power of two (less 1) */ - /* Make it mulitples of 8MB */ - side1_bits -= 25; - - /* side two */ - - /* number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte > 1) { - /* for now only handle the symmetrical case */ - side2_bits = side1_bits; - } - } - - /* Compute the end address for the DRB register */ - /* Only process dimms < 2GB (2^8 * 8MB) */ - if (side1_bits < 8) { - end_of_memory += (1 << side1_bits); - } -#if HAVE_STRING_SUPPORT - print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n"); -#endif - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg, end_of_memory); - - if (side2_bits < 8 ) { - end_of_memory += (1 << side2_bits); - } -#if HAVE_STRING_SUPPORT - print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n"); -#endif - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg +1, end_of_memory); - - drb_reg += 2; - device += SMBUS_MEM_DEVICE_INC; - } -} - -void sdram_no_memory(void) -{ -#if HAVE_STRING_SUPPORT - print_err("No memory!!\n"); -#endif - while(1) ; -} - -static void spd_set_dramc(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRAMC register, which records if ram is registered or not, - * and controls the refresh rate. - * The refresh rate is not set here, as memory refresh - * cannot be enbaled until after memory is initialized. - * see spd_enable_refresh. - */ - /* auto detect if ram is registered or not. */ - /* The DRAMC register also contorls the refresh rate but we can't - * set that here because we must leave refresh disabled. - * see: spd_enable_refresh - */ - /* Find the first dimm and assume the rest are the same */ - /* FIXME Check for illegal/unsupported ram configurations and abort */ - unsigned device; - int byte; - unsigned dramc; - byte = -1; - device = SMBUS_MEM_DEVICE_START; - - while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) { - byte = smbus_read_byte(device, 21); - device += SMBUS_MEM_DEVICE_INC; - } - if (byte < 0) { - /* We couldn't find anything we must have no memory */ - sdram_no_memory(); - } - dramc = 0x8; - if ((byte & 0x12) != 0) { - /* this is a registered part. - * observation: for register parts, BIOS zeros (!) - * registers CA-CC. This has an undocumented meaning. - */ - /* But it does make sense the oppisite of registered - * sdram is buffered and 0xca - 0xcc control the buffers. - * Clearing them aparently disables them. - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xca, 0); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcb, 0); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcc, 0); - dramc = 0x10; - } - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, dramc); -} - -static void spd_enable_refresh(void) -{ - /* - * Effects: Uses serial presence detect to set the - * refresh rate in the DRAMC register. - * see spd_set_dramc for the other values. - * FIXME: Check for illegal/unsupported ram configurations and abort - */ -#if HAVE_STATIC_ARRAY_SUPPORT - static const unsigned char refresh_rates[] = { - 0x01, /* Normal 15.625 us -> 15.6 us */ - 0x05, /* Reduced(.25X) 3.9 us -> 7.8 us */ - 0x05, /* Reduced(.5X) 7.8 us -> 7.8 us */ - 0x02, /* Extended(2x) 31.3 us -> 31.2 us */ - 0x03, /* Extended(4x) 62.5 us -> 62.4 us */ - 0x04, /* Extended(8x) 125 us -> 124.8 us */ - }; -#endif - /* Find the first dimm and assume the rest are the same */ - int status; - int byte; - unsigned device; - unsigned refresh_rate; - byte = -1; - status = -1; - device = SMBUS_MEM_DEVICE_START; - while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) { - byte = smbus_read_byte(device, 12); - device += SMBUS_MEM_DEVICE_INC; - } - if (byte < 0) { - /* We couldn't find anything we must have no memory */ - sdram_no_memory(); - } - byte &= 0x7f; - /* Default refresh rate be conservative */ - refresh_rate = 5; - /* see if the ram refresh is a supported one */ - if (byte < 6) { -#if HAVE_STATIC_ARRAY_SUPPORT - refresh_rate = refresh_rates[byte]; -#endif - } - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); - byte &= 0xf8; - byte |= refresh_rate; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, byte); -} - -static void spd_set_sdramc(void) -{ - return; -} - -static void spd_set_rps(void) -{ - /* - * Effects: Uses serial presence detect to set the row size - * on a given DIMM - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - /* The RPS register holds the size of a ``page'' of DRAM on each DIMM */ - unsigned page_sizes; - unsigned index; - unsigned device; - unsigned char dramc; - /* default all page sizes to 2KB */ - page_sizes = 0; - index = 0; - device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; index += 4, device += SMBUS_MEM_DEVICE_INC) { - unsigned int status; - unsigned int byte; - int page_size; - - byte = smbus_read_byte(device, 3); - if (byte < 0) continue; - - /* I now have the row page size as a power of 2 */ - page_size = byte & 0xf; - /* make it in multiples of 2Kb */ - page_size -= 11; - - if (page_size <= 0) continue; - - /* FIXME: do something with page sizes greather than 8KB!! */ - page_sizes |= (page_size << index); - - /* side two */ - byte = smbus_read_byte(device, 5); - if (byte <= 1) continue; - - /* For now only handle the symmetrical case */ - page_sizes |= (page_size << (index +2)); - } - /* next block is for Ron's attempt to get registered to work. */ - /* we have just verified that we have to have this code. It appears that - * the registered SDRAMs do indeed set the RPS wrong. sheesh. - */ - /* at this point, page_sizes holds the RPS for all ram. - * we have verified that for registered DRAM the values are - * 1/2 the size they should be. So we test for registered - * and then double the sizes if needed. - */ - - dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); - if (dramc & 0x10) { - /* registered */ - - /* BIOS makes weird page size for registered! */ - /* what we have found is you need to set the EVEN banks to - * twice the size. Fortunately there is a very easy way to - * do this. First, read the WORD value of register 0x74. - */ - page_sizes += 0x1111; - } - - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x74, page_sizes); -} - -static void spd_set_pgpol(void) -{ - /* - * Effects: Uses serial presence detect to set the number of banks - * on a given DIMM - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - /* The PGPOL register stores the number of logical banks per DIMM, - * and number of clocks the DRAM controller waits in the idle - * state. - */ - unsigned device; - unsigned bank_sizes; - unsigned bank; - unsigned reg; - /* default all bank counts 2 */ - bank_sizes = 0; - bank = 0; - device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; - bank += 2, device += SMBUS_MEM_DEVICE_INC) { - int byte; - - /* logical banks */ - byte = smbus_read_byte(device, 17); - if (byte < 0) continue; - if (byte < 4) continue; - bank_sizes |= (1 << bank); - - /* side 2 */ - /* Number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte <= 1) continue; - /* for now only handle the symmetrical case */ - bank_sizes |= (1 << (bank +1)); - } - reg = bank_sizes << 8; - reg |= 0x7; /* 32 clocks idle time */ - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x78, reg); -} - -static void spd_set_nbxcfg(void) -{ - /* - * Effects: Uses serial presence detect to set the - * ECC support flags in the NBXCFG register - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - unsigned reg; - unsigned index; - unsigned device; - - /* Say all dimms have no ECC support */ - reg = 0xff; - index = 0; - - device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) { - int byte; - - byte = smbus_read_byte(device, 11); - if (byte < 0) continue; -#if !USE_ECC - byte = 0; /* Disable ECC */ -#endif - /* 0 == None, 1 == Parity, 2 == ECC */ - if (byte != 2) continue; - reg ^= (1 << index); - - /* side two */ - /* number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte <= 1) continue; - /* There is only the symmetrical case */ - reg ^= (1 << (index +1)); - } - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x53, reg); - /* Now see if reg is 0xff. If it is we are done. If not, - * we need to set 0x18 into register 0x50.l - * we will do this in two steps, first or in 0x80 to 0x50.b, - * then or in 0x1 to 0x51.b - */ -#if HAVE_STRING_SUPPORT - print_debug("spd_set_nbxcfg reg="); print_debug_hex8(reg); print_debug("\n"); -#endif - if (reg != 0xff) { - unsigned char byte; - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x50); - byte |= 0x80; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x50, byte); - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x51); - byte |= 1; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x51, byte); - /* try this. - * We should be setting bit 2 in register 76 and we're not - * technically we should see if CL=2 for the ram, - * but registered is so screwed up that it's kind of a lost - * cause. - */ - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); - byte |= 4; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, byte); -#if HAVE_STRING_SUPPORT - print_debug("spd_set_nbxcfg 0x76.b="); print_debug_hex8(byte); print_debug("\n"); -#endif - } -} - -void sdram_set_spd_registers(void) -{ - spd_set_drb(); - spd_set_dramc(); - spd_set_rps(); - spd_set_sdramc(); - spd_set_pgpol(); - spd_set_nbxcfg(); -} - -void sdram_first_normal_reference(void) -{ - return; -} - -void sdram_special_finishup(void) -{ - return; -} - -static void set_ram_command(unsigned command) -{ - unsigned char byte; - command &= 0x7; - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); - byte &= 0x1f; - byte |= (command << 5); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, byte); -#if HAVE_STRING_SUPPORT - print_debug("set_ram_command 0x76.b="); print_debug_hex8(byte); print_debug("\n"); -#endif -} - -#define RAM_COMMAND_NONE 0x0 -#define RAM_COMMAND_NOOP 0x1 -#define RAM_COMMAND_PRECHARGE 0x2 -#define RAM_COMMAND_MRS 0x3 -#define RAM_COMMAND_CBR 0x4 - -void sdram_set_command_none(void) -{ - set_ram_command(RAM_COMMAND_NONE); -} -void sdram_set_command_noop(void) -{ - set_ram_command(RAM_COMMAND_NOOP); -} -void sdram_set_command_precharge(void) -{ - set_ram_command(RAM_COMMAND_PRECHARGE); -} - -static unsigned long dimm_base(int n) -{ - unsigned char byte; - unsigned long result; - if (n == 0) { - return 0; - } - - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60 + (n - 1)); - result = byte; - result <<= 23; - return result; -} - -static void dimms_read(unsigned long offset) -{ - int i; - for(i = 0; i < 8; i++) { - unsigned long dummy; - unsigned long addr; - unsigned long next_base; - - next_base = dimm_base(i +1); - addr = dimm_base(i); - if (addr == next_base) { - continue; - } - addr += offset; -#if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr); - print_debug("\n"); -#endif -#if HAVE_POINTER_SUPPORT -#if HAVE_MACRO_ARG_SUPPORT - dummy = RAM(unsigned long, addr); -#else - dummy = *((volatile unsigned long *)(addr)); -#endif -#endif -#if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr ^ 0xddf8); - print_debug("\n"); -#endif -#if HAVE_POINTER_SUPPORT -#if HAVE_MACRO_ARG_SUPPORT - dummy = RAM(unsigned long, addr ^ 0xdff8); -#else - dummy = *((volatile unsigned long *)(addr ^ 0xdff8)); -#endif -#endif -#if HAVE_STRING_SUPPORT - print_debug("Read "); - print_debug_hex32(addr); - print_debug_hex32(addr ^ 0xddf8); - print_debug("\n"); -#endif - } -} - -void sdram_set_command_cbr(void) -{ - set_ram_command(RAM_COMMAND_CBR); -} - -void sdram_assert_command(void) -{ - dimms_read(0x400); -} - -void sdram_set_mode_register(void) -{ - unsigned char byte; - unsigned cas_mode; - set_ram_command(RAM_COMMAND_MRS); - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); - cas_mode = byte & 0x4; - cas_mode ^= 4; - cas_mode <<= 2; - cas_mode |= 0x2a; - cas_mode <<= 3; - dimms_read(cas_mode); -} - -void sdram_enable_refresh(void) -{ - spd_enable_refresh(); -} - - -unsigned long sdram_get_ecc_size_bytes(void) -{ - unsigned char byte; - unsigned long size; - /* FIXME handle the no ram case. */ - /* Read the RAM SIZE */ - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67); - /* Convert it to bytes */ - size = byte; - size <<= 23; -#if !USE_ECC - size = 0; -#endif - return size; -} - -/* Dummy udelay code acting as a place holder... */ -void udelay(int count) -{ - int i; - i = 5; -} - -void sdram_enable(void) -{ -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 1\n"); -#endif - - /* noop command */ - sdram_set_command_noop(); - udelay(200); - sdram_assert_command(); - - /* Precharge all */ - sdram_set_command_precharge(); - sdram_assert_command(); - - /* wait until the all banks idle state... */ -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 2\n"); -#endif - - /* Now we need 8 AUTO REFRESH / CBR cycles to be performed */ - - sdram_set_command_cbr(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 3\n"); -#endif - - /* mode register set */ - sdram_set_mode_register(); - /* MAx[14:0] lines, - * MAx[2:0 ] 010 == burst mode of 4 - * MAx[3:3 ] 1 == interleave wrap type - * MAx[4:4 ] == CAS# latency bit - * MAx[6:5 ] == 01 - * MAx[12:7] == 0 - */ - -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 4\n"); -#endif - - /* normal operation */ - sdram_set_command_none(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 5\n"); -#endif -} - -/* Setup SDRAM */ -void sdram_initialize(void) -{ -#if HAVE_STRING_SUPPORT - print_debug("Ram1\n"); -#endif - /* Set the registers we can set once to reasonable values */ - sdram_set_registers(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram2\n"); -#endif - /* Now setup those things we can auto detect */ - sdram_set_spd_registers(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram3\n"); -#endif - /* Now that everything is setup enable the SDRAM. - * Some chipsets do the work for use while on others - * we need to it by hand. - */ - sdram_enable(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram4\n"); -#endif - sdram_first_normal_reference(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram5\n"); -#endif - sdram_enable_refresh(); - sdram_special_finishup(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram6\n"); -#endif -} diff --git a/util/romcc/tests/raminit_test2.c b/util/romcc/tests/raminit_test2.c deleted file mode 100644 index af6eaaef88..0000000000 --- a/util/romcc/tests/raminit_test2.c +++ /dev/null @@ -1,1292 +0,0 @@ -#define HAVE_STRING_SUPPORT 1 -#define HAVE_CAST_SUPPORT 1 -#define HAVE_STATIC_ARRAY_SUPPORT 1 -#define HAVE_POINTER_SUPPORT 1 -#define HAVE_MACRO_ARG_SUPPORT 0 - -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} - -void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} - -unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where) -{ - return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3); -} - -static unsigned char pcibios_read_config_byte( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inb(0xCFC + (where & 3)); -} - -static unsigned short pcibios_read_config_word( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inw(0xCFC + (where & 2)); -} - -static unsigned int pcibios_read_config_dword( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inl(0xCFC); -} - - -static void pcibios_write_config_byte( - unsigned char bus, unsigned devfn, unsigned where, unsigned char value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); -} - -static void pcibios_write_config_word( - unsigned char bus, unsigned devfn, unsigned where, unsigned short value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); -} - -static void pcibios_write_config_dword( - unsigned char bus, unsigned devfn, unsigned where, unsigned int value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outl(value, 0xCFC); -} - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - -void __console_tx_char(unsigned char byte) -{ - uart_tx_byte(byte); -} -void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_char(digit); -} -void __console_tx_hex8(unsigned char byte) -{ - __console_tx_nibble(byte >> 4); - __console_tx_nibble(byte & 0x0f); -} - -void __console_tx_hex32(unsigned char value) -{ - __console_tx_nibble((value >> 28) & 0x0f); - __console_tx_nibble((value >> 24) & 0x0f); - __console_tx_nibble((value >> 20) & 0x0f); - __console_tx_nibble((value >> 16) & 0x0f); - __console_tx_nibble((value >> 12) & 0x0f); - __console_tx_nibble((value >> 8) & 0x0f); - __console_tx_nibble((value >> 4) & 0x0f); - __console_tx_nibble(value & 0x0f); -} - -#if HAVE_STRING_SUPPORT -void __console_tx_string(char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_char(ch); - } -} -#else -void __console_tx_string(char *str) -{ -} -#endif - - -void print_emerg_char(unsigned char byte) { __console_tx_char(byte); } -void print_emerg_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_emerg_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_emerg(char *str) { __console_tx_string(str); } - -void print_alert_char(unsigned char byte) { __console_tx_char(byte); } -void print_alert_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_alert_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_alert(char *str) { __console_tx_string(str); } - -void print_crit_char(unsigned char byte) { __console_tx_char(byte); } -void print_crit_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_crit_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_crit(char *str) { __console_tx_string(str); } - -void print_err_char(unsigned char byte) { __console_tx_char(byte); } -void print_err_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_err_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_err(char *str) { __console_tx_string(str); } - -void print_warning_char(unsigned char byte) { __console_tx_char(byte); } -void print_warning_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_warning_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_warning(char *str) { __console_tx_string(str); } - -void print_notice_char(unsigned char byte) { __console_tx_char(byte); } -void print_notice_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_notice_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_notice(char *str) { __console_tx_string(str); } - -void print_info_char(unsigned char byte) { __console_tx_char(byte); } -void print_info_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_info_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_info(char *str) { __console_tx_string(str); } - -void print_debug_char(unsigned char byte) { __console_tx_char(byte); } -void print_debug_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_debug(char *str) { __console_tx_string(str); } - -void print_spew_char(unsigned char byte) { __console_tx_char(byte); } -void print_spew_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_spew_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_spew(char *str) { __console_tx_string(str); } - -#define PIIX4_DEVFN 0x90 -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - - -#define PM_BUS 0 -#define PM_DEVFN (PIIX4_DEVFN+3) - -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 - -void smbus_enable(void) -{ - /* iobase addr */ - pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x90, SMBUS_IO_BASE | 1); - /* smbus enable */ - pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0xd2, (0x4 << 1) | 1); - /* iospace enable */ - pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1); -} - -void smbus_setup(void) -{ - outb(0, SMBUS_IO_BASE + SMBHSTSTAT); -} - -static void smbus_wait_until_ready(void) -{ - while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - }while((byte &1) == 1); - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char host_status_register; - unsigned char byte; - int result; - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - - result = byte; - if (host_status_register != 0x02) { - result = -1; - } - return result; -} - -#define I440GX_BUS 0 -#define I440GX_DEVFN ((0x00 << 3) + 0) - -#define USE_ECC 0 - -#define CAS_LATENCY 3 - - /* CAS latency 2 */ -#if (CAS_LATENCY == 2) -#define CAS_NB 0x17 - /* - * 7 == 0111 - * 1 == 0001 - */ -#define CAS_MODE 0x2a - /* - * a == 1010 - * 2 == 0010 - */ -#endif - - /* CAS latency 3 */ -#if (CAS_LATENCY == 3) -#define CAS_NB 0x13 - /* - * 3 == 0011 - * 1 == 0001 - */ -#define CAS_MODE 0x3a - /* - * a == 1010 - * 3 == 0011 - */ -#endif - -#ifndef CAS_NB -#error "Nothing defined" -#endif - -/* Default values for config registers */ - -static void set_nbxcfg(void) -{ - /* NBXCFG 0x50 - 0x53 */ - /* f == 1111 - * 0 == 0000 - * 0 == 0000 - * 0 == 0000 - * 0 == 0000 - * 1 == 0001 - * 8 == 1000 - * c == 1100 - * SDRAM Row without ECC: - * row 0 == 1 No ECC - * row 1 == 1 No ECC - * row 2 == 1 No ECC - * row 3 == 1 No ECC - * row 4 == 1 No ECC - * row 5 == 1 No ECC - * row 6 == 1 No ECC - * row 7 == 1 No ECC - * Host Bus Fast Data Ready Enable == 0 Disabled - * IDSEL_REDIRECT == 0 (430TX compatibility disable?) - * WSC# Hanshake Disable == 0 enable (Use External IOAPIC) - * Host/DRAM Frequence == 00 100Mhz - * AGP to PCI Access Enable == 0 Disable - * PCI Agent to Aperture Access Disable == 0 Enable (Ignored) - * Aperture Access Global Enable == 0 Disable - * DRAM Data Integrity Mode == 11 (Error Checking/Correction) - * ECC Diagnostic Mode Enable == 0 Not Enabled - * MDA present == 0 Not Present - * USWC Write Post During During I/O Bridge Access Enable == 1 Enabled - * In Order Queue Depth (IQD) (RO) == ?? - */ - pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c); -} - -static void set_dramc(void) -{ - /* 0 == 0000 - * 8 == 1000 - * Not registered SDRAM - * refresh disabled - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, 0x8); -} - -static void set_pam(void) -{ - /* PAM - Programmable Attribute Map Registers */ - /* Ideally we want to enable all of these as DRAM and teach - * linux it is o.k. to use them... - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x59, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5a, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5b, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5d, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5e, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5f, 0x00); -} - -static void set_drb(void) -{ - /* DRB - DRAM Row Boundary Registers */ - /* Conservative setting 8MB of ram on first DIMM... */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x61, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x62, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x63, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x64, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x65, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x66, 0x01); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67, 0x01); -} - -static void set_fdhc(void) -{ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x68, 0x00); -} -static void set_mbsc(void) -{ - /* MBSC - Memory Buffer Strength Control */ - /* 00c00003e820 - * [47:44] 0 == 0000 - * [43:40] 0 == 0000 - * [39:36] c == 1100 - * [35:32] 0 == 0000 - * [31:28] 0 == 0000 - * [27:24] 0 == 0000 - * [23:20] 0 == 0000 - * [19:16] 3 == 0011 - * [15:12] e == 1110 - * [11: 8] 8 == 1000 - * [ 7: 4] 2 == 0010 - * [ 3: 0] 0 == 0000 - * MAA[14:0]#, WEA#, SRASA#, SCASA# Buffer Strengths == 3x - * MAB[14,13,10,12:11,9:0]#, WEB#, SRASB#, SCASB# Buffer Strengths == 3x - * MD[63:0]# Buffer Strength Control 2 == 3x - * MD[63:0]# Buffer Strength Control 1 == 3x - * MECC[7:0] Buffer Strength Control 2 == 3x - * MECC[7:0] Buffer Strength Control 1 == 3x - * CSB7# Buffer Strength == 3x - * CSA7# Buffer Strength == 3x - * CSB6# Buffer Strength == 3x - * CSA6# Buffer Strength == 3x - * CSA5#/CSB5# Buffer Strength == 2x - * CSA4#/CSB4# Buffer Strength == 2x - * CSA3#/CSB3# Buffer Strength == 2x - * CSA2#/CSB2# Buffer Strength == 2x - * CSA1#/CSB1# Buffer Strength == 2x - * CSA0#/CSB0# Buffer Strength == 2x - * DQMA5 Buffer Strength == 2x - * DQMA1 Buffer Strength == 3x - * DQMB5 Buffer Strength == 2x - * DQMB1 Buffer Strength == 2x - * DQMA[7:6,4:2,0] Buffer Strength == 3x - * GCKE Buffer Strength == 1x - * FENA Buffer Strength == 3x - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x69, 0xB3); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6a, 0xee); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6b, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6c, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6d, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6e, 0x03); -} - -static void set_smram(void) -{ - /* 0x72 SMRAM */ - /* 1 == 0001 - * a == 1010 - * SMM Compatible base segment == 010 (Hardcoded value) - */ -} - -static void set_esramc(void) -{ - /* 0x73 ESMRAMC */ -} - -static void set_rps(void) -{ - /* RPS - Row Page Size Register */ - /* 0x0055 - * [15:12] 0 == 0000 - * [11: 8] 0 == 0000 - * [ 7: 4] 5 == 0101 - * [ 3: 0] 5 == 0101 - * DRB[0] == 4KB - * DRB[1] == 4KB - * DRB[2] == 4KB - * DRB[3] == 4KB - * DRB[4] == 2KB - * DRB[5] == 2KB - * DRB[6] == 2KB - * DRB[7] == 2KB - */ - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x74, 0x5555); -} - -static void set_sdramc(void) -{ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, CAS_NB); -} - -static void set_pgpol(void) -{ - /* PGPOL - Paging Policy Register */ - /* 0xff07 - * [15:12] f == 1111 - * [11: 8] f == 1111 - * [ 7: 4] 0 == 0000 - * [ 3: 0] 7 == 0111 - * row0 == 4banks - * row1 == 4banks - * row2 == 4banks - * row3 == 4banks - * row4 == 4banks - * row5 == 4banks - * row6 == 4banks - * row7 == 4banks - * Dram Idle Timer (DIT) == 32 clocks - */ - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x78, 0xff07); -} - -static void set_mbfs(void) -{ - /* MBFS - Memory Buffer Frequencey Select Register */ - /* 0xffff7f - * [23:20] f == 1111 - * [19:16] f == 1111 - * [15:12] f == 1111 - * [11: 8] f == 1111 - * [ 7: 4] 7 == 0111 - * [ 3: 0] f == 1111 - * MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled - * MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled - * MD[63:0] Control 2 == 100 Mhz Buffer Enable - * MD[63:0] Control 1 == 100 Mhz B - * MECC[7:0] Control 2 == 100 Mhz B - * - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xca, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcb, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcc, 0x7f); -} - -static void set_dwtc(void) -{ - /* DWTC - DRAM Write Thermal Throttle Control */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe0, 0xb4); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe1, 0xbe); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe2, 0xff); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe3, 0xd7); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe4, 0x97); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe5, 0x3e); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe6, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe7, 0x80); -} - -static void set_drtc(void) -{ - /* DRTC - DRAM Read Thermal Throttle Control */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe8, 0x2c); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe9, 0xd3); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xea, 0xf7); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xeb, 0xcf); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xec, 0x9d); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xed, 0x3e); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xee, 0x00); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xef, 0x00); -} - -static void set_pmcr(void) -{ - /* PMCR -- BIOS sets 0x90 into it. - * 0x10 is REQUIRED. - * we have never used it. So why did this ever work? - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90); - -} -void sdram_set_registers(void) -{ - set_nbxcfg(); - set_dramc(); - set_pam(); - set_drb(); - set_fdhc(); - set_mbsc(); - set_smram(); - set_esramc(); - set_rps(); - set_sdramc(); - set_pgpol(); - set_mbfs(); - set_dwtc(); - set_drtc(); - set_pmcr(); -} - -int log2(int value) -{ - /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 - * when the value presented to it is zero. - * Otherwise __builtin_bsr returns the zero based index of - * the highest bit set. - */ - return __builtin_bsr(value); -} - - -static void spd_set_drb(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRB registers which holds the ending memory address assigned - * to each DIMM. - */ - unsigned end_of_memory; - unsigned device; - unsigned drb_reg; - - end_of_memory = 0; /* in multiples of 8MiB */ - device = SMBUS_MEM_DEVICE_START; - drb_reg = 0x60; - while (device <= SMBUS_MEM_DEVICE_END) { - unsigned side1_bits, side2_bits; - int byte, byte2; - - side1_bits = side2_bits = -1; - - /* rows */ - byte = smbus_read_byte(device, 3); - if (byte >= 0) { - side1_bits += byte & 0xf; - - /* columns */ - byte = smbus_read_byte(device, 4); - side1_bits += byte & 0xf; - - /* banks */ - byte = smbus_read_byte(device, 17); - side1_bits += log2(byte); - - /* Get the moduel data width and convert it to a power of two */ - /* low byte */ - byte = smbus_read_byte(device, 6); - - /* high byte */ - byte2 = smbus_read_byte(device, 7); -#if HAVE_CAST_SUPPORT - side1_bits += log2((((unsigned long)byte2 << 8)| byte)); -#else - side1_bits += log2((byte2 << 8) | byte); -#endif - - /* now I have the ram size in bits as a power of two (less 1) */ - /* Make it mulitples of 8MB */ - side1_bits -= 25; - - /* side two */ - - /* number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte > 1) { - /* for now only handle the symmetrical case */ - side2_bits = side1_bits; - } - } - - /* Compute the end address for the DRB register */ - /* Only process dimms < 2GB (2^8 * 8MB) */ - if (side1_bits < 8) { - end_of_memory += (1 << side1_bits); - } -#if HAVE_STRING_SUPPORT - print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n"); -#endif - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg, end_of_memory); - - if (side2_bits < 8 ) { - end_of_memory += (1 << side2_bits); - } -#if HAVE_STRING_SUPPORT - print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n"); -#endif - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg +1, end_of_memory); - - drb_reg += 2; - device += SMBUS_MEM_DEVICE_INC; - } -} - -void sdram_no_memory(void) -{ -#if HAVE_STRING_SUPPORT - print_err("No memory!!\n"); -#endif - while(1) ; -} - -static void spd_set_dramc(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRAMC register, which records if ram is registered or not, - * and controls the refresh rate. - * The refresh rate is not set here, as memory refresh - * cannot be enbaled until after memory is initialized. - * see spd_enable_refresh. - */ - /* auto detect if ram is registered or not. */ - /* The DRAMC register also contorls the refresh rate but we can't - * set that here because we must leave refresh disabled. - * see: spd_enable_refresh - */ - /* Find the first dimm and assume the rest are the same */ - /* FIXME Check for illegal/unsupported ram configurations and abort */ - unsigned device; - int byte; - unsigned dramc; - byte = -1; - device = SMBUS_MEM_DEVICE_START; - - while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) { - byte = smbus_read_byte(device, 21); - device += SMBUS_MEM_DEVICE_INC; - } - if (byte < 0) { - /* We couldn't find anything we must have no memory */ - sdram_no_memory(); - } - dramc = 0x8; - if ((byte & 0x12) != 0) { - /* this is a registered part. - * observation: for register parts, BIOS zeros (!) - * registers CA-CC. This has an undocumented meaning. - */ - /* But it does make sense the oppisite of registered - * sdram is buffered and 0xca - 0xcc control the buffers. - * Clearing them aparently disables them. - */ - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xca, 0); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcb, 0); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcc, 0); - dramc = 0x10; - } - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, dramc); -} - -static void spd_enable_refresh(void) -{ - /* - * Effects: Uses serial presence detect to set the - * refresh rate in the DRAMC register. - * see spd_set_dramc for the other values. - * FIXME: Check for illegal/unsupported ram configurations and abort - */ -#if HAVE_STATIC_ARRAY_SUPPORT - static const unsigned char refresh_rates[] = { - 0x01, /* Normal 15.625 us -> 15.6 us */ - 0x05, /* Reduced(.25X) 3.9 us -> 7.8 us */ - 0x05, /* Reduced(.5X) 7.8 us -> 7.8 us */ - 0x02, /* Extended(2x) 31.3 us -> 31.2 us */ - 0x03, /* Extended(4x) 62.5 us -> 62.4 us */ - 0x04, /* Extended(8x) 125 us -> 124.8 us */ - }; -#endif - /* Find the first dimm and assume the rest are the same */ - int status; - int byte; - unsigned device; - unsigned refresh_rate; - byte = -1; - status = -1; - device = SMBUS_MEM_DEVICE_START; - while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) { - byte = smbus_read_byte(device, 12); - device += SMBUS_MEM_DEVICE_INC; - } - if (byte < 0) { - /* We couldn't find anything we must have no memory */ - sdram_no_memory(); - } - byte &= 0x7f; - /* Default refresh rate be conservative */ - refresh_rate = 5; - /* see if the ram refresh is a supported one */ - if (byte < 6) { -#if HAVE_STATIC_ARRAY_SUPPORT - refresh_rate = refresh_rates[byte]; -#endif - } - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); - byte &= 0xf8; - byte |= refresh_rate; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, byte); -} - -static void spd_set_sdramc(void) -{ - return; -} - -static void spd_set_rps(void) -{ - /* - * Effects: Uses serial presence detect to set the row size - * on a given DIMM - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - /* The RPS register holds the size of a ``page'' of DRAM on each DIMM */ - unsigned page_sizes; - unsigned index; - unsigned device; - unsigned char dramc; - /* default all page sizes to 2KB */ - page_sizes = 0; - index = 0; - device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; index += 4, device += SMBUS_MEM_DEVICE_INC) { - unsigned int status; - unsigned int byte; - int page_size; - - byte = smbus_read_byte(device, 3); - if (byte < 0) continue; - - /* I now have the row page size as a power of 2 */ - page_size = byte & 0xf; - /* make it in multiples of 2Kb */ - page_size -= 11; - - if (page_size <= 0) continue; - - /* FIXME: do something with page sizes greather than 8KB!! */ - page_sizes |= (page_size << index); - - /* side two */ - byte = smbus_read_byte(device, 5); - if (byte <= 1) continue; - - /* For now only handle the symmetrical case */ - page_sizes |= (page_size << (index +2)); - } - /* next block is for Ron's attempt to get registered to work. */ - /* we have just verified that we have to have this code. It appears that - * the registered SDRAMs do indeed set the RPS wrong. sheesh. - */ - /* at this point, page_sizes holds the RPS for all ram. - * we have verified that for registered DRAM the values are - * 1/2 the size they should be. So we test for registered - * and then double the sizes if needed. - */ - - dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); - if (dramc & 0x10) { - /* registered */ - - /* BIOS makes weird page size for registered! */ - /* what we have found is you need to set the EVEN banks to - * twice the size. Fortunately there is a very easy way to - * do this. First, read the WORD value of register 0x74. - */ - page_sizes += 0x1111; - } - - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x74, page_sizes); -} - -static void spd_set_pgpol(void) -{ - /* - * Effects: Uses serial presence detect to set the number of banks - * on a given DIMM - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - /* The PGPOL register stores the number of logical banks per DIMM, - * and number of clocks the DRAM controller waits in the idle - * state. - */ - unsigned device; - unsigned bank_sizes; - unsigned bank; - unsigned reg; - /* default all bank counts 2 */ - bank_sizes = 0; - bank = 0; - device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; - bank += 2, device += SMBUS_MEM_DEVICE_INC) { - int byte; - - /* logical banks */ - byte = smbus_read_byte(device, 17); - if (byte < 0) continue; - if (byte < 4) continue; - bank_sizes |= (1 << bank); - - /* side 2 */ - /* Number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte <= 1) continue; - /* for now only handle the symmetrical case */ - bank_sizes |= (1 << (bank +1)); - } - reg = bank_sizes << 8; - reg |= 0x7; /* 32 clocks idle time */ - pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x78, reg); -} - -static void spd_set_nbxcfg(void) -{ - /* - * Effects: Uses serial presence detect to set the - * ECC support flags in the NBXCFG register - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - unsigned reg; - unsigned index; - unsigned device; - - /* Say all dimms have no ECC support */ - reg = 0xff; - index = 0; - - device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) { - int byte; - - byte = smbus_read_byte(device, 11); - if (byte < 0) continue; -#if !USE_ECC - byte = 0; /* Disable ECC */ -#endif - /* 0 == None, 1 == Parity, 2 == ECC */ - if (byte != 2) continue; - reg ^= (1 << index); - - /* side two */ - /* number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte <= 1) continue; - /* There is only the symmetrical case */ - reg ^= (1 << (index +1)); - } - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x53, reg); - /* Now see if reg is 0xff. If it is we are done. If not, - * we need to set 0x18 into register 0x50.l - * we will do this in two steps, first or in 0x80 to 0x50.b, - * then or in 0x1 to 0x51.b - */ -#if HAVE_STRING_SUPPORT - print_debug("spd_set_nbxcfg reg="); print_debug_hex8(reg); print_debug("\n"); -#endif - if (reg != 0xff) { - unsigned char byte; - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x50); - byte |= 0x80; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x50, byte); - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x51); - byte |= 1; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x51, byte); - /* try this. - * We should be setting bit 2 in register 76 and we're not - * technically we should see if CL=2 for the ram, - * but registered is so screwed up that it's kind of a lost - * cause. - */ - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); - byte |= 4; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, byte); -#if HAVE_STRING_SUPPORT - print_debug("spd_set_nbxcfg 0x76.b="); print_debug_hex8(byte); print_debug("\n"); -#endif - } -} - -void sdram_set_spd_registers(void) -{ - spd_set_drb(); - spd_set_dramc(); - spd_set_rps(); - spd_set_sdramc(); - spd_set_pgpol(); - spd_set_nbxcfg(); -} - -void sdram_first_normal_reference(void) -{ - return; -} - -void sdram_special_finishup(void) -{ - return; -} - -static void set_ram_command(unsigned command) -{ - unsigned char byte; - command &= 0x7; - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); - byte &= 0x1f; - byte |= (command << 5); - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, byte); -#if HAVE_STRING_SUPPORT - print_debug("set_ram_command 0x76.b="); print_debug_hex8(byte); print_debug("\n"); -#endif -} - -#define RAM_COMMAND_NONE 0x0 -#define RAM_COMMAND_NOOP 0x1 -#define RAM_COMMAND_PRECHARGE 0x2 -#define RAM_COMMAND_MRS 0x3 -#define RAM_COMMAND_CBR 0x4 - -void sdram_set_command_none(void) -{ - set_ram_command(RAM_COMMAND_NONE); -} -void sdram_set_command_noop(void) -{ - set_ram_command(RAM_COMMAND_NOOP); -} -void sdram_set_command_precharge(void) -{ - set_ram_command(RAM_COMMAND_PRECHARGE); -} - -static unsigned long dimm_base(int n) -{ - unsigned char byte; - unsigned long result; - if (n == 0) { - return 0; - } - - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60 + (n - 1)); - result = byte; - result <<= 23; - return result; -} - -static void dimms_read(unsigned long offset) -{ - int i; - for(i = 0; i < 8; i++) { - unsigned long dummy; - unsigned long addr; - unsigned long next_base; - - next_base = dimm_base(i +1); - addr = dimm_base(i); - if (addr == next_base) { - continue; - } - addr += offset; -#if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr); - print_debug("\n"); -#endif -#if HAVE_POINTER_SUPPORT -#if HAVE_MACRO_ARG_SUPPORT - dummy = RAM(unsigned long, addr); -#else - dummy = *((volatile unsigned long *)(addr)); -#endif -#endif -#if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr ^ 0xddf8); - print_debug("\n"); -#endif -#if HAVE_POINTER_SUPPORT -#if HAVE_MACRO_ARG_SUPPORT - dummy = RAM(unsigned long, addr ^ 0xdff8); -#else - dummy = *((volatile unsigned long *)(addr ^ 0xdff8)); -#endif -#endif -#if HAVE_STRING_SUPPORT - print_debug("Read "); - print_debug_hex32(addr); - print_debug_hex32(addr ^ 0xddf8); - print_debug("\n"); -#endif - } -} - -void sdram_set_command_cbr(void) -{ - set_ram_command(RAM_COMMAND_CBR); -} - -void sdram_assert_command(void) -{ - dimms_read(0x400); -} - -void sdram_set_mode_register(void) -{ - unsigned char byte; - unsigned cas_mode; - set_ram_command(RAM_COMMAND_MRS); - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); - cas_mode = byte & 0x4; - cas_mode ^= 4; - cas_mode <<= 2; - cas_mode |= 0x2a; - cas_mode <<= 3; - dimms_read(cas_mode); -} - -void sdram_enable_refresh(void) -{ - spd_enable_refresh(); -} - - -unsigned long sdram_get_ecc_size_bytes(void) -{ - unsigned char byte; - unsigned long size; - /* FIXME handle the no ram case. */ - /* Read the RAM SIZE */ - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67); - /* Convert it to bytes */ - size = byte; - size <<= 23; -#if !USE_ECC - size = 0; -#endif - return size; -} - -/* Dummy udelay code acting as a place holder... */ -void udelay(int count) -{ - int i; - i = 5; -} - -void sdram_enable(void) -{ -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 1\n"); -#endif - - /* noop command */ - sdram_set_command_noop(); - udelay(200); - sdram_assert_command(); - - /* Precharge all */ - sdram_set_command_precharge(); - sdram_assert_command(); - - /* wait until the all banks idle state... */ -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 2\n"); -#endif - - /* Now we need 8 AUTO REFRESH / CBR cycles to be performed */ - - sdram_set_command_cbr(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - sdram_assert_command(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 3\n"); -#endif - - /* mode register set */ - sdram_set_mode_register(); - /* MAx[14:0] lines, - * MAx[2:0 ] 010 == burst mode of 4 - * MAx[3:3 ] 1 == interleave wrap type - * MAx[4:4 ] == CAS# latency bit - * MAx[6:5 ] == 01 - * MAx[12:7] == 0 - */ - -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 4\n"); -#endif - - /* normal operation */ - sdram_set_command_none(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram Enable 5\n"); -#endif -} - -/* Setup SDRAM */ -void sdram_initialize(void) -{ -#if HAVE_STRING_SUPPORT - print_debug("Ram1\n"); -#endif - /* Set the registers we can set once to reasonable values */ - sdram_set_registers(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram2\n"); -#endif - /* Now setup those things we can auto detect */ - sdram_set_spd_registers(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram3\n"); -#endif - /* Now that everything is setup enable the SDRAM. - * Some chipsets do the work for use while on others - * we need to it by hand. - */ - sdram_enable(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram4\n"); -#endif - sdram_first_normal_reference(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram5\n"); -#endif - sdram_enable_refresh(); - sdram_special_finishup(); - -#if HAVE_STRING_SUPPORT - print_debug("Ram6\n"); -#endif -} diff --git a/util/romcc/tests/raminit_test3.c b/util/romcc/tests/raminit_test3.c deleted file mode 100644 index dc3b4760c2..0000000000 --- a/util/romcc/tests/raminit_test3.c +++ /dev/null @@ -1,1076 +0,0 @@ -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" -# 1 "<built-in>" -# 1 "<command line>" -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/include/stdint.h" 1 -# 11 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/include/stdint.h" -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - - - - - - - -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - - - - - - - -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - - - - - - - -typedef int intptr_t; -typedef unsigned int uintptr_t; - - - - - - -typedef long int intmax_t; -typedef unsigned long int uintmax_t; -# 3 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/include/device/pci_def.h" 1 -# 4 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/include/arch/romcc_io.h" 1 -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -static void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} - -static void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - - -static unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - - -static unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} - -static unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static void hlt(void) -{ - __builtin_hlt(); -} - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} - - - - - - - -static unsigned char pci_read_config8(unsigned addr) -{ - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} - -static unsigned short pci_read_config16(unsigned addr) -{ - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} - -static unsigned int pci_read_config32(unsigned addr) -{ - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -static void pci_write_config8(unsigned addr, unsigned char value) -{ - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config16(unsigned addr, unsigned short value) -{ - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} - -static void pci_write_config32(unsigned addr, unsigned int value) -{ - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} -# 5 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/pc80/serial.c" 1 -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/include/part/fallback_boot.h" 1 -# 2 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/pc80/serial.c" 2 -# 44 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/pc80/serial.c" -static int uart_can_tx_byte(void) -{ - return inb(0x3f8 + 0x05) & 0x20; -} - -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -static void uart_wait_until_sent(void) -{ - while(!(inb(0x3f8 + 0x05) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, 0x3f8 + 0x00); - - uart_wait_until_sent(); -} - -static void uart_init(void) -{ - - outb(0x0, 0x3f8 + 0x01); - - outb(0x01, 0x3f8 + 0x02); - - outb(0x80 | 0x3, 0x3f8 + 0x03); -# 89 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/pc80/serial.c" - outb((115200/9600) & 0xFF, 0x3f8 + 0x00); - outb(((115200/9600) >> 8) & 0xFF, 0x3f8 + 0x01); - - outb(0x3, 0x3f8 + 0x03); -} -# 6 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/lib/console.c" 1 -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/include/console/loglevel.h" 1 -# 2 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/lib/console.c" 2 - -static void __console_tx_byte(unsigned char byte) -{ - uart_tx_byte(byte); -} - -static void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_byte(digit); -} - -static void __console_tx_char(int loglevel, unsigned char byte) -{ - if (8 > loglevel) { - uart_tx_byte(byte); - } -} - -static void __console_tx_hex8(int loglevel, unsigned char value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_hex16(int loglevel, unsigned short value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_hex32(int loglevel, unsigned int value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 28U) & 0x0fU); - __console_tx_nibble((value >> 24U) & 0x0fU); - __console_tx_nibble((value >> 20U) & 0x0fU); - __console_tx_nibble((value >> 16U) & 0x0fU); - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_string(int loglevel, const char *str) -{ - if (8 > loglevel) { - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_byte(ch); - } - } -} - -static void print_emerg_char(unsigned char byte) { __console_tx_char(0, byte); } -static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(0, value); } -static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(0, value); } -static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(0, value); } -static void print_emerg(const char *str) { __console_tx_string(0, str); } - -static void print_alert_char(unsigned char byte) { __console_tx_char(1, byte); } -static void print_alert_hex8(unsigned char value) { __console_tx_hex8(1, value); } -static void print_alert_hex16(unsigned short value){ __console_tx_hex16(1, value); } -static void print_alert_hex32(unsigned int value) { __console_tx_hex32(1, value); } -static void print_alert(const char *str) { __console_tx_string(1, str); } - -static void print_crit_char(unsigned char byte) { __console_tx_char(2, byte); } -static void print_crit_hex8(unsigned char value) { __console_tx_hex8(2, value); } -static void print_crit_hex16(unsigned short value){ __console_tx_hex16(2, value); } -static void print_crit_hex32(unsigned int value) { __console_tx_hex32(2, value); } -static void print_crit(const char *str) { __console_tx_string(2, str); } - -static void print_err_char(unsigned char byte) { __console_tx_char(3, byte); } -static void print_err_hex8(unsigned char value) { __console_tx_hex8(3, value); } -static void print_err_hex16(unsigned short value){ __console_tx_hex16(3, value); } -static void print_err_hex32(unsigned int value) { __console_tx_hex32(3, value); } -static void print_err(const char *str) { __console_tx_string(3, str); } - -static void print_warning_char(unsigned char byte) { __console_tx_char(4, byte); } -static void print_warning_hex8(unsigned char value) { __console_tx_hex8(4, value); } -static void print_warning_hex16(unsigned short value){ __console_tx_hex16(4, value); } -static void print_warning_hex32(unsigned int value) { __console_tx_hex32(4, value); } -static void print_warning(const char *str) { __console_tx_string(4, str); } - -static void print_notice_char(unsigned char byte) { __console_tx_char(5, byte); } -static void print_notice_hex8(unsigned char value) { __console_tx_hex8(5, value); } -static void print_notice_hex16(unsigned short value){ __console_tx_hex16(5, value); } -static void print_notice_hex32(unsigned int value) { __console_tx_hex32(5, value); } -static void print_notice(const char *str) { __console_tx_string(5, str); } - -static void print_info_char(unsigned char byte) { __console_tx_char(6, byte); } -static void print_info_hex8(unsigned char value) { __console_tx_hex8(6, value); } -static void print_info_hex16(unsigned short value){ __console_tx_hex16(6, value); } -static void print_info_hex32(unsigned int value) { __console_tx_hex32(6, value); } -static void print_info(const char *str) { __console_tx_string(6, str); } - -static void print_debug_char(unsigned char byte) { __console_tx_char(7, byte); } -static void print_debug_hex8(unsigned char value) { __console_tx_hex8(7, value); } -static void print_debug_hex16(unsigned short value){ __console_tx_hex16(7, value); } -static void print_debug_hex32(unsigned int value) { __console_tx_hex32(7, value); } -static void print_debug(const char *str) { __console_tx_string(7, str); } - -static void print_spew_char(unsigned char byte) { __console_tx_char(8, byte); } -static void print_spew_hex8(unsigned char value) { __console_tx_hex8(8, value); } -static void print_spew_hex16(unsigned short value){ __console_tx_hex16(8, value); } -static void print_spew_hex32(unsigned int value) { __console_tx_hex32(8, value); } -static void print_spew(const char *str) { __console_tx_string(8, str); } -# 128 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/arch/i386/lib/console.c" -static void console_init(void) -{ - static const char console_test[] = - "\r\n\r\nLinuxBIOS-" - "1.1.0" - ".0Fallback" - " " - "Mon Jun 9 18:15:20 MDT 2003" - " starting...\r\n"; - print_info(console_test); -} -# 7 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/ram/ramtest.c" 1 -static void write_phys(unsigned long addr, unsigned long value) -{ - volatile unsigned long *ptr; - ptr = (void *)addr; - *ptr = value; -} - -static unsigned long read_phys(unsigned long addr) -{ - volatile unsigned long *ptr; - ptr = (void *)addr; - return *ptr; -} - -void ram_fill(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - - - print_debug("DRAM fill: "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - - if ((addr & 0xffff) == 0) { - print_debug_hex32(addr); - print_debug("\r"); - } - write_phys(addr, addr); - }; - - print_debug_hex32(addr); - print_debug("\r\nDRAM filled\r\n"); -} - -void ram_verify(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - - - print_debug("DRAM verify: "); - print_debug_hex32(start); - print_debug_char('-'); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - unsigned long value; - - if ((addr & 0xffff) == 0) { - print_debug_hex32(addr); - print_debug("\r"); - } - value = read_phys(addr); - if (value != addr) { - - print_err_hex32(addr); - print_err_char(':'); - print_err_hex32(value); - print_err("\r\n"); - } - } - - print_debug_hex32(addr); - print_debug("\r\nDRAM verified\r\n"); -} - - -void ramcheck(unsigned long start, unsigned long stop) -{ - int result; - - - - - - print_debug("Testing DRAM : "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - ram_fill(start, stop); - ram_verify(start, stop); - print_debug("Done.\n"); -} -# 8 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2 - -static void die(const char *str) -{ - print_emerg(str); - do { - hlt(); - } while(1); -} - - - - -static void sdram_set_registers(void) -{ - static const unsigned int register_values[] = { -# 51 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000, - - - - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007, -# 93 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000, -# 145 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00, -# 180 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003, -# 219 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000, -# 249 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000, -# 290 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000, -# 316 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x40) & 0xFF)), 0x001f01fe, 0x00000001, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x44) & 0xFF)), 0x001f01fe, 0x01000001, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x48) & 0xFF)), 0x001f01fe, 0x02000001, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x001f01fe, 0x03000001, - - - - - - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x50) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x54) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x58) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x001f01fe, 0x00000000, -# 351 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x60) & 0xFF)), 0xC01f01ff, 0x00e0fe00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x64) & 0xFF)), 0xC01f01ff, 0x00e0fe00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x68) & 0xFF)), 0xC01f01ff, 0x00e0fe00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xC01f01ff, 0x00e0fe00, - - - - - - - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x70) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x74) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x78) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x7C) & 0xFF)), 0xC01f01ff, 0x00000000, -# 387 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x80) & 0xFF)), 0xffff8888, 0x00000033, -# 456 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x88) & 0xFF)), 0xe8088008, 0x03623125, -# 487 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x8c) & 0xFF)), 0xff8fe08e, 0x00000930, -# 563 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), 0xf0000000, - (4 << 25)|(0 << 24)| - (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| - (1 << 19)|(1 << 18)|(0 << 17)|(0 << 16)| - (2 << 14)|(0 << 13)|(0 << 12)| - (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| - (0 << 3) |(0 << 1) |(0 << 0), -# 635 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x94) & 0xFF)), 0xc180f0f0, 0x0e2b0a05, -# 655 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x98) & 0xFF)), 0xfc00ffff, 0x00000000, -# 689 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x58) & 0xFF)), 0xffe0e0e0, 0x00000000, -# 698 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000003e, 0x00000000, - - - - - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x60) & 0xFF)), 0xffffff00, 0x00000000, - }; - int i; - int max; - print_debug("setting up CPU0 northbridge registers\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - unsigned long reg; - - - - - - - reg = pci_read_config32(register_values[i]); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(register_values[i], reg); - } - print_debug("done.\r\n"); -} -# 743 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" -static void sdram_set_spd_registers(void) -{ - unsigned long dcl; - dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF))); - - dcl &= ~(1<<17); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), dcl); -} - - -static void sdram_enable(void) -{ - unsigned long dcl; - - - dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF))); - print_debug("dcl: "); - print_debug_hex32(dcl); - print_debug("\r\n"); - dcl |= (1<<3); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), dcl); - dcl &= ~(1<<3); - dcl &= ~(1<<0); - dcl &= ~(1<<1); - dcl &= ~(1<<2); - dcl |= (1<<8); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), dcl); - - print_debug("Initializing memory: "); - int loops = 0; - do { - dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF))); - loops += 1; - if ((loops & 1023) == 0) { - print_debug("."); - } - } while(((dcl & (1<<8)) != 0) && (loops < 300000)); - if (loops >= 300000) { - print_debug(" failed\r\n"); - } else { - print_debug(" done\r\n"); - } -# 803 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" -} - -static void sdram_first_normal_reference(void) {} -static void sdram_enable_refresh(void) {} -static void sdram_special_finishup(void) {} - -# 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/sdram/generic_sdram.c" 1 -void sdram_no_memory(void) -{ - print_err("No memory!!\r\n"); - while(1) { - hlt(); - } -} - - -void sdram_initialize(void) -{ - print_debug("Ram1\r\n"); - - sdram_set_registers(); - - print_debug("Ram2\r\n"); - - sdram_set_spd_registers(); - - print_debug("Ram3\r\n"); - - - - - sdram_enable(); - - print_debug("Ram4\r\n"); - sdram_first_normal_reference(); - - print_debug("Ram5\r\n"); - sdram_enable_refresh(); - sdram_special_finishup(); - - print_debug("Ram6\r\n"); -} -# 810 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2 - -static int boot_cpu(void) -{ - volatile unsigned long *local_apic; - unsigned long apic_id; - int bsp; - msr_t msr; - msr = rdmsr(0x1b); - bsp = !!(msr.lo & (1 << 8)); - if (bsp) { - print_debug("Bootstrap cpu\r\n"); - } - - return bsp; -} - -static int cpu_init_detected(void) -{ - unsigned long dcl; - int cpu_init; - - unsigned long htic; - - htic = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6c) & 0xFF))); -# 849 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - cpu_init = (htic & (1<<6)); - if (cpu_init) { - print_debug("CPU INIT Detected.\r\n"); - } - return cpu_init; -} - -static void setup_coherent_ht_domain(void) -{ - static const unsigned int register_values[] = { -# 884 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101, -# 983 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f, -# 1005 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4), -# 1082 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020, -# 1127 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200, -# 1148 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000, -# 1182 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000, - - - - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007, -# 1224 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000, -# 1276 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00, -# 1311 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003, -# 1350 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000, -# 1380 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000, -# 1421 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000, - - }; - int i; - int max; - print_debug("setting up coherent ht domain....\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - unsigned long reg; - - - - - - - reg = pci_read_config32(register_values[i]); - reg &= register_values[i+1]; - reg |= register_values[i+2] & ~register_values[i+1]; - pci_write_config32(register_values[i], reg); - } - print_debug("done.\r\n"); -} - -static void enumerate_ht_chain(void) -{ - unsigned next_unitid, last_unitid;; - next_unitid = 1; - do { - uint32_t id; - uint8_t hdr_type, pos; - last_unitid = next_unitid; - - id = pci_read_config32(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x00) & 0xFF))); - - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - break; - } - hdr_type = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x0e) & 0xFF))); - pos = 0; - hdr_type &= 0x7f; - - if ((hdr_type == 0) || - (hdr_type == 1)) { - pos = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x34) & 0xFF))); - } - while(pos != 0) { - uint8_t cap; - cap = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((pos + 0) & 0xFF))); - if (cap == 0x08) { - uint16_t flags; - flags = pci_read_config16(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((pos + 2) & 0xFF))); - if ((flags >> 13) == 0) { - unsigned count; - flags &= ~0x1f; - flags |= next_unitid & 0x1f; - count = (flags >> 5) & 0x1f; - pci_write_config16(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((pos + 2) & 0xFF)), flags); - next_unitid += count; - break; - } - } - pos = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((pos + 1) & 0xFF))); - } - } while((last_unitid != next_unitid) && (next_unitid <= 0x1f)); -} - -static void print_pci_devices(void) -{ - uint32_t addr; - for(addr = ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0) & 0xFF)); - addr <= ( (((0) & 0xFF) << 16) | (((0x1f) & 0x1f) << 11) | (((0x7) & 0x07) << 8) | ((0) & 0xFF)); - addr += ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0) & 0xFF))) { - uint32_t id; - id = pci_read_config32(addr + 0x00); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug("PCI: 00:"); - print_debug_hex8(addr >> 11); - print_debug_char('.'); - print_debug_hex8((addr >> 8) & 7); - print_debug("\r\n"); - } -} -# 1525 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" -static void enable_smbus(void) -{ - uint32_t addr; - for(addr = ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0) & 0xFF)); - addr <= ( (((0) & 0xFF) << 16) | (((0x1f) & 0x1f) << 11) | (((0x7) & 0x07) << 8) | ((0) & 0xFF)); - addr += ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0) & 0xFF))) { - uint32_t id; - id = pci_read_config32(addr); - if (id == ((0x746b << 16) | (0x1022))) { - break; - } - } - if (addr > ( (((0) & 0xFF) << 16) | (((0x1f) & 0x1f) << 11) | (((0x7) & 0x07) << 8) | ((0) & 0xFF))) { - die("SMBUS controller not found\r\n"); - } - uint8_t enable; - print_debug("SMBus controller enabled\r\n"); - pci_write_config32(addr + 0x58, 0x1000 | 1); - enable = pci_read_config8(addr + 0x41); - pci_write_config8(addr + 0x41, enable | (1 << 7)); -} - - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(void) -{ - unsigned long loops; - loops = (100*1000*10); - do { - unsigned short val; - smbus_delay(); - val = inw(0x1000 + 0xe0); - if ((val & 0x800) == 0) { - break; - } - } while(--loops); - return loops?0:-1; -} - -static int smbus_wait_until_done(void) -{ - unsigned long loops; - loops = (100*1000*10); - do { - unsigned short val; - smbus_delay(); - - val = inw(0x1000 + 0xe0); - if (((val & 0x8) == 0) || ((val & 0x437) != 0)) { - break; - } - } while(--loops); - return loops?0:-1; -} - -static int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char global_control_register; - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready() < 0) { - return -1; - } - - - - outw(inw(0x1000 + 0xe2) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), 0x1000 + 0xe2); - - outw(((device & 0x7f) << 1) | 1, 0x1000 + 0xe4); - - outb(address & 0xFF, 0x1000 + 0xe8); - - outw((inw(0x1000 + 0xe2) & ~7) | (0x2), 0x1000 + 0xe2); - - - - outw(inw(0x1000 + 0xe0), 0x1000 + 0xe0); - - - outw(0, 0x1000 + 0xe6); - - - outw((inw(0x1000 + 0xe2) | (1 << 3)), 0x1000 + 0xe2); - - - - if (smbus_wait_until_done() < 0) { - return -1; - } - - global_status_register = inw(0x1000 + 0xe0); - - - byte = inw(0x1000 + 0xe6) & 0xff; - - if (global_status_register != (1 << 4)) { - return -1; - } - return byte; -} - -static void dump_spd_registers(void) -{ - unsigned device; - device = (0xa << 3); - print_debug("\r\n"); - while(device <= ((0xa << 3) +1)) { - int i; - print_debug("dimm: "); - print_debug_hex8(device); - for(i = 0; i < 256; i++) { - int status; - unsigned char byte; - if ((i & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(i); - print_debug(": "); - } - status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device\r\n"); - continue; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - device += 1; - print_debug("\r\n"); - } -} - -static void dump_spd_registers1(void) -{ - int i; - print_debug("dimm: "); - print_debug_hex8((0xa << 3)); - for(i = 0; i < 256; i++) { - int status; - unsigned char byte; - if ((i & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(i); - print_debug(": "); - } - status = smbus_read_byte((0xa << 3), i); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); -} - - - -static void dump_spd_registers2(void) -{ - unsigned dev; - print_debug("\r\n"); - for(dev = (0xa << 3); dev <= ((0xa << 3) +1); dev += 1) { - print_debug("dimm: "); - print_debug_hex8(dev); - int status; - unsigned char byte; - status = smbus_read_byte(dev, 0); - if (status < 0) { - print_debug("bad device\r\n"); - continue; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug("\r\n"); - } -} - -static void main(void) -{ - uart_init(); - console_init(); - if (boot_cpu() && !cpu_init_detected()) { - setup_coherent_ht_domain(); - enumerate_ht_chain(); - print_pci_devices(); - enable_smbus(); - sdram_initialize(); - - - - dump_spd_registers1(); - dump_spd_registers2(); - - - - - - ram_fill( 0x00000000, 0x00001000); - ram_verify(0x00000000, 0x00001000); - - - - - - } -} diff --git a/util/romcc/tests/raminit_test4.c b/util/romcc/tests/raminit_test4.c deleted file mode 100644 index 0769c93c8f..0000000000 --- a/util/romcc/tests/raminit_test4.c +++ /dev/null @@ -1,1147 +0,0 @@ -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" -# 1 "<built-in>" -# 1 "<command line>" -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" - -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/arch/i386/include/stdint.h" 1 -# 11 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/arch/i386/include/stdint.h" -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - - - - - - - -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - - - - - - - -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - - - - - - - -typedef int intptr_t; -typedef unsigned int uintptr_t; - - - - - - -typedef long int intmax_t; -typedef unsigned long int uintmax_t; -# 3 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/include/device/pci_def.h" 1 -# 4 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/arch/i386/include/arch/romcc_io.h" 1 -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -static void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} - -static void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - - -static unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - - -static unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} - -static unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static void hlt(void) -{ - __builtin_hlt(); -} - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} -# 64 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/arch/i386/include/arch/romcc_io.h" -typedef unsigned device_t; - -static unsigned char pci_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} - -static unsigned short pci_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} - -static unsigned int pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config16(device_t dev, unsigned where, unsigned short value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} - -static void pci_write_config32(device_t dev, unsigned where, unsigned int value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - - -static device_t pci_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= ( (((255) & 0xFF) << 16) | (((31) & 0x1f) << 11) | (((7) & 0x7) << 8)); dev += ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((1) & 0x7) << 8))) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return (0xffffffffU); -} -# 5 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/pc80/serial.c" 1 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/include/part/fallback_boot.h" 1 -# 2 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/pc80/serial.c" 2 -# 44 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/pc80/serial.c" -static int uart_can_tx_byte(void) -{ - return inb(0x3f8 + 0x05) & 0x20; -} - -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -static void uart_wait_until_sent(void) -{ - while(!(inb(0x3f8 + 0x05) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, 0x3f8 + 0x00); - - uart_wait_until_sent(); -} - -static void uart_init(void) -{ - - outb(0x0, 0x3f8 + 0x01); - - outb(0x01, 0x3f8 + 0x02); - - outb(0x80 | 0x3, 0x3f8 + 0x03); -# 87 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/pc80/serial.c" - outb((115200/9600) & 0xFF, 0x3f8 + 0x00); - outb(((115200/9600) >> 8) & 0xFF, 0x3f8 + 0x01); - - outb(0x3, 0x3f8 + 0x03); -} -# 6 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/arch/i386/lib/console.c" 1 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/include/console/loglevel.h" 1 -# 2 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/arch/i386/lib/console.c" 2 - -static void __console_tx_byte(unsigned char byte) -{ - uart_tx_byte(byte); -} - -static void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_byte(digit); -} - -static void __console_tx_char(int loglevel, unsigned char byte) -{ - if (8 > loglevel) { - uart_tx_byte(byte); - } -} - -static void __console_tx_hex8(int loglevel, unsigned char value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_hex16(int loglevel, unsigned short value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_hex32(int loglevel, unsigned int value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 28U) & 0x0fU); - __console_tx_nibble((value >> 24U) & 0x0fU); - __console_tx_nibble((value >> 20U) & 0x0fU); - __console_tx_nibble((value >> 16U) & 0x0fU); - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_string(int loglevel, const char *str) -{ - if (8 > loglevel) { - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_byte(ch); - } - } -} - -static void print_emerg_char(unsigned char byte) { __console_tx_char(0, byte); } -static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(0, value); } -static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(0, value); } -static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(0, value); } -static void print_emerg(const char *str) { __console_tx_string(0, str); } - -static void print_alert_char(unsigned char byte) { __console_tx_char(1, byte); } -static void print_alert_hex8(unsigned char value) { __console_tx_hex8(1, value); } -static void print_alert_hex16(unsigned short value){ __console_tx_hex16(1, value); } -static void print_alert_hex32(unsigned int value) { __console_tx_hex32(1, value); } -static void print_alert(const char *str) { __console_tx_string(1, str); } - -static void print_crit_char(unsigned char byte) { __console_tx_char(2, byte); } -static void print_crit_hex8(unsigned char value) { __console_tx_hex8(2, value); } -static void print_crit_hex16(unsigned short value){ __console_tx_hex16(2, value); } -static void print_crit_hex32(unsigned int value) { __console_tx_hex32(2, value); } -static void print_crit(const char *str) { __console_tx_string(2, str); } - -static void print_err_char(unsigned char byte) { __console_tx_char(3, byte); } -static void print_err_hex8(unsigned char value) { __console_tx_hex8(3, value); } -static void print_err_hex16(unsigned short value){ __console_tx_hex16(3, value); } -static void print_err_hex32(unsigned int value) { __console_tx_hex32(3, value); } -static void print_err(const char *str) { __console_tx_string(3, str); } - -static void print_warning_char(unsigned char byte) { __console_tx_char(4, byte); } -static void print_warning_hex8(unsigned char value) { __console_tx_hex8(4, value); } -static void print_warning_hex16(unsigned short value){ __console_tx_hex16(4, value); } -static void print_warning_hex32(unsigned int value) { __console_tx_hex32(4, value); } -static void print_warning(const char *str) { __console_tx_string(4, str); } - -static void print_notice_char(unsigned char byte) { __console_tx_char(5, byte); } -static void print_notice_hex8(unsigned char value) { __console_tx_hex8(5, value); } -static void print_notice_hex16(unsigned short value){ __console_tx_hex16(5, value); } -static void print_notice_hex32(unsigned int value) { __console_tx_hex32(5, value); } -static void print_notice(const char *str) { __console_tx_string(5, str); } - -static void print_info_char(unsigned char byte) { __console_tx_char(6, byte); } -static void print_info_hex8(unsigned char value) { __console_tx_hex8(6, value); } -static void print_info_hex16(unsigned short value){ __console_tx_hex16(6, value); } -static void print_info_hex32(unsigned int value) { __console_tx_hex32(6, value); } -static void print_info(const char *str) { __console_tx_string(6, str); } - -static void print_debug_char(unsigned char byte) { __console_tx_char(7, byte); } -static void print_debug_hex8(unsigned char value) { __console_tx_hex8(7, value); } -static void print_debug_hex16(unsigned short value){ __console_tx_hex16(7, value); } -static void print_debug_hex32(unsigned int value) { __console_tx_hex32(7, value); } -static void print_debug(const char *str) { __console_tx_string(7, str); } - -static void print_spew_char(unsigned char byte) { __console_tx_char(8, byte); } -static void print_spew_hex8(unsigned char value) { __console_tx_hex8(8, value); } -static void print_spew_hex16(unsigned short value){ __console_tx_hex16(8, value); } -static void print_spew_hex32(unsigned int value) { __console_tx_hex32(8, value); } -static void print_spew(const char *str) { __console_tx_string(8, str); } -# 128 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/arch/i386/lib/console.c" -static void console_init(void) -{ - static const char console_test[] = - "\r\n\r\nLinuxBIOS-" - "1.1.0" - ".0Fallback" - " " - "Fri Jun 13 21:02:41 MDT 2003" - " starting...\r\n"; - print_info(console_test); -} - - -static void die(const char *str) -{ - print_emerg(str); - do { - hlt(); - } while(1); -} -# 7 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/ram/ramtest.c" 1 -static void write_phys(unsigned long addr, unsigned long value) -{ - volatile unsigned long *ptr; - ptr = (void *)addr; - *ptr = value; -} - -static unsigned long read_phys(unsigned long addr) -{ - volatile unsigned long *ptr; - ptr = (void *)addr; - return *ptr; -} - -void ram_fill(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - - - print_debug("DRAM fill: "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - - if ((addr & 0xffff) == 0) { - print_debug_hex32(addr); - print_debug("\r"); - } - write_phys(addr, addr); - }; - - print_debug_hex32(addr); - print_debug("\r\nDRAM filled\r\n"); -} - -void ram_verify(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - - - print_debug("DRAM verify: "); - print_debug_hex32(start); - print_debug_char('-'); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - unsigned long value; - - if ((addr & 0xffff) == 0) { - print_debug_hex32(addr); - print_debug("\r"); - } - value = read_phys(addr); - if (value != addr) { - - print_err_hex32(addr); - print_err_char(':'); - print_err_hex32(value); - print_err("\r\n"); - } - } - - print_debug_hex32(addr); - print_debug("\r\nDRAM verified\r\n"); -} - - -void ram_check(unsigned long start, unsigned long stop) -{ - int result; - - - - - - print_debug("Testing DRAM : "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - ram_fill(start, stop); - ram_verify(start, stop); - print_debug("Done.\n"); -} -# 8 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/early_ht.c" 1 -static void enumerate_ht_chain(void) -{ - - - - - - unsigned next_unitid, last_unitid;; - next_unitid = 1; - do { - uint32_t id; - uint8_t hdr_type, pos; - last_unitid = next_unitid; - - id = pci_read_config32(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), 0x00); - - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - break; - } - hdr_type = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), 0x0e); - pos = 0; - hdr_type &= 0x7f; - - if ((hdr_type == 0) || - (hdr_type == 1)) { - pos = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), 0x34); - } - while(pos != 0) { - uint8_t cap; - cap = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), pos + 0); - if (cap == 0x08) { - uint16_t flags; - flags = pci_read_config16(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), pos + 2); - if ((flags >> 13) == 0) { - unsigned count; - flags &= ~0x1f; - flags |= next_unitid & 0x1f; - count = (flags >> 5) & 0x1f; - pci_write_config16(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), pos + 2, flags); - next_unitid += count; - break; - } - } - pos = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), pos + 1); - } - } while((last_unitid != next_unitid) && (next_unitid <= 0x1f)); -} -# 9 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/southbridge/amd/amd8111/amd8111_early_smbus.c" 1 -# 12 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/southbridge/amd/amd8111/amd8111_early_smbus.c" -static void enable_smbus(void) -{ - device_t dev; - dev = pci_locate_device(((((0x746b) & 0xFFFF) << 16) | ((0x1022) & 0xFFFF)), 0); - if (dev == (0xffffffffU)) { - die("SMBUS controller not found\r\n"); - } - uint8_t enable; - print_debug("SMBus controller enabled\r\n"); - pci_write_config32(dev, 0x58, 0x1000 | 1); - enable = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, enable | (1 << 7)); -} - - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(void) -{ - unsigned long loops; - loops = (100*1000*10); - do { - unsigned short val; - smbus_delay(); - val = inw(0x1000 + 0xe0); - if ((val & 0x800) == 0) { - break; - } - } while(--loops); - return loops?0:-1; -} - -static int smbus_wait_until_done(void) -{ - unsigned long loops; - loops = (100*1000*10); - do { - unsigned short val; - smbus_delay(); - - val = inw(0x1000 + 0xe0); - if (((val & 0x8) == 0) || ((val & 0x437) != 0)) { - break; - } - } while(--loops); - return loops?0:-1; -} - -static int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char global_control_register; - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready() < 0) { - return -1; - } - - - - outw(inw(0x1000 + 0xe2) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), 0x1000 + 0xe2); - - outw(((device & 0x7f) << 1) | 1, 0x1000 + 0xe4); - - outb(address & 0xFF, 0x1000 + 0xe8); - - outw((inw(0x1000 + 0xe2) & ~7) | (0x2), 0x1000 + 0xe2); - - - - outw(inw(0x1000 + 0xe0), 0x1000 + 0xe0); - - - outw(0, 0x1000 + 0xe6); - - - outw((inw(0x1000 + 0xe2) | (1 << 3)), 0x1000 + 0xe2); - - - - if (smbus_wait_until_done() < 0) { - return -1; - } - - global_status_register = inw(0x1000 + 0xe0); - - - byte = inw(0x1000 + 0xe6) & 0xff; - - if (global_status_register != (1 << 4)) { - return -1; - } - return byte; -} -# 10 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" 1 -# 10 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" -static void setup_resource_map(const unsigned int *register_values, int max) -{ - int i; - print_debug("setting up resource map....\r\n"); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - - - - - - - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - - - - - - - } - print_debug("done.\r\n"); -} - -static void setup_default_resource_map(void) -{ - static const unsigned int register_values[] = { -# 70 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007, -# 108 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00000000, -# 149 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00000000, -# 184 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00000000, -# 218 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x01fff000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000, -# 248 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000, -# 289 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000, - }; - int max; - max = sizeof(register_values)/sizeof(register_values[0]); - setup_resource_map(register_values, max); -} - -static void sdram_set_registers(void) -{ - static const unsigned int register_values[] = { -# 339 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x007f0001, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007, -# 378 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003, -# 398 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00800000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00800000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00800000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00800000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00800000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00800000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00800000, -# 451 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00fe2f00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00fec000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x0000b000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00000000, -# 503 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00fc0003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00fec00e, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000a03, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00000000, -# 545 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x01fff000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000, -# 583 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x00000033, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000, -# 632 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000, -# 659 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x40) & 0xFF)), 0x001f01fe, 0x00000001, -# 671 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x44) & 0xFF)), 0x001f01fe, 0x00001001, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x48) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x001f01fe, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x50) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x54) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x58) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x001f01fe, 0x00000000, -# 711 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x60) & 0xFF)), 0xC01f01ff, 0x03e0ee00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x64) & 0xFF)), 0xC01f01ff, 0x03e0ee00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x68) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xC01f01ff, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x70) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x74) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x78) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x7C) & 0xFF)), 0xC01f01ff, 0x00000000, -# 747 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x80) & 0xFF)), 0xffff8888, 0x00000003, -# 817 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x88) & 0xFF)), 0xe8088008, 0x13723335, -# 855 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x8c) & 0xFF)), 0xff8fe08e, 0x00100a20, -# 937 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), 0xf0000000, - (4 << 25)|(0 << 24)| - (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| - (0 << 19)|(0 << 18)|(0 << 17)|(1 << 16)| - (2 << 14)|(0 << 13)|(0 << 12)| - (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| - (0 << 3) |(0 << 1) |(0 << 0), -# 1016 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x94) & 0xFF)), 0xc180f0f0, 0x065b0b08, -# 1033 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x98) & 0xFF)), 0xfc00ffff, 0x00000000, -# 1067 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x58) & 0xFF)), 0xffe0e0e0, 0x00000000, -# 1076 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000003e, 0x00000000, - - - - - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x60) & 0xFF)), 0xffffff00, 0x00000000, - }; - int i; - int max; - print_debug("setting up CPU0 northbridge registers\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - - - - - - - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - - - - - - - - } - print_debug("done.\r\n"); -} -# 1132 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" -static void sdram_set_spd_registers(void) -{ - unsigned long dcl; - dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90); - - dcl &= ~(1<<17); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90, dcl); -} - - -static void sdram_enable(void) -{ - unsigned long dcl; - - - dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90); - print_debug("dcl: "); - print_debug_hex32(dcl); - print_debug("\r\n"); - dcl |= (1<<3); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90, dcl); - dcl &= ~(1<<3); - dcl &= ~(1<<0); - dcl &= ~(1<<1); - dcl &= ~(1<<2); - dcl |= (1<<8); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90, dcl); - - print_debug("Initializing memory: "); - int loops = 0; - do { - dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90); - loops += 1; - if ((loops & 1023) == 0) { - print_debug("."); - } - } while(((dcl & (1<<8)) != 0) && (loops < 300000)); - if (loops >= 300000) { - print_debug(" failed\r\n"); - } else { - print_debug(" done\r\n"); - } -# 1192 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c" -} - -static void sdram_first_normal_reference(void) {} -static void sdram_enable_refresh(void) {} -static void sdram_special_finishup(void) {} -# 11 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/coherent_ht.c" 1 -# 9 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/coherent_ht.c" -static void setup_coherent_ht_domain(void) -{ - static const unsigned int register_values[] = { -# 37 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/coherent_ht.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101, -# 136 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/coherent_ht.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f, -# 158 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/coherent_ht.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4), -# 235 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/coherent_ht.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020, -# 280 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/coherent_ht.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200, -# 301 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/coherent_ht.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000, - - - - - - }; - int i; - int max; - print_debug("setting up coherent ht domain....\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - - - - - - - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - - - - - - - } - print_debug("done.\r\n"); -} -# 12 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 -# 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/sdram/generic_sdram.c" 1 -void sdram_no_memory(void) -{ - print_err("No memory!!\r\n"); - while(1) { - hlt(); - } -} - - -void sdram_initialize(void) -{ - print_debug("Ram1\r\n"); - - sdram_set_registers(); - - print_debug("Ram2\r\n"); - - sdram_set_spd_registers(); - - print_debug("Ram3\r\n"); - - - - - sdram_enable(); - - print_debug("Ram4\r\n"); - sdram_first_normal_reference(); - - print_debug("Ram5\r\n"); - sdram_enable_refresh(); - sdram_special_finishup(); - - print_debug("Ram6\r\n"); -} -# 13 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2 - -static int boot_cpu(void) -{ - volatile unsigned long *local_apic; - unsigned long apic_id; - int bsp; - msr_t msr; - msr = rdmsr(0x1b); - bsp = !!(msr.lo & (1 << 8)); - if (bsp) { - print_debug("Bootstrap cpu\r\n"); - } - - return bsp; -} - -static int cpu_init_detected(void) -{ - unsigned long dcl; - int cpu_init; - - unsigned long htic; - - htic = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x7) << 8)), 0x6c); -# 52 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" - cpu_init = (htic & (1<<6)); - if (cpu_init) { - print_debug("CPU INIT Detected.\r\n"); - } - return cpu_init; -} - - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)); - dev <= ( (((0) & 0xFF) << 16) | (((0x1f) & 0x1f) << 11) | (((0x7) & 0x7) << 8)); - dev += ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((1) & 0x7) << 8))) { - uint32_t id; - id = pci_read_config32(dev, 0x00); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug("PCI: 00:"); - print_debug_hex8(dev >> 11); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); - print_debug("\r\n"); - } -} - - -static void dump_spd_registers(void) -{ - unsigned device; - device = (0xa << 3); - print_debug("\r\n"); - while(device <= ((0xa << 3) +7)) { - int i; - print_debug("dimm: "); - print_debug_hex8(device); - for(i = 0; i < 256; i++) { - int status; - unsigned char byte; - if ((i & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(i); - print_debug(": "); - } - status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - device += 1; - print_debug("\r\n"); - } -} - -static void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg) -{ - outb(reg, port); - outb(value, port +1); -} - -static unsigned char pnp_read_config(unsigned char port, unsigned char reg) -{ - outb(reg, port); - return inb(port +1); -} - -static void pnp_set_logical_device(unsigned char port, int device) -{ - pnp_write_config(port, device, 0x07); -} - -static void pnp_set_enable(unsigned char port, int enable) -{ - pnp_write_config(port, enable?0x1:0x0, 0x30); -} - -static int pnp_read_enable(unsigned char port) -{ - return !!pnp_read_config(port, 0x30); -} - -static void pnp_set_iobase0(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x60); - pnp_write_config(port, iobase & 0xff, 0x61); -} - -static void pnp_set_iobase1(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x62); - pnp_write_config(port, iobase & 0xff, 0x63); -} - -static void pnp_set_irq0(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x70); -} - -static void pnp_set_irq1(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x72); -} - -static void pnp_set_drq(unsigned char port, unsigned drq) -{ - pnp_write_config(port, drq & 0xff, 0x74); -} -# 179 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" -static void pc87360_enable_serial(void) -{ - pnp_set_logical_device(0x2e, 0x03); - pnp_set_enable(0x2e, 1); - pnp_set_iobase0(0x2e, 0x3f8); -} - -static void main(void) -{ - pc87360_enable_serial(); - uart_init(); - console_init(); - if (boot_cpu() && !cpu_init_detected()) { - setup_coherent_ht_domain(); - enumerate_ht_chain(); - print_pci_devices(); - enable_smbus(); - sdram_initialize(); - - dump_spd_registers(); - - ram_check(0x00000000, 0x00001000); - ram_check(0x00000000, 0x00180000); - } -} diff --git a/util/romcc/tests/raminit_test5.c b/util/romcc/tests/raminit_test5.c deleted file mode 100644 index f386a75ebf..0000000000 --- a/util/romcc/tests/raminit_test5.c +++ /dev/null @@ -1,1392 +0,0 @@ - - - - - - - -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - - - - - - - -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - - - - - - - -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - - - - - - - -typedef int intptr_t; -typedef unsigned int uintptr_t; - - - - - - -typedef long int intmax_t; -typedef unsigned long int uintmax_t; - - - - -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -static void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} - -static void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - - -static unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - - -static unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} - -static unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static void hlt(void) -{ - __builtin_hlt(); -} - -int log2(int value) -{ - - - - - - - return __builtin_bsr(value); -} - - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} - -typedef unsigned device_t; - -static unsigned char pci_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} - -static unsigned short pci_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} - -static unsigned int pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config16(device_t dev, unsigned where, unsigned short value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} - -static void pci_write_config32(device_t dev, unsigned where, unsigned int value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - - -static device_t pci_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= ( (((255) & 0xFF) << 16) | (((31) & 0x1f) << 11) | (((7) & 0x7) << 8)); dev += ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((1) & 0x7) << 8))) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return (0xffffffffU); -} - - - - - -static int uart_can_tx_byte(void) -{ - return inb(0x3f8 + 0x05) & 0x20; -} - -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -static void uart_wait_until_sent(void) -{ - while(!(inb(0x3f8 + 0x05) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, 0x3f8 + 0x00); - - uart_wait_until_sent(); -} - -static void uart_init(void) -{ - - outb(0x0, 0x3f8 + 0x01); - - outb(0x01, 0x3f8 + 0x02); - - outb(0x80 | 0x3, 0x3f8 + 0x03); - - outb((115200/115200) & 0xFF, 0x3f8 + 0x00); - outb(((115200/115200) >> 8) & 0xFF, 0x3f8 + 0x01); - - outb(0x3, 0x3f8 + 0x03); -} - - - - - -static void __console_tx_byte(unsigned char byte) -{ - uart_tx_byte(byte); -} - -static void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_byte(digit); -} - -static void __console_tx_char(int loglevel, unsigned char byte) -{ - if (8 > loglevel) { - uart_tx_byte(byte); - } -} - -static void __console_tx_hex8(int loglevel, unsigned char value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_hex16(int loglevel, unsigned short value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_hex32(int loglevel, unsigned int value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 28U) & 0x0fU); - __console_tx_nibble((value >> 24U) & 0x0fU); - __console_tx_nibble((value >> 20U) & 0x0fU); - __console_tx_nibble((value >> 16U) & 0x0fU); - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_string(int loglevel, const char *str) -{ - if (8 > loglevel) { - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_byte(ch); - } - } -} - -static void print_emerg_char(unsigned char byte) { __console_tx_char(0, byte); } -static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(0, value); } -static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(0, value); } -static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(0, value); } -static void print_emerg(const char *str) { __console_tx_string(0, str); } - -static void print_alert_char(unsigned char byte) { __console_tx_char(1, byte); } -static void print_alert_hex8(unsigned char value) { __console_tx_hex8(1, value); } -static void print_alert_hex16(unsigned short value){ __console_tx_hex16(1, value); } -static void print_alert_hex32(unsigned int value) { __console_tx_hex32(1, value); } -static void print_alert(const char *str) { __console_tx_string(1, str); } - -static void print_crit_char(unsigned char byte) { __console_tx_char(2, byte); } -static void print_crit_hex8(unsigned char value) { __console_tx_hex8(2, value); } -static void print_crit_hex16(unsigned short value){ __console_tx_hex16(2, value); } -static void print_crit_hex32(unsigned int value) { __console_tx_hex32(2, value); } -static void print_crit(const char *str) { __console_tx_string(2, str); } - -static void print_err_char(unsigned char byte) { __console_tx_char(3, byte); } -static void print_err_hex8(unsigned char value) { __console_tx_hex8(3, value); } -static void print_err_hex16(unsigned short value){ __console_tx_hex16(3, value); } -static void print_err_hex32(unsigned int value) { __console_tx_hex32(3, value); } -static void print_err(const char *str) { __console_tx_string(3, str); } - -static void print_warning_char(unsigned char byte) { __console_tx_char(4, byte); } -static void print_warning_hex8(unsigned char value) { __console_tx_hex8(4, value); } -static void print_warning_hex16(unsigned short value){ __console_tx_hex16(4, value); } -static void print_warning_hex32(unsigned int value) { __console_tx_hex32(4, value); } -static void print_warning(const char *str) { __console_tx_string(4, str); } - -static void print_notice_char(unsigned char byte) { __console_tx_char(5, byte); } -static void print_notice_hex8(unsigned char value) { __console_tx_hex8(5, value); } -static void print_notice_hex16(unsigned short value){ __console_tx_hex16(5, value); } -static void print_notice_hex32(unsigned int value) { __console_tx_hex32(5, value); } -static void print_notice(const char *str) { __console_tx_string(5, str); } - -static void print_info_char(unsigned char byte) { __console_tx_char(6, byte); } -static void print_info_hex8(unsigned char value) { __console_tx_hex8(6, value); } -static void print_info_hex16(unsigned short value){ __console_tx_hex16(6, value); } -static void print_info_hex32(unsigned int value) { __console_tx_hex32(6, value); } -static void print_info(const char *str) { __console_tx_string(6, str); } - -static void print_debug_char(unsigned char byte) { __console_tx_char(7, byte); } -static void print_debug_hex8(unsigned char value) { __console_tx_hex8(7, value); } -static void print_debug_hex16(unsigned short value){ __console_tx_hex16(7, value); } -static void print_debug_hex32(unsigned int value) { __console_tx_hex32(7, value); } -static void print_debug(const char *str) { __console_tx_string(7, str); } - -static void print_spew_char(unsigned char byte) { __console_tx_char(8, byte); } -static void print_spew_hex8(unsigned char value) { __console_tx_hex8(8, value); } -static void print_spew_hex16(unsigned short value){ __console_tx_hex16(8, value); } -static void print_spew_hex32(unsigned int value) { __console_tx_hex32(8, value); } -static void print_spew(const char *str) { __console_tx_string(8, str); } - -static void console_init(void) -{ - static const char console_test[] = - "\r\n\r\nLinuxBIOS-" - "1.1.0" - ".0Fallback" - " " - "Thu Jun 19 05:42:16 MDT 2003" - " starting...\r\n"; - print_info(console_test); -} - - -static void die(const char *str) -{ - print_emerg(str); - do { - hlt(); - } while(1); -} - - - - - - - - - -static void write_phys(unsigned long addr, unsigned long value) -{ - - asm volatile( - "movnti %1, (%0)" - : - : "r" (addr), "r" (value) - : - ); - - - - - -} - -static unsigned long read_phys(unsigned long addr) -{ - volatile unsigned long *ptr; - ptr = (void *)addr; - return *ptr; -} - -static void ram_fill(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - - - print_debug("DRAM fill: "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - - if (!(addr & 0xffff)) { - print_debug_hex32(addr); - print_debug("\r"); - } - write_phys(addr, addr); - }; - - print_debug_hex32(addr); - print_debug("\r\nDRAM filled\r\n"); -} - -static void ram_verify(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - - - print_debug("DRAM verify: "); - print_debug_hex32(start); - print_debug_char('-'); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - unsigned long value; - - if (!(addr & 0xffff)) { - print_debug_hex32(addr); - print_debug("\r"); - } - value = read_phys(addr); - if (value != addr) { - - print_err_hex32(addr); - print_err_char(':'); - print_err_hex32(value); - print_err("\r\n"); - } - } - - print_debug_hex32(addr); - print_debug("\r\nDRAM verified\r\n"); -} - - -void ram_check(unsigned long start, unsigned long stop) -{ - int result; - - - - - - print_debug("Testing DRAM : "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - ram_fill(start, stop); - ram_verify(start, stop); - print_debug("Done.\n"); -} - - -static void enumerate_ht_chain(void) -{ - - - - - - unsigned next_unitid, last_unitid;; - next_unitid = 1; - do { - uint32_t id; - uint8_t hdr_type, pos; - last_unitid = next_unitid; - - id = pci_read_config32(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), 0x00); - - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - break; - } - hdr_type = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), 0x0e); - pos = 0; - hdr_type &= 0x7f; - - if ((hdr_type == 0) || - (hdr_type == 1)) { - pos = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), 0x34); - } - while(pos != 0) { - uint8_t cap; - cap = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), pos + 0); - if (cap == 0x08) { - uint16_t flags; - flags = pci_read_config16(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), pos + 2); - if ((flags >> 13) == 0) { - unsigned count; - flags &= ~0x1f; - flags |= next_unitid & 0x1f; - count = (flags >> 5) & 0x1f; - pci_write_config16(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), pos + 2, flags); - next_unitid += count; - break; - } - } - pos = pci_read_config8(( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)), pos + 1); - } - } while((last_unitid != next_unitid) && (next_unitid <= 0x1f)); -} - - - -static void enable_smbus(void) -{ - device_t dev; - dev = pci_locate_device(((((0x746b) & 0xFFFF) << 16) | ((0x1022) & 0xFFFF)), 0); - if (dev == (0xffffffffU)) { - die("SMBUS controller not found\r\n"); - } - uint8_t enable; - print_debug("SMBus controller enabled\r\n"); - pci_write_config32(dev, 0x58, 0x1000 | 1); - enable = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, enable | (1 << 7)); -} - - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(void) -{ - unsigned long loops; - loops = (100*1000*10); - do { - unsigned short val; - smbus_delay(); - val = inw(0x1000 + 0xe0); - if ((val & 0x800) == 0) { - break; - } - } while(--loops); - return loops?0:-1; -} - -static int smbus_wait_until_done(void) -{ - unsigned long loops; - loops = (100*1000*10); - do { - unsigned short val; - smbus_delay(); - - val = inw(0x1000 + 0xe0); - if (((val & 0x8) == 0) | ((val & 0x437) != 0)) { - break; - } - } while(--loops); - return loops?0:-1; -} - -static int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char global_control_register; - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready() < 0) { - return -1; - } - - - - outw(inw(0x1000 + 0xe2) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), 0x1000 + 0xe2); - - outw(((device & 0x7f) << 1) | 1, 0x1000 + 0xe4); - - outb(address & 0xFF, 0x1000 + 0xe8); - - outw((inw(0x1000 + 0xe2) & ~7) | (0x2), 0x1000 + 0xe2); - - - - outw(inw(0x1000 + 0xe0), 0x1000 + 0xe0); - - - outw(0, 0x1000 + 0xe6); - - - outw((inw(0x1000 + 0xe2) | (1 << 3)), 0x1000 + 0xe2); - - - - if (smbus_wait_until_done() < 0) { - return -1; - } - - global_status_register = inw(0x1000 + 0xe0); - - - byte = inw(0x1000 + 0xe6) & 0xff; - - if (global_status_register != (1 << 4)) { - return -1; - } - return byte; -} - - - - - - - - - - - - - - - -static void setup_resource_map(const unsigned int *register_values, int max) -{ - int i; - print_debug("setting up resource map....\r\n"); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - - - - - - - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - - - - - - - } - print_debug("done.\r\n"); -} - -static void setup_default_resource_map(void) -{ - static const unsigned int register_values[] = { - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x01fff000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000, - }; - int max; - max = sizeof(register_values)/sizeof(register_values[0]); - setup_resource_map(register_values, max); -} - -static void sdram_set_registers(void) -{ - static const unsigned int register_values[] = { - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03, - - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x40) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x44) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x48) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x001f01fe, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x50) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x54) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x58) & 0xFF)), 0x001f01fe, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x001f01fe, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x60) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x64) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x68) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xC01f01ff, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x70) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x74) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x78) & 0xFF)), 0xC01f01ff, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x7C) & 0xFF)), 0xC01f01ff, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x80) & 0xFF)), 0xffff8888, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x88) & 0xFF)), 0xe8088008, 0x03623125, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x8c) & 0xFF)), 0xff8fe08e, 0x00000930, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), 0xf0000000, - (4 << 25)|(0 << 24)| - (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| - (1 << 19)|(1 << 18)|(0 << 17)|(0 << 16)| - (2 << 14)|(0 << 13)|(0 << 12)| - (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| - (0 << 3) |(0 << 1) |(0 << 0), - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x94) & 0xFF)), 0xc180f0f0, 0x0e2b0a05, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x98) & 0xFF)), 0xfc00ffff, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x58) & 0xFF)), 0xffe0e0e0, 0x00000000, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000003e, 0x00000000, - - - - - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) | ((0x60) & 0xFF)), 0xffffff00, 0x00000000, - }; - int i; - int max; - print_debug("setting up CPU0 northbridge registers\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - - - - - - - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - - - - - - - - } - print_debug("done.\r\n"); -} - - -struct dimm_size { - unsigned long side1; - unsigned long side2; -}; -static struct dimm_size spd_get_dimm_size(unsigned device) -{ - - struct dimm_size sz; - int value, low; - sz.side1 = 0; - sz.side2 = 0; - - - - - - value = smbus_read_byte(device, 3); - if (value < 0) return sz; - sz.side1 += value & 0xf; - - value = smbus_read_byte(device, 4); - if (value < 0) return sz; - sz.side1 += value & 0xf; - - value = smbus_read_byte(device, 17); - if (value < 0) return sz; - sz.side1 += log2(value & 0xff); - - - value = smbus_read_byte(device, 7); - if (value < 0) return sz; - value &= 0xff; - value <<= 8; - - low = smbus_read_byte(device, 6); - if (low < 0) return sz; - value = value | (low & 0xff); - sz.side1 += log2(value); - - - value = smbus_read_byte(device, 5); - if (value <= 1) return sz; - - - sz.side2 = sz.side1; - - value = smbus_read_byte(device, 3); - if (value < 0) return sz; - if ((value & 0xf0) == 0) return sz; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); - - value = smbus_read_byte(device, 4); - if (value < 0) return sz; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); - return sz; -} - -static unsigned spd_to_dimm(unsigned device) -{ - return (device - (0xa << 3)); -} - -static void set_dimm_size(struct dimm_size sz, unsigned index) -{ - uint32_t base0, base1, map; - - - print_debug("set_dimm_size: ("); - print_debug_hex32(sz.side1); - print_debug_char(','); - print_debug_hex32(sz.side2); - print_debug_char(','); - print_debug_hex32(index); - print_debug(")\r\n"); - - if (sz.side1 != sz.side2) { - sz.side2 = 0; - } - map = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x80); - map &= ~(0xf << (index + 4)); - - - - - - - - base0 = base1 = 0; - - - if (sz.side1 >= (25 + 3)) { - base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1; - map |= (sz.side1 - (25 + 3)) << (index *4); - } - - - if (sz.side2 >= (25 + 3)) { - base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1; - } - - - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x40 + (((index << 1)+0)<<2), base0); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x40 + (((index << 1)+1)<<2), base1); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x80, map); -} - -static void spd_set_ram_size(void) -{ - unsigned device; - for(device = (0xa << 3); - device <= ((0xa << 3) +1); - device += 1) - { - struct dimm_size sz; - sz = spd_get_dimm_size(device); - set_dimm_size(sz, spd_to_dimm(device)); - } -} - -static void set_top_mem(unsigned tom_k) -{ - - if (!tom_k) { - die("No memory"); - } - - msr_t msr; - msr.lo = (tom_k & 0x003fffff) << 10; - msr.hi = (tom_k & 0xffc00000) >> 22; - wrmsr(0xC001001A, msr); - - - - - - - -} - -static void order_dimms(void) -{ - unsigned long tom; - unsigned mask; - unsigned index; - - - tom = 0; - for(;;) { - - unsigned canidate; - uint32_t csbase, csmask; - unsigned size; - csbase = 0; - canidate = 0; - for(index = 0; index < 8; index++) { - uint32_t value; - value = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x40 + (index << 2)); - - - if (!(value & 1)) { - continue; - } - - - if (value <= csbase) { - continue; - } - - - if (tom & (1 << (index + 24))) { - continue; - } - - csbase = value; - canidate = index; - } - - if (csbase == 0) { - break; - } - - - tom |= (1 << (canidate + 24)); - - - size = csbase >> 21; - - - csbase = (tom << 21) | 1; - - - tom += size; - - - csmask = ((size -1) << 21); - csmask |= 0xfe00; - - - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x40 + (canidate << 2), csbase); - - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x60 + (canidate << 2), csmask); - - } - set_top_mem((tom & ~0xff000000) << 15); -} - -static void spd_set_dram_timing(void) -{ - -} - -static void spd_set_ecc_mode(void) -{ - unsigned long dcl; - dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90); - - dcl &= ~(1<<17); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90, dcl); - -} -static void sdram_set_spd_registers(void) -{ - spd_set_ram_size(); - spd_set_dram_timing(); - spd_set_ecc_mode(); - order_dimms(); -} - - -static void sdram_enable(void) -{ - unsigned long dcl; - - - dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90); - print_debug("dcl: "); - print_debug_hex32(dcl); - print_debug("\r\n"); - dcl |= (1<<3); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90, dcl); - dcl &= ~(1<<3); - dcl &= ~(1<<0); - dcl &= ~(1<<1); - dcl &= ~(1<<2); - dcl |= (1<<8); - pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90, dcl); - - print_debug("Initializing memory: "); - int loops = 0; - do { - dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90); - loops += 1; - if ((loops & 1023) == 0) { - print_debug("."); - } - } while(((dcl & (1<<8)) != 0) && (loops < 300000)); - if (loops >= 300000) { - print_debug(" failed\r\n"); - } else { - print_debug(" done\r\n"); - } - -} - -static void sdram_first_normal_reference(void) {} -static void sdram_enable_refresh(void) {} -static void sdram_special_finishup(void) {} - - -static void setup_coherent_ht_domain(void) -{ - static const unsigned int register_values[] = { - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4), - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000, - - - - - - }; - int i; - int max; - print_debug("setting up coherent ht domain....\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - - - - - - - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - - - - - - - } - print_debug("done.\r\n"); -} - - -void sdram_no_memory(void) -{ - print_err("No memory!!\r\n"); - while(1) { - hlt(); - } -} - - -void sdram_initialize(void) -{ - print_debug("Ram1\r\n"); - - sdram_set_registers(); - - print_debug("Ram2\r\n"); - - sdram_set_spd_registers(); - - print_debug("Ram3\r\n"); - - - - - sdram_enable(); - - print_debug("Ram4\r\n"); - sdram_first_normal_reference(); - - print_debug("Ram5\r\n"); - sdram_enable_refresh(); - sdram_special_finishup(); - - print_debug("Ram6\r\n"); -} - - -static int boot_cpu(void) -{ - volatile unsigned long *local_apic; - unsigned long apic_id; - int bsp; - msr_t msr; - msr = rdmsr(0x1b); - bsp = !!(msr.lo & (1 << 8)); - if (bsp) { - print_debug("Bootstrap processor\r\n"); - } else { - print_debug("Application processor\r\n"); - } - - return bsp; -} - -static int cpu_init_detected(void) -{ - unsigned long dcl; - int cpu_init; - - unsigned long htic; - - htic = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x7) << 8)), 0x6c); - - cpu_init = (htic & (1<<6)); - if (cpu_init) { - print_debug("CPU INIT Detected.\r\n"); - } - return cpu_init; -} - - -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((0) & 0x7) << 8)); - dev <= ( (((0) & 0xFF) << 16) | (((0x1f) & 0x1f) << 11) | (((0x7) & 0x7) << 8)); - dev += ( (((0) & 0xFF) << 16) | (((0) & 0x1f) << 11) | (((1) & 0x7) << 8))) { - uint32_t id; - id = pci_read_config32(dev, 0x00); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\r\n"); - } -} - - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\r\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } -} - -static void dump_spd_registers(void) -{ - unsigned device; - device = (0xa << 3); - print_debug("\r\n"); - while(device <= ((0xa << 3) +1)) { - int i; - print_debug("dimm: "); - print_debug_hex8(device); - for(i = 0; i < 256; i++) { - int status; - unsigned char byte; - if ((i & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(i); - print_debug(": "); - } - status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - device += 1; - print_debug("\r\n"); - } -} - - -static void main(void) -{ - uart_init(); - console_init(); - - - - - - - - if (boot_cpu() && !cpu_init_detected()) { - setup_default_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(); - print_pci_devices(); - enable_smbus(); - sdram_initialize(); - - dump_spd_registers(); - dump_pci_device(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8))); - - - msr_t msr; - msr = rdmsr(0xC001001A); - print_debug("TOP_MEM: "); - print_debug_hex32(msr.hi); - print_debug_hex32(msr.lo); - print_debug("\r\n"); - ram_check(0x00000000, msr.lo); - } -} diff --git a/util/romcc/tests/raminit_test6.c b/util/romcc/tests/raminit_test6.c deleted file mode 100644 index 8048dcee89..0000000000 --- a/util/romcc/tests/raminit_test6.c +++ /dev/null @@ -1,2800 +0,0 @@ -typedef unsigned char uint8_t; -typedef signed char int8_t; -typedef unsigned short uint16_t; -typedef signed short int16_t; -typedef unsigned int uint32_t; -typedef signed int int32_t; - -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -typedef int intptr_t; -typedef unsigned int uintptr_t; - -typedef long int intmax_t; -typedef unsigned long int uintmax_t; - -static inline unsigned long apic_read(unsigned long reg) -{ - return *((volatile unsigned long *)(0xfee00000 +reg)); -} -static inline void apic_write(unsigned long reg, unsigned long v) -{ - *((volatile unsigned long *)(0xfee00000 +reg)) = v; -} -static inline void apic_wait_icr_idle(void) -{ - do { } while ( apic_read( 0x300 ) & 0x01000 ); -} - -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} -static void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} -static void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} -static unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} -static unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} -static unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} -static inline void outsb(uint16_t port, const void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; outsb " - : "=S" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void outsw(uint16_t port, const void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; outsw " - : "=S" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void outsl(uint16_t port, const void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; outsl " - : "=S" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void insb(uint16_t port, void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; insb " - : "=D" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void insw(uint16_t port, void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; insw " - : "=D" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void insl(uint16_t port, void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; insl " - : "=D" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg) -{ - outb(reg, port); - outb(value, port +1); -} -static inline unsigned char pnp_read_config(unsigned char port, unsigned char reg) -{ - outb(reg, port); - return inb(port +1); -} -static inline void pnp_set_logical_device(unsigned char port, int device) -{ - pnp_write_config(port, device, 0x07); -} -static inline void pnp_set_enable(unsigned char port, int enable) -{ - pnp_write_config(port, enable?0x1:0x0, 0x30); -} -static inline int pnp_read_enable(unsigned char port) -{ - return !!pnp_read_config(port, 0x30); -} -static inline void pnp_set_iobase0(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x60); - pnp_write_config(port, iobase & 0xff, 0x61); -} -static inline void pnp_set_iobase1(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x62); - pnp_write_config(port, iobase & 0xff, 0x63); -} -static inline void pnp_set_irq0(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x70); -} -static inline void pnp_set_irq1(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x72); -} -static inline void pnp_set_drq(unsigned char port, unsigned drq) -{ - pnp_write_config(port, drq & 0xff, 0x74); -} -static void hlt(void) -{ - __builtin_hlt(); -} -typedef __builtin_div_t div_t; -typedef __builtin_ldiv_t ldiv_t; -typedef __builtin_udiv_t udiv_t; -typedef __builtin_uldiv_t uldiv_t; -static div_t div(int numer, int denom) -{ - return __builtin_div(numer, denom); -} -static ldiv_t ldiv(long numer, long denom) -{ - return __builtin_ldiv(numer, denom); -} -static udiv_t udiv(unsigned numer, unsigned denom) -{ - return __builtin_udiv(numer, denom); -} -static uldiv_t uldiv(unsigned long numer, unsigned long denom) -{ - return __builtin_uldiv(numer, denom); -} -int log2(int value) -{ - - return __builtin_bsr(value); -} -typedef unsigned device_t; -static unsigned char pci_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} -static unsigned short pci_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} -static unsigned int pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} -static void pci_write_config16(device_t dev, unsigned where, unsigned short value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} -static void pci_write_config32(device_t dev, unsigned where, unsigned int value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} -static device_t pci_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= ( ((( 255 ) & 0xFF) << 16) | ((( 31 ) & 0x1f) << 11) | ((( 7 ) & 0x7) << 8)) ; dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return (0xffffffffU) ; -} - - - - - -static int uart_can_tx_byte(void) -{ - return inb(1016 + 0x05 ) & 0x20; -} -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} -static void uart_wait_until_sent(void) -{ - while(!(inb(1016 + 0x05 ) & 0x40)) - ; -} -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, 1016 + 0x00 ); - - uart_wait_until_sent(); -} -static void uart_init(void) -{ - - outb(0x0, 1016 + 0x01 ); - - outb(0x01, 1016 + 0x02 ); - - outb(0x80 | 3 , 1016 + 0x03 ); - outb((115200/ 115200 ) & 0xFF, 1016 + 0x00 ); - outb(((115200/ 115200 ) >> 8) & 0xFF, 1016 + 0x01 ); - outb(3 , 1016 + 0x03 ); -} - -static void __console_tx_byte(unsigned char byte) -{ - uart_tx_byte(byte); -} -static void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_byte(digit); -} -static void __console_tx_char(int loglevel, unsigned char byte) -{ - if (8 > loglevel) { - uart_tx_byte(byte); - } -} -static void __console_tx_hex8(int loglevel, unsigned char value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} -static void __console_tx_hex16(int loglevel, unsigned short value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} -static void __console_tx_hex32(int loglevel, unsigned int value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 28U) & 0x0fU); - __console_tx_nibble((value >> 24U) & 0x0fU); - __console_tx_nibble((value >> 20U) & 0x0fU); - __console_tx_nibble((value >> 16U) & 0x0fU); - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} -static void __console_tx_string(int loglevel, const char *str) -{ - if (8 > loglevel) { - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_byte(ch); - } - } -} -static void print_emerg_char(unsigned char byte) { __console_tx_char(0 , byte); } -static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(0 , value); } -static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(0 , value); } -static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(0 , value); } -static void print_emerg(const char *str) { __console_tx_string(0 , str); } -static void print_alert_char(unsigned char byte) { __console_tx_char(1 , byte); } -static void print_alert_hex8(unsigned char value) { __console_tx_hex8(1 , value); } -static void print_alert_hex16(unsigned short value){ __console_tx_hex16(1 , value); } -static void print_alert_hex32(unsigned int value) { __console_tx_hex32(1 , value); } -static void print_alert(const char *str) { __console_tx_string(1 , str); } -static void print_crit_char(unsigned char byte) { __console_tx_char(2 , byte); } -static void print_crit_hex8(unsigned char value) { __console_tx_hex8(2 , value); } -static void print_crit_hex16(unsigned short value){ __console_tx_hex16(2 , value); } -static void print_crit_hex32(unsigned int value) { __console_tx_hex32(2 , value); } -static void print_crit(const char *str) { __console_tx_string(2 , str); } -static void print_err_char(unsigned char byte) { __console_tx_char(3 , byte); } -static void print_err_hex8(unsigned char value) { __console_tx_hex8(3 , value); } -static void print_err_hex16(unsigned short value){ __console_tx_hex16(3 , value); } -static void print_err_hex32(unsigned int value) { __console_tx_hex32(3 , value); } -static void print_err(const char *str) { __console_tx_string(3 , str); } -static void print_warning_char(unsigned char byte) { __console_tx_char(4 , byte); } -static void print_warning_hex8(unsigned char value) { __console_tx_hex8(4 , value); } -static void print_warning_hex16(unsigned short value){ __console_tx_hex16(4 , value); } -static void print_warning_hex32(unsigned int value) { __console_tx_hex32(4 , value); } -static void print_warning(const char *str) { __console_tx_string(4 , str); } -static void print_notice_char(unsigned char byte) { __console_tx_char(5 , byte); } -static void print_notice_hex8(unsigned char value) { __console_tx_hex8(5 , value); } -static void print_notice_hex16(unsigned short value){ __console_tx_hex16(5 , value); } -static void print_notice_hex32(unsigned int value) { __console_tx_hex32(5 , value); } -static void print_notice(const char *str) { __console_tx_string(5 , str); } -static void print_info_char(unsigned char byte) { __console_tx_char(6 , byte); } -static void print_info_hex8(unsigned char value) { __console_tx_hex8(6 , value); } -static void print_info_hex16(unsigned short value){ __console_tx_hex16(6 , value); } -static void print_info_hex32(unsigned int value) { __console_tx_hex32(6 , value); } -static void print_info(const char *str) { __console_tx_string(6 , str); } -static void print_debug_char(unsigned char byte) { __console_tx_char(7 , byte); } -static void print_debug_hex8(unsigned char value) { __console_tx_hex8(7 , value); } -static void print_debug_hex16(unsigned short value){ __console_tx_hex16(7 , value); } -static void print_debug_hex32(unsigned int value) { __console_tx_hex32(7 , value); } -static void print_debug(const char *str) { __console_tx_string(7 , str); } -static void print_spew_char(unsigned char byte) { __console_tx_char(8 , byte); } -static void print_spew_hex8(unsigned char value) { __console_tx_hex8(8 , value); } -static void print_spew_hex16(unsigned short value){ __console_tx_hex16(8 , value); } -static void print_spew_hex32(unsigned int value) { __console_tx_hex32(8 , value); } -static void print_spew(const char *str) { __console_tx_string(8 , str); } -static void console_init(void) -{ - static const char console_test[] = - "\r\n\r\nLinuxBIOS-" - "1.1.4" - ".0Fallback" - " " - "Thu Oct 9 20:29:48 MDT 2003" - " starting...\r\n"; - print_info(console_test); -} -static void die(const char *str) -{ - print_emerg(str); - do { - hlt(); - } while(1); -} -static void write_phys(unsigned long addr, unsigned long value) -{ - asm volatile( - "movnti %1, (%0)" - : - : "r" (addr), "r" (value) - : - ); -} -static unsigned long read_phys(unsigned long addr) -{ - volatile unsigned long *ptr; - ptr = (void *)addr; - return *ptr; -} -static void ram_fill(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - print_debug("DRAM fill: "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - - if (!(addr & 0xffff)) { - print_debug_hex32(addr); - print_debug("\r"); - } - write_phys(addr, addr); - }; - - print_debug_hex32(addr); - print_debug("\r\nDRAM filled\r\n"); -} -static void ram_verify(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - print_debug("DRAM verify: "); - print_debug_hex32(start); - print_debug_char('-'); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - unsigned long value; - - if (!(addr & 0xffff)) { - print_debug_hex32(addr); - print_debug("\r"); - } - value = read_phys(addr); - if (value != addr) { - - print_err_hex32(addr); - print_err_char(':'); - print_err_hex32(value); - print_err("\r\n"); - } - } - - print_debug_hex32(addr); - print_debug("\r\nDRAM verified\r\n"); -} -void ram_check(unsigned long start, unsigned long stop) -{ - int result; - - print_debug("Testing DRAM : "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - ram_fill(start, stop); - ram_verify(start, stop); - print_debug("Done.\r\n"); -} -static int enumerate_ht_chain(unsigned link) -{ - - unsigned next_unitid, last_unitid; - int reset_needed = 0; - next_unitid = 1; - do { - uint32_t id; - uint8_t hdr_type, pos; - last_unitid = next_unitid; - id = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x00 ); - - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - break; - } - hdr_type = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x0e ); - pos = 0; - hdr_type &= 0x7f; - if ((hdr_type == 0 ) || - (hdr_type == 1 )) { - pos = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x34 ); - } - while(pos != 0) { - uint8_t cap; - cap = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , pos + 0 ); - if (cap == 0x08 ) { - uint16_t flags; - flags = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , pos + 2 ); - if ((flags >> 13) == 0) { - unsigned count; - flags &= ~0x1f; - flags |= next_unitid & 0x1f; - count = (flags >> 5) & 0x1f; - pci_write_config16(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , pos + 2 , flags); - next_unitid += count; - break; - } - } - pos = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , pos + 1 ); - } - } while((last_unitid != next_unitid) && (next_unitid <= 0x1f)); - return reset_needed; -} -static void enable_smbus(void) -{ - device_t dev; - dev = pci_locate_device((((( 0x746b ) & 0xFFFF) << 16) | (( 0x1022 ) & 0xFFFF)) , 0); - if (dev == (0xffffffffU) ) { - die("SMBUS controller not found\r\n"); - } - uint8_t enable; - print_debug("SMBus controller enabled\r\n"); - pci_write_config32(dev, 0x58, 0x0f00 | 1); - enable = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, enable | (1 << 7)); - - outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); -} -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} -static int smbus_wait_until_ready(void) -{ - unsigned long loops; - loops = (100*1000*10) ; - do { - unsigned short val; - smbus_delay(); - val = inw(0x0f00 + 0xe0 ); - if ((val & 0x800) == 0) { - break; - } - if(loops == ((100*1000*10) / 2)) { - outw(inw(0x0f00 + 0xe0 ), - 0x0f00 + 0xe0 ); - } - } while(--loops); - return loops?0:-2; -} -static int smbus_wait_until_done(void) -{ - unsigned long loops; - loops = (100*1000*10) ; - do { - unsigned short val; - smbus_delay(); - - val = inw(0x0f00 + 0xe0 ); - if (((val & 0x8) == 0) | ((val & 0x437) != 0)) { - break; - } - } while(--loops); - return loops?0:-3; -} -static int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char global_control_register; - unsigned char global_status_register; - unsigned char byte; - if (smbus_wait_until_ready() < 0) { - return -2; - } - - - - outw(inw(0x0f00 + 0xe2 ) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), 0x0f00 + 0xe2 ); - - outw(((device & 0x7f) << 1) | 1, 0x0f00 + 0xe4 ); - - outb(address & 0xFF, 0x0f00 + 0xe8 ); - - outw((inw(0x0f00 + 0xe2 ) & ~7) | (0x2), 0x0f00 + 0xe2 ); - - - outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); - - outw(0, 0x0f00 + 0xe6 ); - - outw((inw(0x0f00 + 0xe2 ) | (1 << 3)), 0x0f00 + 0xe2 ); - - if (smbus_wait_until_done() < 0) { - return -3; - } - global_status_register = inw(0x0f00 + 0xe0 ); - - byte = inw(0x0f00 + 0xe6 ) & 0xff; - if (global_status_register != (1 << 4)) { - return -1; - } - return byte; -} -static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - return; -} -struct mem_controller { - unsigned node_id; - device_t f0, f1, f2, f3; - uint8_t channel0[4]; - uint8_t channel1[4]; -}; -typedef __builtin_msr_t msr_t; -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} -struct tsc_struct { - unsigned lo; - unsigned hi; -}; -typedef struct tsc_struct tsc_t; -static tsc_t rdtsc(void) -{ - tsc_t res; - asm ("rdtsc" - : "=a" (res.lo), "=d"(res.hi) - : - : - ); - return res; -} -void init_timer(void) -{ - - apic_write(0x320 , (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - apic_write(0x3E0 , 0xB ); - - apic_write(0x380 , 0xffffffff); -} -void udelay(unsigned usecs) -{ - uint32_t start, value, ticks; - - ticks = usecs * 200; - start = apic_read(0x390 ); - do { - value = apic_read(0x390 ); - } while((start - value) < ticks); - -} -void mdelay(unsigned msecs) -{ - unsigned i; - for(i = 0; i < msecs; i++) { - udelay(1000); - } -} -void delay(unsigned secs) -{ - unsigned i; - for(i = 0; i < secs; i++) { - mdelay(1000); - } -} -int boot_cpu(void) -{ - volatile unsigned long *local_apic; - unsigned long apic_id; - int bsp; - msr_t msr; - msr = rdmsr(0x1b); - bsp = !!(msr.lo & (1 << 8)); - return bsp; -} -static int cpu_init_detected(void) -{ - unsigned long htic; - htic = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c ); - return !!(htic & (1<<6) ); -} -static int bios_reset_detected(void) -{ - unsigned long htic; - htic = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c ); - return (htic & (1<<4) ) && !(htic & (1<<5) ); -} -static int cold_reset_detected(void) -{ - unsigned long htic; - htic = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c ); - return !(htic & (1<<4) ); -} -static void distinguish_cpu_resets(unsigned node_id) -{ - uint32_t htic; - device_t device; - device = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 + node_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - htic = pci_read_config32(device, 0x6c ); - htic |= (1<<4) | (1<<5) | (1<<6) ; - pci_write_config32(device, 0x6c , htic); -} -static void set_bios_reset(void) -{ - unsigned long htic; - htic = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c ); - htic &= ~(1<<5) ; - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c , htic); -} -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} -static void print_pci_devices(void) -{ - device_t dev; - for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; - dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { - uint32_t id; - id = pci_read_config32(dev, 0x00 ); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\r\n"); - } -} -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\r\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } -} -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; - dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { - uint32_t id; - id = pci_read_config32(dev, 0x00 ); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} -static void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - print_debug("\r\n"); - for(i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".0: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - } -} - -static unsigned int cpuid(unsigned int op) -{ - unsigned int ret; - unsigned dummy2,dummy3,dummy4; - asm volatile ( - "cpuid" - : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) - : "a" (op) - ); - return ret; -} -static int is_cpu_rev_a0(void) -{ - return (cpuid(1) & 0xffff) == 0x0f10; -} -static int is_cpu_pre_c0(void) -{ - return (cpuid(1) & 0xffef) < 0x0f48; -} -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0x0f00 + 0xc0 + 28); - - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0x0f00 + 0xc0 + 29); - } - else { - - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0x0f00 + 0xc0 + 29); - } -} -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0x0f00 + 0xc0 + 28); - udelay(90); - } -} -static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) -{ - - uint32_t ret=0x00010101; - static const unsigned int rows_2p[2][2] = { - { 0x00050101, 0x00010404 }, - { 0x00010404, 0x00050101 } - }; - if(maxnodes>2) { - print_debug("this mainboard is only designed for 2 cpus\r\n"); - maxnodes=2; - } - if (!(node>=maxnodes || row>=maxnodes)) { - ret=rows_2p[node][row]; - } - return ret; -} -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static void coherent_ht_mainboard(unsigned cpus) -{ -} - -void cpu_ldtstop(unsigned cpus) -{ - uint32_t tmp; - device_t dev; - unsigned cnt; - for(cnt=0; cnt<cpus; cnt++) { - - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0x81,0x23); - - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0xd4,0x00000701); - - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0xd8,0x00000000); - - tmp=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) ,0x90); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) ,0x90, tmp | (1<<24) ); - } -} - - - - - -static void setup_resource_map(const unsigned int *register_values, int max) -{ - int i; - print_debug("setting up resource map....\r\n"); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } - print_debug("done.\r\n"); -} -static void setup_default_resource_map(void) -{ - static const unsigned int register_values[] = { - - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x0000f8f8, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x0000f8f8, 0x00000001, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x0000f8f8, 0x00000002, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x0000f8f8, 0x00000003, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x64 ) & 0xFF)) , 0x0000f8f8, 0x00000004, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0x0000f8f8, 0x00000005, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0x0000f8f8, 0x00000006, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0x0000f8f8, 0x00000007, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x84 ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x8C ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x9C ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xA4 ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xAC ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB4 ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xBC ) & 0xFF)) , 0x00000048, 0x00ffff00, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x80 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x88 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xA0 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xA8 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB0 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB8 ) & 0xFF)) , 0x000000f0, 0x00fc0003, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC4 ) & 0xFF)) , 0xFE000FC8, 0x01fff000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xCC ) & 0xFF)) , 0xFE000FC8, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD4 ) & 0xFF)) , 0xFE000FC8, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xDC ) & 0xFF)) , 0xFE000FC8, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC0 ) & 0xFF)) , 0xFE000FCC, 0x00000003, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC8 ) & 0xFF)) , 0xFE000FCC, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD0 ) & 0xFF)) , 0xFE000FCC, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD8 ) & 0xFF)) , 0xFE000FCC, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE0 ) & 0xFF)) , 0x0000FC88, 0xff000003, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE4 ) & 0xFF)) , 0x0000FC88, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE8 ) & 0xFF)) , 0x0000FC88, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xEC ) & 0xFF)) , 0x0000FC88, 0x00000000, - }; - int max; - max = sizeof(register_values)/sizeof(register_values[0]); - setup_resource_map(register_values, max); -} -static void sdram_set_registers(const struct mem_controller *ctrl) -{ - static const unsigned int register_values[] = { - - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x0000f8f8, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x0000f8f8, 0x00000001, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x0000f8f8, 0x00000002, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x0000f8f8, 0x00000003, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x64 ) & 0xFF)) , 0x0000f8f8, 0x00000004, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0x0000f8f8, 0x00000005, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0x0000f8f8, 0x00000006, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0x0000f8f8, 0x00000007, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x001f01fe, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x64 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0xC01f01ff, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x80 ) & 0xFF)) , 0xffff8888, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x88 ) & 0xFF)) , 0xe8088008, 0x02522001 , - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x8c ) & 0xFF)) , 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0), - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xf0000000, - (4 << 25)|(0 << 24)| - (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| - (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| - (2 << 14)|(0 << 13)|(0 << 12)| - (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| - (0 << 3) |(0 << 1) |(0 << 0), - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0xc180f0f0, - (0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)| - (0 << 20)|(0 << 19)|(3 << 16)|(0 << 8)|(0 << 0), - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0xfc00ffff, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0xffe0e0e0, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x0000003e, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0xffffff00, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0xffff8000, 0x00000f70, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xffffff80, 0x00000002, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0x0000000f, 0x00068300, - }; - int i; - int max; - print_debug("setting up CPU"); - print_debug_hex8(ctrl->node_id); - print_debug(" northbridge registers\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - dev = (register_values[i] & ~0xff) - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) + ctrl->f0; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } - print_debug("done.\r\n"); -} -static int is_dual_channel(const struct mem_controller *ctrl) -{ - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, 0x90 ); - return dcl & (1<<16) ; -} -static int is_opteron(const struct mem_controller *ctrl) -{ - - uint32_t nbcap; - nbcap = pci_read_config32(ctrl->f3, 0xE8 ); - return !!(nbcap & 0x0001 ); -} -static int is_registered(const struct mem_controller *ctrl) -{ - - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, 0x90 ); - return !(dcl & (1<<18) ); -} -struct dimm_size { - unsigned long side1; - unsigned long side2; -}; -static struct dimm_size spd_get_dimm_size(unsigned device) -{ - - struct dimm_size sz; - int value, low; - sz.side1 = 0; - sz.side2 = 0; - - value = spd_read_byte(device, 3); - if (value < 0) goto out; - sz.side1 += value & 0xf; - value = spd_read_byte(device, 4); - if (value < 0) goto out; - sz.side1 += value & 0xf; - value = spd_read_byte(device, 17); - if (value < 0) goto out; - sz.side1 += log2(value & 0xff); - - value = spd_read_byte(device, 7); - if (value < 0) goto out; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, 6); - if (low < 0) goto out; - value = value | (low & 0xff); - sz.side1 += log2(value); - - value = spd_read_byte(device, 5); - if (value <= 1) goto out; - - sz.side2 = sz.side1; - value = spd_read_byte(device, 3); - if (value < 0) goto out; - if ((value & 0xf0) == 0) goto out; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); - value = spd_read_byte(device, 4); - if (value < 0) goto out; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); - out: - return sz; -} -static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) -{ - uint32_t base0, base1, map; - uint32_t dch; - if (sz.side1 != sz.side2) { - sz.side2 = 0; - } - map = pci_read_config32(ctrl->f2, 0x80 ); - map &= ~(0xf << (index + 4)); - - - base0 = base1 = 0; - - if (sz.side1 >= (25 +3)) { - map |= (sz.side1 - (25 + 3)) << (index *4); - base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1; - } - - if (sz.side2 >= (25 + 3)) { - base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1; - } - - if (is_dual_channel(ctrl)) { - base0 = (base0 << 1) | (base0 & 1); - base1 = (base1 << 1) | (base1 & 1); - } - - base0 &= ~0x001ffffe; - base1 &= ~0x001ffffe; - - pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+0)<<2), base0); - pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+1)<<2), base1); - pci_write_config32(ctrl->f2, 0x80 , map); - - - if (base0) { - dch = pci_read_config32(ctrl->f2, 0x94 ); - dch |= (1 << 26) << index; - pci_write_config32(ctrl->f2, 0x94 , dch); - } -} -static void spd_set_ram_size(const struct mem_controller *ctrl) -{ - int i; - - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - struct dimm_size sz; - sz = spd_get_dimm_size(ctrl->channel0[i]); - set_dimm_size(ctrl, sz, i); - } -} -static void route_dram_accesses(const struct mem_controller *ctrl, - unsigned long base_k, unsigned long limit_k) -{ - - unsigned node_id; - unsigned limit; - unsigned base; - unsigned index; - unsigned limit_reg, base_reg; - device_t device; - node_id = ctrl->node_id; - index = (node_id << 3); - limit = (limit_k << 2); - limit &= 0xffff0000; - limit -= 0x00010000; - limit |= ( 0 << 8) | (node_id << 0); - base = (base_k << 2); - base &= 0xffff0000; - base |= (0 << 8) | (1<<1) | (1<<0); - limit_reg = 0x44 + index; - base_reg = 0x40 + index; - for(device = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ; device <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ; device += ( ((( 0 ) & 0xFF) << 16) | ((( 1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ) { - pci_write_config32(device, limit_reg, limit); - pci_write_config32(device, base_reg, base); - } -} -static void set_top_mem(unsigned tom_k) -{ - - if (!tom_k) { - set_bios_reset(); - print_debug("No memory - reset"); - - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0x04 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , 0x41, 0xf1); - - outb(0x0e, 0x0cf9); - } - - print_debug("RAM: 0x"); - print_debug_hex32(tom_k); - print_debug(" KB\r\n"); - - msr_t msr; - msr.lo = (tom_k & 0x003fffff) << 10; - msr.hi = (tom_k & 0xffc00000) >> 22; - wrmsr(0xC001001D , msr); - - if (tom_k >= 0x003f0000) { - tom_k = 0x3f0000; - } - msr.lo = (tom_k & 0x003fffff) << 10; - msr.hi = (tom_k & 0xffc00000) >> 22; - wrmsr(0xC001001A , msr); -} -static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) -{ - - static const uint32_t csbase_low[] = { - (1 << (13 - 4)), - (1 << (14 - 4)), - (1 << (14 - 4)), - (1 << (15 - 4)), - (1 << (15 - 4)), - (1 << (16 - 4)), - (1 << (16 - 4)), - }; - uint32_t csbase_inc; - int chip_selects, index; - int bits; - int dual_channel; - unsigned common_size; - uint32_t csbase, csmask; - - chip_selects = 0; - common_size = 0; - for(index = 0; index < 8; index++) { - unsigned size; - uint32_t value; - - value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - - - if (!(value & 1)) { - continue; - } - chip_selects++; - size = value >> 21; - if (common_size == 0) { - common_size = size; - } - - if (common_size != size) { - return 0; - } - } - - bits = log2(chip_selects); - if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { - return 0; - - } - - if ((bits == 3) && (common_size == (1 << (32 - 3)))) { - print_debug("8 4GB chip selects cannot be interleaved\r\n"); - return 0; - } - - if (is_dual_channel(ctrl)) { - csbase_inc = csbase_low[log2(common_size) - 1] << 1; - } else { - csbase_inc = csbase_low[log2(common_size)]; - } - - csbase = 0 | 1; - csmask = (((common_size << bits) - 1) << 21); - csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc); - for(index = 0; index < 8; index++) { - uint32_t value; - value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - - if (!(value & 1)) { - continue; - } - pci_write_config32(ctrl->f2, 0x40 + (index << 2), csbase); - pci_write_config32(ctrl->f2, 0x60 + (index << 2), csmask); - csbase += csbase_inc; - } - - print_debug("Interleaved\r\n"); - - return common_size << (15 + bits); -} -static unsigned long order_chip_selects(const struct mem_controller *ctrl) -{ - unsigned long tom; - - - tom = 0; - for(;;) { - - unsigned index, canidate; - uint32_t csbase, csmask; - unsigned size; - csbase = 0; - canidate = 0; - for(index = 0; index < 8; index++) { - uint32_t value; - value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - - if (!(value & 1)) { - continue; - } - - - if (value <= csbase) { - continue; - } - - - if (tom & (1 << (index + 24))) { - continue; - } - - csbase = value; - canidate = index; - } - - if (csbase == 0) { - break; - } - - size = csbase >> 21; - - tom |= (1 << (canidate + 24)); - - csbase = (tom << 21) | 1; - - tom += size; - - csmask = ((size -1) << 21); - csmask |= 0xfe00; - - pci_write_config32(ctrl->f2, 0x40 + (canidate << 2), csbase); - - pci_write_config32(ctrl->f2, 0x60 + (canidate << 2), csmask); - - } - - return (tom & ~0xff000000) << 15; -} -static void order_dimms(const struct mem_controller *ctrl) -{ - unsigned long tom, tom_k, base_k; - unsigned node_id; - tom_k = interleave_chip_selects(ctrl); - if (!tom_k) { - tom_k = order_chip_selects(ctrl); - } - - base_k = 0; - for(node_id = 0; node_id < ctrl->node_id; node_id++) { - uint32_t limit, base; - unsigned index; - index = node_id << 3; - base = pci_read_config32(ctrl->f1, 0x40 + index); - - if ((base & 3) == 3) { - limit = pci_read_config32(ctrl->f1, 0x44 + index); - base_k = ((limit + 0x00010000) & 0xffff0000) >> 2; - } - } - tom_k += base_k; - route_dram_accesses(ctrl, base_k, tom_k); - set_top_mem(tom_k); -} -static void disable_dimm(const struct mem_controller *ctrl, unsigned index) -{ - print_debug("disabling dimm"); - print_debug_hex8(index); - print_debug("\r\n"); - pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+0)<<2), 0); - pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+1)<<2), 0); -} -static void spd_handle_unbuffered_dimms(const struct mem_controller *ctrl) -{ - int i; - int registered; - int unbuffered; - uint32_t dcl; - unbuffered = 0; - registered = 0; - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int value; - value = spd_read_byte(ctrl->channel0[i], 21); - if (value < 0) { - disable_dimm(ctrl, i); - continue; - } - - if (value & (1 << 1)) { - registered = 1; - } - - else { - unbuffered = 1; - } - } - if (unbuffered && registered) { - die("Mixed buffered and registered dimms not supported"); - } - if (unbuffered && is_opteron(ctrl)) { - die("Unbuffered Dimms not supported on Opteron"); - } - dcl = pci_read_config32(ctrl->f2, 0x90 ); - dcl &= ~(1<<18) ; - if (unbuffered) { - dcl |= (1<<18) ; - } - pci_write_config32(ctrl->f2, 0x90 , dcl); -} -static void spd_enable_2channels(const struct mem_controller *ctrl) -{ - int i; - uint32_t nbcap; - - - static const unsigned addresses[] = { - 2, - 3, - 4, - 5, - 6, - 7, - 9, - 11, - 13, - 17, - 18, - 21, - 23, - 26, - 27, - 28, - 29, - 30, - 41, - 42, - }; - nbcap = pci_read_config32(ctrl->f3, 0xE8 ); - if (!(nbcap & 0x0001 )) { - return; - } - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - unsigned device0, device1; - int value0, value1; - int j; - device0 = ctrl->channel0[i]; - device1 = ctrl->channel1[i]; - if (!device1) - return; - for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { - unsigned addr; - addr = addresses[j]; - value0 = spd_read_byte(device0, addr); - if (value0 < 0) { - break; - } - value1 = spd_read_byte(device1, addr); - if (value1 < 0) { - return; - } - if (value0 != value1) { - return; - } - } - } - print_debug("Enabling dual channel memory\r\n"); - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, 0x90 ); - dcl &= ~(1<<19) ; - dcl |= (1<<16) ; - pci_write_config32(ctrl->f2, 0x90 , dcl); -} -struct mem_param { - uint8_t cycle_time; - uint8_t divisor; - uint8_t tRC; - uint8_t tRFC; - uint32_t dch_memclk; - uint16_t dch_tref4k, dch_tref8k; - uint8_t dtl_twr; - char name[9]; -}; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) -{ - static const struct mem_param speed[] = { - { - .name = "100Mhz\r\n", - .cycle_time = 0xa0, - .divisor = (10 <<1), - .tRC = 0x46, - .tRFC = 0x50, - .dch_memclk = 0 << 20 , - .dch_tref4k = 0x00 , - .dch_tref8k = 0x08 , - .dtl_twr = 2, - }, - { - .name = "133Mhz\r\n", - .cycle_time = 0x75, - .divisor = (7<<1)+1, - .tRC = 0x41, - .tRFC = 0x4B, - .dch_memclk = 2 << 20 , - .dch_tref4k = 0x01 , - .dch_tref8k = 0x09 , - .dtl_twr = 2, - }, - { - .name = "166Mhz\r\n", - .cycle_time = 0x60, - .divisor = (6<<1), - .tRC = 0x3C, - .tRFC = 0x48, - .dch_memclk = 5 << 20 , - .dch_tref4k = 0x02 , - .dch_tref8k = 0x0A , - .dtl_twr = 3, - }, - { - .name = "200Mhz\r\n", - .cycle_time = 0x50, - .divisor = (5<<1), - .tRC = 0x37, - .tRFC = 0x46, - .dch_memclk = 7 << 20 , - .dch_tref4k = 0x03 , - .dch_tref8k = 0x0B , - .dtl_twr = 3, - }, - { - .cycle_time = 0x00, - }, - }; - const struct mem_param *param; - for(param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } - print_debug(param->name); - return param; -} -static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) -{ - - const struct mem_param *param; - unsigned min_cycle_time, min_latency; - int i; - uint32_t value; - static const int latency_indices[] = { 26, 23, 9 }; - static const unsigned char min_cycle_times[] = { - [0 ] = 0x50, - [1 ] = 0x60, - [2 ] = 0x75, - [3 ] = 0xa0, - }; - value = pci_read_config32(ctrl->f3, 0xE8 ); - min_cycle_time = min_cycle_times[(value >> 5 ) & 3 ]; - min_latency = 2; - - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - - new_cycle_time = 0xa0; - new_latency = 5; - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - latency = log2(latencies) -2; - - for(index = 0; index < 3; index++, latency++) { - int value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { - continue; - } - value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); - if (value < 0) { - continue; - } - - if ((value >= min_cycle_time) && (value < new_cycle_time)) { - new_cycle_time = value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - - - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int value; - int dimm; - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) { - goto dimm_err; - } - - latency = log2(latencies) -2; - - for(index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { - continue; - } - if (latency == min_latency) - break; - } - - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; - } - - - value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); - - - if (value <= min_cycle_time) { - continue; - } - - dimm_err: - disable_dimm(ctrl, i); - } - - param = get_mem_param(min_cycle_time); - - value = pci_read_config32(ctrl->f2, 0x94 ); - value &= ~(0x7 << 20 ); - value |= param->dch_memclk; - pci_write_config32(ctrl->f2, 0x94 , value); - static const unsigned latencies[] = { 1 , 5 , 2 }; - - value = pci_read_config32(ctrl->f2, 0x88 ); - value &= ~(0x7 << 0 ); - value |= latencies[min_latency - 2] << 0 ; - pci_write_config32(ctrl->f2, 0x88 , value); - - return param; -} -static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 41); - if (value < 0) return -1; - if ((value == 0) || (value == 0xff)) { - value = param->tRC; - } - clocks = ((value << 1) + param->divisor - 1)/param->divisor; - if (clocks < 7 ) { - clocks = 7 ; - } - if (clocks > 22 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 4 ) & 0xf ) + 7 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0xf << 4 ); - dtl |= ((clocks - 7 ) << 4 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 42); - if (value < 0) return -1; - if ((value == 0) || (value == 0xff)) { - value = param->tRFC; - } - clocks = ((value << 1) + param->divisor - 1)/param->divisor; - if (clocks < 9 ) { - clocks = 9 ; - } - if (clocks > 24 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 8 ) & 0xf ) + 9 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0xf << 8 ); - dtl |= ((clocks - 9 ) << 8 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 29); - if (value < 0) return -1; - clocks = (value + ((param->divisor & 0xff) << 1) -1)/((param->divisor & 0xff) << 1); - if (clocks < 2 ) { - clocks = 2 ; - } - if (clocks > 6 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 12 ) & 0x7 ) + 0 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0x7 << 12 ); - dtl |= ((clocks - 0 ) << 12 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 28); - if (value < 0) return -1; - clocks = (value + ((param->divisor & 0xff) << 1) -1)/((param->divisor & 0xff) << 1); - if (clocks < 2 ) { - clocks = 2 ; - } - if (clocks > 4 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 16 ) & 0x7 ) + 0 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0x7 << 16 ); - dtl |= ((clocks - 0 ) << 16 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 30); - if (value < 0) return -1; - clocks = ((value << 1) + param->divisor - 1)/param->divisor; - if (clocks < 5 ) { - clocks = 5 ; - } - if (clocks > 15 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 20 ) & 0xf ) + 0 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0xf << 20 ); - dtl |= ((clocks - 0 ) << 20 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 27); - if (value < 0) return -1; - clocks = (value + ((param->divisor & 0xff) << 1) - 1)/((param->divisor & 0xff) << 1); - if (clocks < 2 ) { - clocks = 2 ; - } - if (clocks > 6 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 24 ) & 0x7 ) + 0 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0x7 << 24 ); - dtl |= ((clocks - 0 ) << 24 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dtl; - dtl = pci_read_config32(ctrl->f2, 0x88 ); - dtl &= ~(0x1 << 28 ); - dtl |= (param->dtl_twr - 2 ) << 28 ; - pci_write_config32(ctrl->f2, 0x88 , dtl); -} -static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dth; - dth = pci_read_config32(ctrl->f2, 0x8c ); - dth &= ~(0x1f << 8 ); - dth |= (param->dch_tref4k << 8 ); - pci_write_config32(ctrl->f2, 0x8c , dth); -} -static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - uint32_t dth; - int value; - unsigned tref, old_tref; - value = spd_read_byte(ctrl->channel0[i], 3); - if (value < 0) return -1; - value &= 0xf; - tref = param->dch_tref8k; - if (value == 12) { - tref = param->dch_tref4k; - } - dth = pci_read_config32(ctrl->f2, 0x8c ); - old_tref = (dth >> 8 ) & 0x1f ; - if ((value == 12) && (old_tref == param->dch_tref4k)) { - tref = param->dch_tref4k; - } else { - tref = param->dch_tref8k; - } - dth &= ~(0x1f << 8 ); - dth |= (tref << 8 ); - pci_write_config32(ctrl->f2, 0x8c , dth); - return 0; -} -static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - uint32_t dcl; - int value; - int dimm; - value = spd_read_byte(ctrl->channel0[i], 13); - if (value < 0) { - return -1; - } - dimm = i; - dimm += 20 ; - dcl = pci_read_config32(ctrl->f2, 0x90 ); - dcl &= ~(1 << dimm); - if (value == 4) { - dcl |= (1 << dimm); - } - pci_write_config32(ctrl->f2, 0x90 , dcl); - return 0; -} -static int update_dimm_ecc(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - uint32_t dcl; - int value; - value = spd_read_byte(ctrl->channel0[i], 11); - if (value < 0) { - return -1; - } - if (value != 2) { - dcl = pci_read_config32(ctrl->f2, 0x90 ); - dcl &= ~(1<<17) ; - pci_write_config32(ctrl->f2, 0x90 , dcl); - } - return 0; -} -static int count_dimms(const struct mem_controller *ctrl) -{ - int dimms; - unsigned index; - dimms = 0; - for(index = 0; index < 8; index += 2) { - uint32_t csbase; - csbase = pci_read_config32(ctrl->f2, (0x40 + index << 2)); - if (csbase & 1) { - dimms += 1; - } - } - return dimms; -} -static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dth; - unsigned clocks; - clocks = 1; - dth = pci_read_config32(ctrl->f2, 0x8c ); - dth &= ~(0x1 << 0 ); - dth |= ((clocks - 1 ) << 0 ); - pci_write_config32(ctrl->f2, 0x8c , dth); -} -static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dth, dtl; - unsigned divisor; - unsigned latency; - unsigned clocks; - clocks = 0; - dtl = pci_read_config32(ctrl->f2, 0x88 ); - latency = (dtl >> 0 ) & 0x7 ; - divisor = param->divisor; - if (is_opteron(ctrl)) { - if (latency == 1 ) { - if (divisor == ((6 << 0) + 0)) { - - clocks = 3; - } - else if (divisor > ((6 << 0)+0)) { - - clocks = 2; - } - } - else if (latency == 5 ) { - clocks = 3; - } - else if (latency == 2 ) { - if (divisor == ((6 << 0)+0)) { - - clocks = 4; - } - else if (divisor > ((6 << 0)+0)) { - - clocks = 3; - } - } - } - else { - if (is_registered(ctrl)) { - if (latency == 1 ) { - clocks = 2; - } - else if (latency == 5 ) { - clocks = 3; - } - else if (latency == 2 ) { - clocks = 3; - } - } - else { - if (latency == 1 ) { - clocks = 3; - } - else if (latency == 5 ) { - clocks = 4; - } - else if (latency == 2 ) { - clocks = 4; - } - } - } - if ((clocks < 1 ) || (clocks > 6 )) { - die("Unknown Trwt"); - } - - dth = pci_read_config32(ctrl->f2, 0x8c ); - dth &= ~(0x7 << 4 ); - dth |= ((clocks - 1 ) << 4 ); - pci_write_config32(ctrl->f2, 0x8c , dth); - return; -} -static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param) -{ - - uint32_t dth; - unsigned clocks; - if (is_registered(ctrl)) { - clocks = 2; - } else { - clocks = 1; - } - dth = pci_read_config32(ctrl->f2, 0x8c ); - dth &= ~(0x7 << 20 ); - dth |= ((clocks - 1 ) << 20 ); - pci_write_config32(ctrl->f2, 0x8c , dth); -} -static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dch; - unsigned divisor; - unsigned rdpreamble; - divisor = param->divisor; - dch = pci_read_config32(ctrl->f2, 0x94 ); - dch &= ~(0xf << 8 ); - rdpreamble = 0; - if (is_registered(ctrl)) { - if (divisor == ((10 << 1)+0)) { - - rdpreamble = ((9 << 1)+ 0); - } - else if (divisor == ((7 << 1)+1)) { - - rdpreamble = ((8 << 1)+0); - } - else if (divisor == ((6 << 1)+0)) { - - rdpreamble = ((7 << 1)+1); - } - else if (divisor == ((5 << 1)+0)) { - - rdpreamble = ((7 << 1)+0); - } - } - else { - int slots; - int i; - slots = 0; - for(i = 0; i < 4; i++) { - if (ctrl->channel0[i]) { - slots += 1; - } - } - if (divisor == ((10 << 1)+0)) { - - if (slots <= 2) { - - rdpreamble = ((9 << 1)+0); - } else { - - rdpreamble = ((14 << 1)+0); - } - } - else if (divisor == ((7 << 1)+1)) { - - if (slots <= 2) { - - rdpreamble = ((7 << 1)+0); - } else { - - rdpreamble = ((11 << 1)+0); - } - } - else if (divisor == ((6 << 1)+0)) { - - if (slots <= 2) { - - rdpreamble = ((7 << 1)+0); - } else { - - rdpreamble = ((9 << 1)+0); - } - } - else if (divisor == ((5 << 1)+0)) { - - if (slots <= 2) { - - rdpreamble = ((5 << 1)+0); - } else { - - rdpreamble = ((7 << 1)+0); - } - } - } - if ((rdpreamble < ((2<<1)+0) ) || (rdpreamble > ((9<<1)+1) )) { - die("Unknown rdpreamble"); - } - dch |= (rdpreamble - ((2<<1)+0) ) << 8 ; - pci_write_config32(ctrl->f2, 0x94 , dch); -} -static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dch; - int i; - unsigned async_lat; - int dimms; - dimms = count_dimms(ctrl); - dch = pci_read_config32(ctrl->f2, 0x94 ); - dch &= ~(0xf << 0 ); - async_lat = 0; - if (is_registered(ctrl)) { - if (dimms == 4) { - - async_lat = 9; - } - else { - - async_lat = 8; - } - } - else { - if (dimms > 3) { - die("Too many unbuffered dimms"); - } - else if (dimms == 3) { - - async_lat = 7; - } - else { - - async_lat = 6; - } - } - dch |= ((async_lat - 0 ) << 0 ); - pci_write_config32(ctrl->f2, 0x94 , dch); -} -static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dch; - - dch = pci_read_config32(ctrl->f2, 0x94 ); - dch &= ~(0x7 << 16 ); - dch |= 3 << 16 ; - dch |= (1 << 19) ; - pci_write_config32(ctrl->f2, 0x94 , dch); -} -static void spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param) -{ - int dimms; - int i; - int rc; - - init_Tref(ctrl, param); - for(i = 0; (i < 4) && ctrl->channel0[i]; i++) { - int rc; - - if (update_dimm_Trc (ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Trfc(ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Trcd(ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Trrd(ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Tras(ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Trp (ctrl, param, i) < 0) goto dimm_err; - - if (update_dimm_Tref(ctrl, param, i) < 0) goto dimm_err; - - if (update_dimm_x4 (ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_ecc(ctrl, param, i) < 0) goto dimm_err; - continue; - dimm_err: - disable_dimm(ctrl, i); - - } - - set_Twr(ctrl, param); - - set_Twtr(ctrl, param); - set_Trwt(ctrl, param); - set_Twcl(ctrl, param); - - set_read_preamble(ctrl, param); - set_max_async_latency(ctrl, param); - set_idle_cycle_limit(ctrl, param); -} -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - const struct mem_param *param; - spd_enable_2channels(ctrl); - spd_set_ram_size(ctrl); - spd_handle_unbuffered_dimms(ctrl); - param = spd_set_memclk(ctrl); - spd_set_dram_timing(ctrl, param); - order_dimms(ctrl); -} -static void sdram_enable(int controllers, const struct mem_controller *ctrl) -{ - int i; - - for(i = 0; i < controllers; i++) { - uint32_t dch; - dch = pci_read_config32(ctrl[i].f2, 0x94 ); - dch |= (1 << 25) ; - pci_write_config32(ctrl[i].f2, 0x94 , dch); - } - - memreset(controllers, ctrl); - for(i = 0; i < controllers; i++) { - uint32_t dcl; - - dcl = pci_read_config32(ctrl[i].f2, 0x90 ); - if (dcl & (1<<17) ) { - uint32_t mnc; - print_debug("ECC enabled\r\n"); - mnc = pci_read_config32(ctrl[i].f3, 0x44 ); - mnc |= (1 << 22) ; - if (dcl & (1<<16) ) { - mnc |= (1 << 23) ; - } - pci_write_config32(ctrl[i].f3, 0x44 , mnc); - } - dcl |= (1<<3) ; - pci_write_config32(ctrl[i].f2, 0x90 , dcl); - dcl &= ~(1<<3) ; - dcl &= ~(1<<0) ; - dcl &= ~(1<<1) ; - dcl &= ~(1<<2) ; - dcl |= (1<<8) ; - pci_write_config32(ctrl[i].f2, 0x90 , dcl); - } - for(i = 0; i < controllers; i++) { - uint32_t dcl; - print_debug("Initializing memory: "); - int loops = 0; - do { - dcl = pci_read_config32(ctrl[i].f2, 0x90 ); - loops += 1; - if ((loops & 1023) == 0) { - print_debug("."); - } - } while(((dcl & (1<<8) ) != 0) && (loops < 300000 )); - if (loops >= 300000 ) { - print_debug(" failed\r\n"); - } else { - print_debug(" done\r\n"); - } - if (dcl & (1<<17) ) { - print_debug("Clearing memory: "); - if (!is_cpu_pre_c0()) { - - dcl &= ~((1<<11) | (1<<10) ); - pci_write_config32(ctrl[i].f2, 0x90 , dcl); - do { - dcl = pci_read_config32(ctrl[i].f2, 0x90 ); - } while(((dcl & (1<<11) ) == 0) || ((dcl & (1<<10) ) == 0) ); - } - uint32_t base, last_scrub_k, scrub_k; - uint32_t cnt,zstart,zend; - msr_t msr,msr_201; - - pci_write_config32(ctrl[i].f3, 0x58 , - (0 << 16) | (0 << 8) | (0 << 0)); - - msr_201 = rdmsr(0x201); - zstart = pci_read_config32(ctrl[0].f1, 0x40 + (i*8)); - zend = pci_read_config32(ctrl[0].f1, 0x44 + (i*8)); - zstart >>= 16; - zend >>=16; - print_debug("addr "); - print_debug_hex32(zstart); - print_debug("-"); - print_debug_hex32(zend); - print_debug("\r\n"); - - - msr = rdmsr(0x2ff ); - msr.lo &= ~(1<<10); - wrmsr(0x2ff , msr); - - msr = rdmsr(0xc0010015); - msr.lo |= (1<<17); - wrmsr(0xc0010015,msr); - for(;zstart<zend;zstart+=4) { - - if(zstart == 0x0fc) - continue; - - - __asm__ volatile( - "movl %%cr0, %0\n\t" - "orl $0x40000000, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) - ); - - - msr.lo = 1 + ((zstart&0x0ff)<<24); - msr.hi = (zstart&0x0ff00)>>8; - wrmsr(0x200,msr); - - msr.hi = 0x000000ff; - msr.lo = 0xfc000800; - wrmsr(0x201,msr); - - __asm__ volatile( - "movl %%cr0, %0\n\t" - "andl $0x9fffffff, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) - ); - - msr.lo = (zstart&0xff) << 24; - msr.hi = (zstart&0xff00) >> 8; - wrmsr(0xc0000100,msr); - print_debug_char((zstart > 0x0ff)?'+':'-'); - - - __asm__ volatile( - "1: \n\t" - "movl %0, %%fs:(%1)\n\t" - "addl $4,%1\n\t" - "subl $1,%2\n\t" - "jnz 1b\n\t" - : - : "a" (0), "D" (0), "c" (0x01000000) - ); - } - - - __asm__ volatile( - "movl %%cr0, %0\n\t" - "orl $0x40000000, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) - ); - - - msr = rdmsr(0x2ff ); - msr.lo |= 0x0400; - wrmsr(0x2ff , msr); - - msr.lo = 6; - msr.hi = 0; - wrmsr(0x200,msr); - wrmsr(0x201,msr_201); - - msr.lo = 0; - msr.hi = 0; - wrmsr(0xc0000100,msr); - - __asm__ volatile( - "movl %%cr0, %0\n\t" - "andl $0x9fffffff, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) - ); - - - msr = rdmsr(0xc0010015); - msr.lo &= ~(1<<17); - wrmsr(0xc0010015,msr); - - base = pci_read_config32(ctrl[i].f1, 0x40 + (ctrl[i].node_id << 3)); - base &= 0xffff0000; - - pci_write_config32(ctrl[i].f3, 0x5C , base << 8); - pci_write_config32(ctrl[i].f3, 0x60 , base >> 24); - - pci_write_config32(ctrl[i].f3, 0x58 , - (22 << 16) | (22 << 8) | (22 << 0)); - print_debug("done\r\n"); - } - } -} - - - - - -typedef uint8_t u8; -typedef uint32_t u32; -typedef int8_t bool; -static void disable_probes(void) -{ - - - u32 val; - print_debug("Disabling read/write/fill probes for UP... "); - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68); - val |= (1<<10)|(1<<9)|(1<<8)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1 << 0); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68, val); - print_debug("done.\r\n"); -} - -static void wait_ap_stop(u8 node) -{ - unsigned long reg; - unsigned long i; - for(i=0;i< 1000 ;i++) { - unsigned long regx; - regx = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x6c); - if((regx & (1<<4))==1) break; - } - reg = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x6c); - reg &= ~(1<<4); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c, reg); -} -static void notify_bsp_ap_is_stopped(void) -{ - unsigned long reg; - unsigned long apic_id; - apic_id = *((volatile unsigned long *)(0xfee00000 + 0x020 )); - apic_id >>= 24; - - if(apic_id != 0) { - - reg = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ apic_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6C); - reg |= 1<<4; - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ apic_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6C, reg); - } - -} - -static void enable_routing(u8 node) -{ - u32 val; - - - print_debug("Enabling routing table for node "); - print_debug_hex32(node); - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c); - val &= ~((1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c, val); - - if(node!=0) { - wait_ap_stop(node); - } - - print_debug(" done.\r\n"); -} -static void rename_temp_node(u8 node) -{ - uint32_t val; - print_debug("Renaming current temp node to "); - print_debug_hex32(node); - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60); - val &= (~7); - val |= node; - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60, val); - print_debug(" done.\r\n"); -} -static bool check_connection(u8 src, u8 dest, u8 link) -{ - - u32 val; - - - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ src ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x98+link); - if ( (val&0x17) != 0x03) - return 0; - - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ dest ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0); - if(val != 0x11001022) - return 0; - return 1; -} -static void optimize_connection(u8 node1, u8 link1, u8 node2, u8 link2) -{ - static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; - static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; - uint16_t freq_cap1, freq_cap2, freq_cap, freq_mask; - uint8_t width_cap1, width_cap2, width_cap, width, ln_width1, ln_width2; - uint8_t freq; - - - freq_cap1 = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 0x0a ); - freq_cap2 = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 0x0a ); - - - freq = log2(freq_cap1 & freq_cap2 & 0xff); - - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 0x09 , freq); - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 0x09 , freq); - - width_cap1 = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 6 ); - width_cap2 = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 6 ); - - ln_width1 = link_width_to_pow2[width_cap1 & 7]; - ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; - if (ln_width1 > ln_width2) { - ln_width1 = ln_width2; - } - width = pow2_to_link_width[ln_width1]; - - ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; - ln_width2 = link_width_to_pow2[width_cap2 & 7]; - if (ln_width1 > ln_width2) { - ln_width1 = ln_width2; - } - width |= pow2_to_link_width[ln_width1] << 4; - - - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 6 + 1, width); - - width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 6 + 1, width); -} -static void fill_row(u8 node, u8 row, u32 value) -{ - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x40+(row<<2), value); -} -static void setup_row(u8 source, u8 dest, u8 cpus) -{ - fill_row(source,dest,generate_row(source,dest,cpus)); -} -static void setup_temp_row(u8 source, u8 dest, u8 cpus) -{ - fill_row(source,7,((generate_row( source,dest,cpus )&(~0x0f0000))|0x010000) ); -} -static void setup_node(u8 node, u8 cpus) -{ - u8 row; - for(row=0; row<cpus; row++) - setup_row(node, row, cpus); -} -static void setup_remote_row(u8 source, u8 dest, u8 cpus) -{ - fill_row(7, dest, generate_row(source, dest, cpus)); -} -static void setup_remote_node(u8 node, u8 cpus) -{ - static const uint8_t pci_reg[] = { - 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, - 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78, - 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, - 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, - 0xc4, 0xcc, 0xd4, 0xdc, - 0xc0, 0xc8, 0xd0, 0xd8, - 0xe0, 0xe4, 0xe8, 0xec, - }; - uint8_t row; - int i; - print_debug("setup_remote_node\r\n"); - for(row=0; row<cpus; row++) - setup_remote_row(node, row, cpus); - - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { - uint32_t value; - uint8_t reg; - reg = pci_reg[i]; - value = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) , reg); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) , reg, value); - } - print_debug("setup_remote_done\r\n"); -} -static u8 setup_uniprocessor(void) -{ - print_debug("Enabling UP settings\r\n"); - disable_probes(); - return 1; -} -static u8 setup_smp(void) -{ - u8 cpus=2; - print_debug("Enabling SMP settings\r\n"); - setup_row(0,0,cpus); - - setup_temp_row(0,1,cpus); - - if (!check_connection(0, 7, 0x20 )) { - print_debug("No connection to Node 1.\r\n"); - fill_row( 0 ,7,0x00010101 ) ; - setup_uniprocessor(); - return 1; - } - - optimize_connection(0, 0x20 , 7, 0x20 ); - setup_node(0, cpus); - setup_remote_node(1, cpus); - rename_temp_node(1); - enable_routing(1); - - fill_row( 0 ,7,0x00010101 ) ; - - print_debug_hex32(cpus); - print_debug(" nodes initialized.\r\n"); - return cpus; -} -static unsigned detect_mp_capabilities(unsigned cpus) -{ - unsigned node, row, mask; - bool mp_cap= (-1) ; - print_debug("detect_mp_capabilities: "); - print_debug_hex32(cpus); - print_debug("\r\n"); - if (cpus>2) - mask=0x06; - else - mask=0x02; - for (node=0; node<cpus; node++) { - if ((pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , 0xe8) & mask)!=mask) - mp_cap= (0) ; - } - if (mp_cap) - return cpus; - - print_debug("One of the CPUs is not MP capable. Going back to UP\r\n"); - for (node=cpus; node>0; node--) - for (row=cpus; row>0; row--) - fill_row(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node-1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , row-1, 0x00010101 ); - - return setup_uniprocessor(); -} -static void coherent_ht_finalize(unsigned cpus) -{ - int node; - bool rev_a0; - - - print_debug("coherent_ht_finalize\r\n"); - rev_a0= is_cpu_rev_a0(); - for (node=0; node<cpus; node++) { - u32 val; - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60); - val &= (~0x000F0070); - val |= ((cpus-1)<<16)|((cpus-1)<<4); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x60,val); - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68); - val |= 0x00008000; - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x68,val); - if (rev_a0) { - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x94,0); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0xb4,0); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0xd4,0); - } - } - print_debug("done\r\n"); -} -static int setup_coherent_ht_domain(void) -{ - unsigned cpus; - int reset_needed = 0; - enable_routing(0) ; - cpus=setup_smp(); - cpus=detect_mp_capabilities(cpus); - coherent_ht_finalize(cpus); - - coherent_ht_mainboard(cpus); - return reset_needed; -} -void sdram_no_memory(void) -{ - print_err("No memory!!\r\n"); - while(1) { - hlt(); - } -} - -void sdram_initialize(int controllers, const struct mem_controller *ctrl) -{ - int i; - - for(i = 0; i < controllers; i++) { - print_debug("Ram1."); - print_debug_hex8(i); - print_debug("\r\n"); - sdram_set_registers(ctrl + i); - } - - for(i = 0; i < controllers; i++) { - print_debug("Ram2."); - print_debug_hex8(i); - print_debug("\r\n"); - sdram_set_spd_registers(ctrl + i); - } - - print_debug("Ram3\r\n"); - sdram_enable(controllers, ctrl); - print_debug("Ram4\r\n"); -} -static void enable_lapic(void) -{ - msr_t msr; - msr = rdmsr(0x1b); - msr.hi &= 0xffffff00; - msr.lo &= 0x000007ff; - msr.lo |= 0xfee00000 | (1 << 11); - wrmsr(0x1b, msr); -} -static void stop_this_cpu(void) -{ - unsigned apicid; - apicid = apic_read(0x020 ) >> 24; - - apic_write(0x310 , (( apicid )<<24) ); - apic_write(0x300 , 0x08000 | 0x04000 | 0x00500 ); - - apic_wait_icr_idle(); - - apic_write(0x310 , (( apicid )<<24) ); - apic_write(0x300 , 0x08000 | 0x00500 ); - - apic_wait_icr_idle(); - - for(;;) { - hlt(); - } -} -static void pc87360_enable_serial(void) -{ - pnp_set_logical_device(0x2e , 0x03 ); - pnp_set_enable(0x2e , 1); - pnp_set_iobase0(0x2e , 0x3f8); -} -static void main(void) -{ - - static const struct mem_controller cpu[] = { - { - .node_id = 0, - .f0 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , - .f1 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) , - .f2 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) , - .f3 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, - }, - { - .node_id = 1, - .f0 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x19 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , - .f1 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x19 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) , - .f2 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x19 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) , - .f3 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x19 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, - }, - }; - if (cpu_init_detected()) { - asm("jmp __cpu_reset"); - } - enable_lapic(); - init_timer(); - if (!boot_cpu()) { - stop_this_cpu(); - } - pc87360_enable_serial(); - uart_init(); - console_init(); - setup_default_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(0); - distinguish_cpu_resets(0); - - enable_smbus(); - memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - -} diff --git a/util/romcc/tests/raminit_test7.c b/util/romcc/tests/raminit_test7.c deleted file mode 100644 index c768e86a3c..0000000000 --- a/util/romcc/tests/raminit_test7.c +++ /dev/null @@ -1,2805 +0,0 @@ -typedef unsigned char uint8_t; -typedef signed char int8_t; -typedef unsigned short uint16_t; -typedef signed short int16_t; -typedef unsigned int uint32_t; -typedef signed int int32_t; - -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -typedef int intptr_t; -typedef unsigned int uintptr_t; - -typedef long int intmax_t; -typedef unsigned long int uintmax_t; - -static inline unsigned long apic_read(unsigned long reg) -{ - return *((volatile unsigned long *)(0xfee00000 +reg)); -} -static inline void apic_write(unsigned long reg, unsigned long v) -{ - *((volatile unsigned long *)(0xfee00000 +reg)) = v; -} -static inline void apic_wait_icr_idle(void) -{ - do { } while ( apic_read( 0x300 ) & 0x01000 ); -} - -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} -static void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} -static void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} -static unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} -static unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} -static unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} -static inline void outsb(uint16_t port, const void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; outsb " - : "=S" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void outsw(uint16_t port, const void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; outsw " - : "=S" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void outsl(uint16_t port, const void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; outsl " - : "=S" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void insb(uint16_t port, void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; insb " - : "=D" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void insw(uint16_t port, void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; insw " - : "=D" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void insl(uint16_t port, void *addr, unsigned long count) -{ - __asm__ __volatile__ ( - "cld ; rep ; insl " - : "=D" (addr), "=c" (count) - : "d"(port), "0"(addr), "1" (count) - ); -} -static inline void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg) -{ - outb(reg, port); - outb(value, port +1); -} -static inline unsigned char pnp_read_config(unsigned char port, unsigned char reg) -{ - outb(reg, port); - return inb(port +1); -} -static inline void pnp_set_logical_device(unsigned char port, int device) -{ - pnp_write_config(port, device, 0x07); -} -static inline void pnp_set_enable(unsigned char port, int enable) -{ - pnp_write_config(port, enable?0x1:0x0, 0x30); -} -static inline int pnp_read_enable(unsigned char port) -{ - return !!pnp_read_config(port, 0x30); -} -static inline void pnp_set_iobase0(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x60); - pnp_write_config(port, iobase & 0xff, 0x61); -} -static inline void pnp_set_iobase1(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x62); - pnp_write_config(port, iobase & 0xff, 0x63); -} -static inline void pnp_set_irq0(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x70); -} -static inline void pnp_set_irq1(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x72); -} -static inline void pnp_set_drq(unsigned char port, unsigned drq) -{ - pnp_write_config(port, drq & 0xff, 0x74); -} -static void hlt(void) -{ - __builtin_hlt(); -} -typedef __builtin_div_t div_t; -typedef __builtin_ldiv_t ldiv_t; -typedef __builtin_udiv_t udiv_t; -typedef __builtin_uldiv_t uldiv_t; -static div_t div(int numer, int denom) -{ - return __builtin_div(numer, denom); -} -static ldiv_t ldiv(long numer, long denom) -{ - return __builtin_ldiv(numer, denom); -} -static udiv_t udiv(unsigned numer, unsigned denom) -{ - return __builtin_udiv(numer, denom); -} -static uldiv_t uldiv(unsigned long numer, unsigned long denom) -{ - return __builtin_uldiv(numer, denom); -} -int log2(int value) -{ - - return __builtin_bsr(value); -} -typedef unsigned device_t; -static unsigned char pci_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} -static unsigned short pci_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} -static unsigned int pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} -static void pci_write_config16(device_t dev, unsigned where, unsigned short value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} -static void pci_write_config32(device_t dev, unsigned where, unsigned int value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} -static device_t pci_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= ( ((( 255 ) & 0xFF) << 16) | ((( 31 ) & 0x1f) << 11) | ((( 7 ) & 0x7) << 8)) ; dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return (0xffffffffU) ; -} - - - - - -static int uart_can_tx_byte(void) -{ - return inb(1016 + 0x05 ) & 0x20; -} -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} -static void uart_wait_until_sent(void) -{ - while(!(inb(1016 + 0x05 ) & 0x40)) - ; -} -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, 1016 + 0x00 ); - - uart_wait_until_sent(); -} -static void uart_init(void) -{ - - outb(0x0, 1016 + 0x01 ); - - outb(0x01, 1016 + 0x02 ); - - outb(0x80 | 3 , 1016 + 0x03 ); - outb((115200/ 115200 ) & 0xFF, 1016 + 0x00 ); - outb(((115200/ 115200 ) >> 8) & 0xFF, 1016 + 0x01 ); - outb(3 , 1016 + 0x03 ); -} - -static void __console_tx_byte(unsigned char byte) -{ - uart_tx_byte(byte); -} -static void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_byte(digit); -} -static void __console_tx_char(int loglevel, unsigned char byte) -{ - if (8 > loglevel) { - uart_tx_byte(byte); - } -} -static void __console_tx_hex8(int loglevel, unsigned char value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} -static void __console_tx_hex16(int loglevel, unsigned short value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} -static void __console_tx_hex32(int loglevel, unsigned int value) -{ - if (8 > loglevel) { - __console_tx_nibble((value >> 28U) & 0x0fU); - __console_tx_nibble((value >> 24U) & 0x0fU); - __console_tx_nibble((value >> 20U) & 0x0fU); - __console_tx_nibble((value >> 16U) & 0x0fU); - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void do_console_tx_string(const char *str) __attribute__((noinline)) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_byte(ch); - } -} -static void __console_tx_string(int loglevel, const char *str) -{ - if (8 > loglevel) { - do_console_tx_string(str); - } -} -static void print_emerg_char(unsigned char byte) { __console_tx_char(0 , byte); } -static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(0 , value); } -static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(0 , value); } -static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(0 , value); } -static void print_emerg(const char *str) { __console_tx_string(0 , str); } -static void print_alert_char(unsigned char byte) { __console_tx_char(1 , byte); } -static void print_alert_hex8(unsigned char value) { __console_tx_hex8(1 , value); } -static void print_alert_hex16(unsigned short value){ __console_tx_hex16(1 , value); } -static void print_alert_hex32(unsigned int value) { __console_tx_hex32(1 , value); } -static void print_alert(const char *str) { __console_tx_string(1 , str); } -static void print_crit_char(unsigned char byte) { __console_tx_char(2 , byte); } -static void print_crit_hex8(unsigned char value) { __console_tx_hex8(2 , value); } -static void print_crit_hex16(unsigned short value){ __console_tx_hex16(2 , value); } -static void print_crit_hex32(unsigned int value) { __console_tx_hex32(2 , value); } -static void print_crit(const char *str) { __console_tx_string(2 , str); } -static void print_err_char(unsigned char byte) { __console_tx_char(3 , byte); } -static void print_err_hex8(unsigned char value) { __console_tx_hex8(3 , value); } -static void print_err_hex16(unsigned short value){ __console_tx_hex16(3 , value); } -static void print_err_hex32(unsigned int value) { __console_tx_hex32(3 , value); } -static void print_err(const char *str) { __console_tx_string(3 , str); } -static void print_warning_char(unsigned char byte) { __console_tx_char(4 , byte); } -static void print_warning_hex8(unsigned char value) { __console_tx_hex8(4 , value); } -static void print_warning_hex16(unsigned short value){ __console_tx_hex16(4 , value); } -static void print_warning_hex32(unsigned int value) { __console_tx_hex32(4 , value); } -static void print_warning(const char *str) { __console_tx_string(4 , str); } -static void print_notice_char(unsigned char byte) { __console_tx_char(5 , byte); } -static void print_notice_hex8(unsigned char value) { __console_tx_hex8(5 , value); } -static void print_notice_hex16(unsigned short value){ __console_tx_hex16(5 , value); } -static void print_notice_hex32(unsigned int value) { __console_tx_hex32(5 , value); } -static void print_notice(const char *str) { __console_tx_string(5 , str); } -static void print_info_char(unsigned char byte) { __console_tx_char(6 , byte); } -static void print_info_hex8(unsigned char value) { __console_tx_hex8(6 , value); } -static void print_info_hex16(unsigned short value){ __console_tx_hex16(6 , value); } -static void print_info_hex32(unsigned int value) { __console_tx_hex32(6 , value); } -static void print_info(const char *str) { __console_tx_string(6 , str); } -static void print_debug_char(unsigned char byte) { __console_tx_char(7 , byte); } -static void print_debug_hex8(unsigned char value) { __console_tx_hex8(7 , value); } -static void print_debug_hex16(unsigned short value){ __console_tx_hex16(7 , value); } -static void print_debug_hex32(unsigned int value) { __console_tx_hex32(7 , value); } -static void print_debug(const char *str) { __console_tx_string(7 , str); } -static void print_spew_char(unsigned char byte) { __console_tx_char(8 , byte); } -static void print_spew_hex8(unsigned char value) { __console_tx_hex8(8 , value); } -static void print_spew_hex16(unsigned short value){ __console_tx_hex16(8 , value); } -static void print_spew_hex32(unsigned int value) { __console_tx_hex32(8 , value); } -static void print_spew(const char *str) { __console_tx_string(8 , str); } -static void console_init(void) -{ - static const char console_test[] = - "\r\n\r\nLinuxBIOS-" - "1.1.4" - ".0Fallback" - " " - "Thu Oct 9 20:29:48 MDT 2003" - " starting...\r\n"; - print_info(console_test); -} -static void die(const char *str) -{ - print_emerg(str); - do { - hlt(); - } while(1); -} -static void write_phys(unsigned long addr, unsigned long value) -{ - asm volatile( - "movnti %1, (%0)" - : - : "r" (addr), "r" (value) - : - ); -} -static unsigned long read_phys(unsigned long addr) -{ - volatile unsigned long *ptr; - ptr = (void *)addr; - return *ptr; -} -static void ram_fill(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - print_debug("DRAM fill: "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - - if (!(addr & 0xffff)) { - print_debug_hex32(addr); - print_debug("\r"); - } - write_phys(addr, addr); - }; - - print_debug_hex32(addr); - print_debug("\r\nDRAM filled\r\n"); -} -static void ram_verify(unsigned long start, unsigned long stop) -{ - unsigned long addr; - - print_debug("DRAM verify: "); - print_debug_hex32(start); - print_debug_char('-'); - print_debug_hex32(stop); - print_debug("\r\n"); - for(addr = start; addr < stop ; addr += 4) { - unsigned long value; - - if (!(addr & 0xffff)) { - print_debug_hex32(addr); - print_debug("\r"); - } - value = read_phys(addr); - if (value != addr) { - - print_err_hex32(addr); - print_err_char(':'); - print_err_hex32(value); - print_err("\r\n"); - } - } - - print_debug_hex32(addr); - print_debug("\r\nDRAM verified\r\n"); -} -void ram_check(unsigned long start, unsigned long stop) -{ - int result; - - print_debug("Testing DRAM : "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - ram_fill(start, stop); - ram_verify(start, stop); - print_debug("Done.\r\n"); -} -static int enumerate_ht_chain(unsigned link) -{ - - unsigned next_unitid, last_unitid; - int reset_needed = 0; - next_unitid = 1; - do { - uint32_t id; - uint8_t hdr_type, pos; - last_unitid = next_unitid; - id = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x00 ); - - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - break; - } - hdr_type = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x0e ); - pos = 0; - hdr_type &= 0x7f; - if ((hdr_type == 0 ) || - (hdr_type == 1 )) { - pos = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x34 ); - } - while(pos != 0) { - uint8_t cap; - cap = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , pos + 0 ); - if (cap == 0x08 ) { - uint16_t flags; - flags = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , pos + 2 ); - if ((flags >> 13) == 0) { - unsigned count; - flags &= ~0x1f; - flags |= next_unitid & 0x1f; - count = (flags >> 5) & 0x1f; - pci_write_config16(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , pos + 2 , flags); - next_unitid += count; - break; - } - } - pos = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , pos + 1 ); - } - } while((last_unitid != next_unitid) && (next_unitid <= 0x1f)); - return reset_needed; -} -static void enable_smbus(void) -{ - device_t dev; - dev = pci_locate_device((((( 0x746b ) & 0xFFFF) << 16) | (( 0x1022 ) & 0xFFFF)) , 0); - if (dev == (0xffffffffU) ) { - die("SMBUS controller not found\r\n"); - } - uint8_t enable; - print_debug("SMBus controller enabled\r\n"); - pci_write_config32(dev, 0x58, 0x0f00 | 1); - enable = pci_read_config8(dev, 0x41); - pci_write_config8(dev, 0x41, enable | (1 << 7)); - - outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); -} -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} -static int smbus_wait_until_ready(void) -{ - unsigned long loops; - loops = (100*1000*10) ; - do { - unsigned short val; - smbus_delay(); - val = inw(0x0f00 + 0xe0 ); - if ((val & 0x800) == 0) { - break; - } - if(loops == ((100*1000*10) / 2)) { - outw(inw(0x0f00 + 0xe0 ), - 0x0f00 + 0xe0 ); - } - } while(--loops); - return loops?0:-2; -} -static int smbus_wait_until_done(void) -{ - unsigned long loops; - loops = (100*1000*10) ; - do { - unsigned short val; - smbus_delay(); - - val = inw(0x0f00 + 0xe0 ); - if (((val & 0x8) == 0) | ((val & 0x437) != 0)) { - break; - } - } while(--loops); - return loops?0:-3; -} -static int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char global_control_register; - unsigned char global_status_register; - unsigned char byte; - if (smbus_wait_until_ready() < 0) { - return -2; - } - - - - outw(inw(0x0f00 + 0xe2 ) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), 0x0f00 + 0xe2 ); - - outw(((device & 0x7f) << 1) | 1, 0x0f00 + 0xe4 ); - - outb(address & 0xFF, 0x0f00 + 0xe8 ); - - outw((inw(0x0f00 + 0xe2 ) & ~7) | (0x2), 0x0f00 + 0xe2 ); - - - outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); - - outw(0, 0x0f00 + 0xe6 ); - - outw((inw(0x0f00 + 0xe2 ) | (1 << 3)), 0x0f00 + 0xe2 ); - - if (smbus_wait_until_done() < 0) { - return -3; - } - global_status_register = inw(0x0f00 + 0xe0 ); - - byte = inw(0x0f00 + 0xe6 ) & 0xff; - if (global_status_register != (1 << 4)) { - return -1; - } - return byte; -} -static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - return; -} -struct mem_controller { - unsigned node_id; - device_t f0, f1, f2, f3; - uint8_t channel0[4]; - uint8_t channel1[4]; -}; -typedef __builtin_msr_t msr_t; -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} -struct tsc_struct { - unsigned lo; - unsigned hi; -}; -typedef struct tsc_struct tsc_t; -static tsc_t rdtsc(void) -{ - tsc_t res; - asm ("rdtsc" - : "=a" (res.lo), "=d"(res.hi) - : - : - ); - return res; -} -void init_timer(void) -{ - - apic_write(0x320 , (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - apic_write(0x3E0 , 0xB ); - - apic_write(0x380 , 0xffffffff); -} -void udelay(unsigned usecs) -{ - uint32_t start, value, ticks; - - ticks = usecs * 200; - start = apic_read(0x390 ); - do { - value = apic_read(0x390 ); - } while((start - value) < ticks); - -} -void mdelay(unsigned msecs) -{ - unsigned i; - for(i = 0; i < msecs; i++) { - udelay(1000); - } -} -void delay(unsigned secs) -{ - unsigned i; - for(i = 0; i < secs; i++) { - mdelay(1000); - } -} -int boot_cpu(void) -{ - volatile unsigned long *local_apic; - unsigned long apic_id; - int bsp; - msr_t msr; - msr = rdmsr(0x1b); - bsp = !!(msr.lo & (1 << 8)); - return bsp; -} -static int cpu_init_detected(void) -{ - unsigned long htic; - htic = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c ); - return !!(htic & (1<<6) ); -} -static int bios_reset_detected(void) -{ - unsigned long htic; - htic = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c ); - return (htic & (1<<4) ) && !(htic & (1<<5) ); -} -static int cold_reset_detected(void) -{ - unsigned long htic; - htic = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c ); - return !(htic & (1<<4) ); -} -static void distinguish_cpu_resets(unsigned node_id) -{ - uint32_t htic; - device_t device; - device = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 + node_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - htic = pci_read_config32(device, 0x6c ); - htic |= (1<<4) | (1<<5) | (1<<6) ; - pci_write_config32(device, 0x6c , htic); -} -static void set_bios_reset(void) -{ - unsigned long htic; - htic = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c ); - htic &= ~(1<<5) ; - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c , htic); -} -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} -static void print_pci_devices(void) -{ - device_t dev; - for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; - dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { - uint32_t id; - id = pci_read_config32(dev, 0x00 ); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\r\n"); - } -} -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\r\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } -} -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; - dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { - uint32_t id; - id = pci_read_config32(dev, 0x00 ); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} -static void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - print_debug("\r\n"); - for(i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".0: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - } -} - -static unsigned int cpuid(unsigned int op) -{ - unsigned int ret; - unsigned dummy2,dummy3,dummy4; - asm volatile ( - "cpuid" - : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) - : "a" (op) - ); - return ret; -} -static int is_cpu_rev_a0(void) -{ - return (cpuid(1) & 0xffff) == 0x0f10; -} -static int is_cpu_pre_c0(void) -{ - return (cpuid(1) & 0xffef) < 0x0f48; -} -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0x0f00 + 0xc0 + 28); - - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0x0f00 + 0xc0 + 29); - } - else { - - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0x0f00 + 0xc0 + 29); - } -} -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0x0f00 + 0xc0 + 28); - udelay(90); - } -} -static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) -{ - - uint32_t ret=0x00010101; - static const unsigned int rows_2p[2][2] = { - { 0x00050101, 0x00010404 }, - { 0x00010404, 0x00050101 } - }; - if(maxnodes>2) { - print_debug("this mainboard is only designed for 2 cpus\r\n"); - maxnodes=2; - } - if (!(node>=maxnodes || row>=maxnodes)) { - ret=rows_2p[node][row]; - } - return ret; -} -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static void coherent_ht_mainboard(unsigned cpus) -{ -} - -void cpu_ldtstop(unsigned cpus) -{ - uint32_t tmp; - device_t dev; - unsigned cnt; - for(cnt=0; cnt<cpus; cnt++) { - - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0x81,0x23); - - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0xd4,0x00000701); - - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0xd8,0x00000000); - - tmp=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) ,0x90); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) ,0x90, tmp | (1<<24) ); - } -} - - - - - -static void setup_resource_map(const unsigned int *register_values, int max) -{ - int i; - print_debug("setting up resource map....\r\n"); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - dev = register_values[i] & ~0xff; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } - print_debug("done.\r\n"); -} -static void setup_default_resource_map(void) -{ - static const unsigned int register_values[] = { - - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x0000f8f8, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x0000f8f8, 0x00000001, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x0000f8f8, 0x00000002, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x0000f8f8, 0x00000003, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x64 ) & 0xFF)) , 0x0000f8f8, 0x00000004, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0x0000f8f8, 0x00000005, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0x0000f8f8, 0x00000006, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0x0000f8f8, 0x00000007, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x84 ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x8C ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x9C ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xA4 ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xAC ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB4 ) & 0xFF)) , 0x00000048, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xBC ) & 0xFF)) , 0x00000048, 0x00ffff00, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x80 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x88 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xA0 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xA8 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB0 ) & 0xFF)) , 0x000000f0, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB8 ) & 0xFF)) , 0x000000f0, 0x00fc0003, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC4 ) & 0xFF)) , 0xFE000FC8, 0x01fff000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xCC ) & 0xFF)) , 0xFE000FC8, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD4 ) & 0xFF)) , 0xFE000FC8, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xDC ) & 0xFF)) , 0xFE000FC8, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC0 ) & 0xFF)) , 0xFE000FCC, 0x00000003, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC8 ) & 0xFF)) , 0xFE000FCC, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD0 ) & 0xFF)) , 0xFE000FCC, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD8 ) & 0xFF)) , 0xFE000FCC, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE0 ) & 0xFF)) , 0x0000FC88, 0xff000003, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE4 ) & 0xFF)) , 0x0000FC88, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE8 ) & 0xFF)) , 0x0000FC88, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xEC ) & 0xFF)) , 0x0000FC88, 0x00000000, - }; - int max; - max = sizeof(register_values)/sizeof(register_values[0]); - setup_resource_map(register_values, max); -} -static void sdram_set_registers(const struct mem_controller *ctrl) -{ - static const unsigned int register_values[] = { - - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x0000f8f8, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x0000f8f8, 0x00000001, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x0000f8f8, 0x00000002, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x0000f8f8, 0x00000003, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x64 ) & 0xFF)) , 0x0000f8f8, 0x00000004, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0x0000f8f8, 0x00000005, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0x0000f8f8, 0x00000006, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0x0000f8f8, 0x00000007, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0x001f01fe, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x001f01fe, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x64 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0xC01f01ff, 0x00000000, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0xC01f01ff, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x80 ) & 0xFF)) , 0xffff8888, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x88 ) & 0xFF)) , 0xe8088008, 0x02522001 , - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x8c ) & 0xFF)) , 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0), - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xf0000000, - (4 << 25)|(0 << 24)| - (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| - (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| - (2 << 14)|(0 << 13)|(0 << 12)| - (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| - (0 << 3) |(0 << 1) |(0 << 0), - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0xc180f0f0, - (0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)| - (0 << 20)|(0 << 19)|(3 << 16)|(0 << 8)|(0 << 0), - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0xfc00ffff, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0xffe0e0e0, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x0000003e, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0xffffff00, 0x00000000, - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0xffff8000, 0x00000f70, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xffffff80, 0x00000002, - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0x0000000f, 0x00068300, - }; - int i; - int max; - print_debug("setting up CPU"); - print_debug_hex8(ctrl->node_id); - print_debug(" northbridge registers\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - device_t dev; - unsigned where; - unsigned long reg; - dev = (register_values[i] & ~0xff) - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) + ctrl->f0; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } - print_debug("done.\r\n"); -} -static int is_dual_channel(const struct mem_controller *ctrl) -{ - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, 0x90 ); - return dcl & (1<<16) ; -} -static int is_opteron(const struct mem_controller *ctrl) -{ - - uint32_t nbcap; - nbcap = pci_read_config32(ctrl->f3, 0xE8 ); - return !!(nbcap & 0x0001 ); -} -static int is_registered(const struct mem_controller *ctrl) -{ - - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, 0x90 ); - return !(dcl & (1<<18) ); -} -struct dimm_size { - unsigned long side1; - unsigned long side2; -}; -static struct dimm_size spd_get_dimm_size(unsigned device) -{ - - struct dimm_size sz; - int value, low; - sz.side1 = 0; - sz.side2 = 0; - - value = spd_read_byte(device, 3); - if (value < 0) goto out; - sz.side1 += value & 0xf; - value = spd_read_byte(device, 4); - if (value < 0) goto out; - sz.side1 += value & 0xf; - value = spd_read_byte(device, 17); - if (value < 0) goto out; - sz.side1 += log2(value & 0xff); - - value = spd_read_byte(device, 7); - if (value < 0) goto out; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, 6); - if (low < 0) goto out; - value = value | (low & 0xff); - sz.side1 += log2(value); - - value = spd_read_byte(device, 5); - if (value <= 1) goto out; - - sz.side2 = sz.side1; - value = spd_read_byte(device, 3); - if (value < 0) goto out; - if ((value & 0xf0) == 0) goto out; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); - value = spd_read_byte(device, 4); - if (value < 0) goto out; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); - out: - return sz; -} -static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) -{ - uint32_t base0, base1, map; - uint32_t dch; - if (sz.side1 != sz.side2) { - sz.side2 = 0; - } - map = pci_read_config32(ctrl->f2, 0x80 ); - map &= ~(0xf << (index + 4)); - - - base0 = base1 = 0; - - if (sz.side1 >= (25 +3)) { - map |= (sz.side1 - (25 + 3)) << (index *4); - base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1; - } - - if (sz.side2 >= (25 + 3)) { - base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1; - } - - if (is_dual_channel(ctrl)) { - base0 = (base0 << 1) | (base0 & 1); - base1 = (base1 << 1) | (base1 & 1); - } - - base0 &= ~0x001ffffe; - base1 &= ~0x001ffffe; - - pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+0)<<2), base0); - pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+1)<<2), base1); - pci_write_config32(ctrl->f2, 0x80 , map); - - - if (base0) { - dch = pci_read_config32(ctrl->f2, 0x94 ); - dch |= (1 << 26) << index; - pci_write_config32(ctrl->f2, 0x94 , dch); - } -} -static void spd_set_ram_size(const struct mem_controller *ctrl) -{ - int i; - - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - struct dimm_size sz; - sz = spd_get_dimm_size(ctrl->channel0[i]); - set_dimm_size(ctrl, sz, i); - } -} -static void route_dram_accesses(const struct mem_controller *ctrl, - unsigned long base_k, unsigned long limit_k) -{ - - unsigned node_id; - unsigned limit; - unsigned base; - unsigned index; - unsigned limit_reg, base_reg; - device_t device; - node_id = ctrl->node_id; - index = (node_id << 3); - limit = (limit_k << 2); - limit &= 0xffff0000; - limit -= 0x00010000; - limit |= ( 0 << 8) | (node_id << 0); - base = (base_k << 2); - base &= 0xffff0000; - base |= (0 << 8) | (1<<1) | (1<<0); - limit_reg = 0x44 + index; - base_reg = 0x40 + index; - for(device = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ; device <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ; device += ( ((( 0 ) & 0xFF) << 16) | ((( 1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ) { - pci_write_config32(device, limit_reg, limit); - pci_write_config32(device, base_reg, base); - } -} -static void set_top_mem(unsigned tom_k) -{ - - if (!tom_k) { - set_bios_reset(); - print_debug("No memory - reset"); - - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0x04 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , 0x41, 0xf1); - - outb(0x0e, 0x0cf9); - } - - print_debug("RAM: 0x"); - print_debug_hex32(tom_k); - print_debug(" KB\r\n"); - - msr_t msr; - msr.lo = (tom_k & 0x003fffff) << 10; - msr.hi = (tom_k & 0xffc00000) >> 22; - wrmsr(0xC001001D , msr); - - if (tom_k >= 0x003f0000) { - tom_k = 0x3f0000; - } - msr.lo = (tom_k & 0x003fffff) << 10; - msr.hi = (tom_k & 0xffc00000) >> 22; - wrmsr(0xC001001A , msr); -} -static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) -{ - - static const uint32_t csbase_low[] = { - (1 << (13 - 4)), - (1 << (14 - 4)), - (1 << (14 - 4)), - (1 << (15 - 4)), - (1 << (15 - 4)), - (1 << (16 - 4)), - (1 << (16 - 4)), - }; - uint32_t csbase_inc; - int chip_selects, index; - int bits; - int dual_channel; - unsigned common_size; - uint32_t csbase, csmask; - - chip_selects = 0; - common_size = 0; - for(index = 0; index < 8; index++) { - unsigned size; - uint32_t value; - - value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - - - if (!(value & 1)) { - continue; - } - chip_selects++; - size = value >> 21; - if (common_size == 0) { - common_size = size; - } - - if (common_size != size) { - return 0; - } - } - - bits = log2(chip_selects); - if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { - return 0; - - } - - if ((bits == 3) && (common_size == (1 << (32 - 3)))) { - print_debug("8 4GB chip selects cannot be interleaved\r\n"); - return 0; - } - - if (is_dual_channel(ctrl)) { - csbase_inc = csbase_low[log2(common_size) - 1] << 1; - } else { - csbase_inc = csbase_low[log2(common_size)]; - } - - csbase = 0 | 1; - csmask = (((common_size << bits) - 1) << 21); - csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc); - for(index = 0; index < 8; index++) { - uint32_t value; - value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - - if (!(value & 1)) { - continue; - } - pci_write_config32(ctrl->f2, 0x40 + (index << 2), csbase); - pci_write_config32(ctrl->f2, 0x60 + (index << 2), csmask); - csbase += csbase_inc; - } - - print_debug("Interleaved\r\n"); - - return common_size << (15 + bits); -} -static unsigned long order_chip_selects(const struct mem_controller *ctrl) -{ - unsigned long tom; - - - tom = 0; - for(;;) { - - unsigned index, canidate; - uint32_t csbase, csmask; - unsigned size; - csbase = 0; - canidate = 0; - for(index = 0; index < 8; index++) { - uint32_t value; - value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - - if (!(value & 1)) { - continue; - } - - - if (value <= csbase) { - continue; - } - - - if (tom & (1 << (index + 24))) { - continue; - } - - csbase = value; - canidate = index; - } - - if (csbase == 0) { - break; - } - - size = csbase >> 21; - - tom |= (1 << (canidate + 24)); - - csbase = (tom << 21) | 1; - - tom += size; - - csmask = ((size -1) << 21); - csmask |= 0xfe00; - - pci_write_config32(ctrl->f2, 0x40 + (canidate << 2), csbase); - - pci_write_config32(ctrl->f2, 0x60 + (canidate << 2), csmask); - - } - - return (tom & ~0xff000000) << 15; -} -static void order_dimms(const struct mem_controller *ctrl) -{ - unsigned long tom, tom_k, base_k; - unsigned node_id; - tom_k = interleave_chip_selects(ctrl); - if (!tom_k) { - tom_k = order_chip_selects(ctrl); - } - - base_k = 0; - for(node_id = 0; node_id < ctrl->node_id; node_id++) { - uint32_t limit, base; - unsigned index; - index = node_id << 3; - base = pci_read_config32(ctrl->f1, 0x40 + index); - - if ((base & 3) == 3) { - limit = pci_read_config32(ctrl->f1, 0x44 + index); - base_k = ((limit + 0x00010000) & 0xffff0000) >> 2; - } - } - tom_k += base_k; - route_dram_accesses(ctrl, base_k, tom_k); - set_top_mem(tom_k); -} -static void disable_dimm(const struct mem_controller *ctrl, unsigned index) -{ - print_debug("disabling dimm"); - print_debug_hex8(index); - print_debug("\r\n"); - pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+0)<<2), 0); - pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+1)<<2), 0); -} -static void spd_handle_unbuffered_dimms(const struct mem_controller *ctrl) -{ - int i; - int registered; - int unbuffered; - uint32_t dcl; - unbuffered = 0; - registered = 0; - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int value; - value = spd_read_byte(ctrl->channel0[i], 21); - if (value < 0) { - disable_dimm(ctrl, i); - continue; - } - - if (value & (1 << 1)) { - registered = 1; - } - - else { - unbuffered = 1; - } - } - if (unbuffered && registered) { - die("Mixed buffered and registered dimms not supported"); - } - if (unbuffered && is_opteron(ctrl)) { - die("Unbuffered Dimms not supported on Opteron"); - } - dcl = pci_read_config32(ctrl->f2, 0x90 ); - dcl &= ~(1<<18) ; - if (unbuffered) { - dcl |= (1<<18) ; - } - pci_write_config32(ctrl->f2, 0x90 , dcl); -} -static void spd_enable_2channels(const struct mem_controller *ctrl) -{ - int i; - uint32_t nbcap; - - - static const unsigned addresses[] = { - 2, - 3, - 4, - 5, - 6, - 7, - 9, - 11, - 13, - 17, - 18, - 21, - 23, - 26, - 27, - 28, - 29, - 30, - 41, - 42, - }; - nbcap = pci_read_config32(ctrl->f3, 0xE8 ); - if (!(nbcap & 0x0001 )) { - return; - } - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - unsigned device0, device1; - int value0, value1; - int j; - device0 = ctrl->channel0[i]; - device1 = ctrl->channel1[i]; - if (!device1) - return; - for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { - unsigned addr; - addr = addresses[j]; - value0 = spd_read_byte(device0, addr); - if (value0 < 0) { - break; - } - value1 = spd_read_byte(device1, addr); - if (value1 < 0) { - return; - } - if (value0 != value1) { - return; - } - } - } - print_debug("Enabling dual channel memory\r\n"); - uint32_t dcl; - dcl = pci_read_config32(ctrl->f2, 0x90 ); - dcl &= ~(1<<19) ; - dcl |= (1<<16) ; - pci_write_config32(ctrl->f2, 0x90 , dcl); -} -struct mem_param { - uint8_t cycle_time; - uint8_t divisor; - uint8_t tRC; - uint8_t tRFC; - uint32_t dch_memclk; - uint16_t dch_tref4k, dch_tref8k; - uint8_t dtl_twr; - char name[9]; -}; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) -{ - static const struct mem_param speed[] = { - { - .name = "100Mhz\r\n", - .cycle_time = 0xa0, - .divisor = (10 <<1), - .tRC = 0x46, - .tRFC = 0x50, - .dch_memclk = 0 << 20 , - .dch_tref4k = 0x00 , - .dch_tref8k = 0x08 , - .dtl_twr = 2, - }, - { - .name = "133Mhz\r\n", - .cycle_time = 0x75, - .divisor = (7<<1)+1, - .tRC = 0x41, - .tRFC = 0x4B, - .dch_memclk = 2 << 20 , - .dch_tref4k = 0x01 , - .dch_tref8k = 0x09 , - .dtl_twr = 2, - }, - { - .name = "166Mhz\r\n", - .cycle_time = 0x60, - .divisor = (6<<1), - .tRC = 0x3C, - .tRFC = 0x48, - .dch_memclk = 5 << 20 , - .dch_tref4k = 0x02 , - .dch_tref8k = 0x0A , - .dtl_twr = 3, - }, - { - .name = "200Mhz\r\n", - .cycle_time = 0x50, - .divisor = (5<<1), - .tRC = 0x37, - .tRFC = 0x46, - .dch_memclk = 7 << 20 , - .dch_tref4k = 0x03 , - .dch_tref8k = 0x0B , - .dtl_twr = 3, - }, - { - .cycle_time = 0x00, - }, - }; - const struct mem_param *param; - for(param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } - print_debug(param->name); - return param; -} -static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) -{ - - const struct mem_param *param; - unsigned min_cycle_time, min_latency; - int i; - uint32_t value; - static const int latency_indices[] = { 26, 23, 9 }; - static const unsigned char min_cycle_times[] = { - [0 ] = 0x50, - [1 ] = 0x60, - [2 ] = 0x75, - [3 ] = 0xa0, - }; - value = pci_read_config32(ctrl->f3, 0xE8 ); - min_cycle_time = min_cycle_times[(value >> 5 ) & 3 ]; - min_latency = 2; - - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - - new_cycle_time = 0xa0; - new_latency = 5; - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - latency = log2(latencies) -2; - - for(index = 0; index < 3; index++, latency++) { - int value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { - continue; - } - value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); - if (value < 0) { - continue; - } - - if ((value >= min_cycle_time) && (value < new_cycle_time)) { - new_cycle_time = value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - - - for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int value; - int dimm; - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) { - goto dimm_err; - } - - latency = log2(latencies) -2; - - for(index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { - continue; - } - if (latency == min_latency) - break; - } - - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; - } - - - value = spd_read_byte(ctrl->channel0[i], latency_indices[index]); - - - if (value <= min_cycle_time) { - continue; - } - - dimm_err: - disable_dimm(ctrl, i); - } - - param = get_mem_param(min_cycle_time); - - value = pci_read_config32(ctrl->f2, 0x94 ); - value &= ~(0x7 << 20 ); - value |= param->dch_memclk; - pci_write_config32(ctrl->f2, 0x94 , value); - static const unsigned latencies[] = { 1 , 5 , 2 }; - - value = pci_read_config32(ctrl->f2, 0x88 ); - value &= ~(0x7 << 0 ); - value |= latencies[min_latency - 2] << 0 ; - pci_write_config32(ctrl->f2, 0x88 , value); - - return param; -} -static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 41); - if (value < 0) return -1; - if ((value == 0) || (value == 0xff)) { - value = param->tRC; - } - clocks = ((value << 1) + param->divisor - 1)/param->divisor; - if (clocks < 7 ) { - clocks = 7 ; - } - if (clocks > 22 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 4 ) & 0xf ) + 7 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0xf << 4 ); - dtl |= ((clocks - 7 ) << 4 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 42); - if (value < 0) return -1; - if ((value == 0) || (value == 0xff)) { - value = param->tRFC; - } - clocks = ((value << 1) + param->divisor - 1)/param->divisor; - if (clocks < 9 ) { - clocks = 9 ; - } - if (clocks > 24 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 8 ) & 0xf ) + 9 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0xf << 8 ); - dtl |= ((clocks - 9 ) << 8 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 29); - if (value < 0) return -1; - clocks = (value + ((param->divisor & 0xff) << 1) -1)/((param->divisor & 0xff) << 1); - if (clocks < 2 ) { - clocks = 2 ; - } - if (clocks > 6 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 12 ) & 0x7 ) + 0 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0x7 << 12 ); - dtl |= ((clocks - 0 ) << 12 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 28); - if (value < 0) return -1; - clocks = (value + ((param->divisor & 0xff) << 1) -1)/((param->divisor & 0xff) << 1); - if (clocks < 2 ) { - clocks = 2 ; - } - if (clocks > 4 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 16 ) & 0x7 ) + 0 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0x7 << 16 ); - dtl |= ((clocks - 0 ) << 16 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 30); - if (value < 0) return -1; - clocks = ((value << 1) + param->divisor - 1)/param->divisor; - if (clocks < 5 ) { - clocks = 5 ; - } - if (clocks > 15 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 20 ) & 0xf ) + 0 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0xf << 20 ); - dtl |= ((clocks - 0 ) << 20 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - unsigned clocks, old_clocks; - uint32_t dtl; - int value; - value = spd_read_byte(ctrl->channel0[i], 27); - if (value < 0) return -1; - clocks = (value + ((param->divisor & 0xff) << 1) - 1)/((param->divisor & 0xff) << 1); - if (clocks < 2 ) { - clocks = 2 ; - } - if (clocks > 6 ) { - return -1; - } - dtl = pci_read_config32(ctrl->f2, 0x88 ); - old_clocks = ((dtl >> 24 ) & 0x7 ) + 0 ; - if (old_clocks > clocks) { - clocks = old_clocks; - } - dtl &= ~(0x7 << 24 ); - dtl |= ((clocks - 0 ) << 24 ); - pci_write_config32(ctrl->f2, 0x88 , dtl); - return 0; -} -static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dtl; - dtl = pci_read_config32(ctrl->f2, 0x88 ); - dtl &= ~(0x1 << 28 ); - dtl |= (param->dtl_twr - 2 ) << 28 ; - pci_write_config32(ctrl->f2, 0x88 , dtl); -} -static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dth; - dth = pci_read_config32(ctrl->f2, 0x8c ); - dth &= ~(0x1f << 8 ); - dth |= (param->dch_tref4k << 8 ); - pci_write_config32(ctrl->f2, 0x8c , dth); -} -static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - uint32_t dth; - int value; - unsigned tref, old_tref; - value = spd_read_byte(ctrl->channel0[i], 3); - if (value < 0) return -1; - value &= 0xf; - tref = param->dch_tref8k; - if (value == 12) { - tref = param->dch_tref4k; - } - dth = pci_read_config32(ctrl->f2, 0x8c ); - old_tref = (dth >> 8 ) & 0x1f ; - if ((value == 12) && (old_tref == param->dch_tref4k)) { - tref = param->dch_tref4k; - } else { - tref = param->dch_tref8k; - } - dth &= ~(0x1f << 8 ); - dth |= (tref << 8 ); - pci_write_config32(ctrl->f2, 0x8c , dth); - return 0; -} -static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - uint32_t dcl; - int value; - int dimm; - value = spd_read_byte(ctrl->channel0[i], 13); - if (value < 0) { - return -1; - } - dimm = i; - dimm += 20 ; - dcl = pci_read_config32(ctrl->f2, 0x90 ); - dcl &= ~(1 << dimm); - if (value == 4) { - dcl |= (1 << dimm); - } - pci_write_config32(ctrl->f2, 0x90 , dcl); - return 0; -} -static int update_dimm_ecc(const struct mem_controller *ctrl, const struct mem_param *param, int i) -{ - uint32_t dcl; - int value; - value = spd_read_byte(ctrl->channel0[i], 11); - if (value < 0) { - return -1; - } - if (value != 2) { - dcl = pci_read_config32(ctrl->f2, 0x90 ); - dcl &= ~(1<<17) ; - pci_write_config32(ctrl->f2, 0x90 , dcl); - } - return 0; -} -static int count_dimms(const struct mem_controller *ctrl) -{ - int dimms; - unsigned index; - dimms = 0; - for(index = 0; index < 8; index += 2) { - uint32_t csbase; - csbase = pci_read_config32(ctrl->f2, (0x40 + index << 2)); - if (csbase & 1) { - dimms += 1; - } - } - return dimms; -} -static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dth; - unsigned clocks; - clocks = 1; - dth = pci_read_config32(ctrl->f2, 0x8c ); - dth &= ~(0x1 << 0 ); - dth |= ((clocks - 1 ) << 0 ); - pci_write_config32(ctrl->f2, 0x8c , dth); -} -static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dth, dtl; - unsigned divisor; - unsigned latency; - unsigned clocks; - clocks = 0; - dtl = pci_read_config32(ctrl->f2, 0x88 ); - latency = (dtl >> 0 ) & 0x7 ; - divisor = param->divisor; - if (is_opteron(ctrl)) { - if (latency == 1 ) { - if (divisor == ((6 << 0) + 0)) { - - clocks = 3; - } - else if (divisor > ((6 << 0)+0)) { - - clocks = 2; - } - } - else if (latency == 5 ) { - clocks = 3; - } - else if (latency == 2 ) { - if (divisor == ((6 << 0)+0)) { - - clocks = 4; - } - else if (divisor > ((6 << 0)+0)) { - - clocks = 3; - } - } - } - else { - if (is_registered(ctrl)) { - if (latency == 1 ) { - clocks = 2; - } - else if (latency == 5 ) { - clocks = 3; - } - else if (latency == 2 ) { - clocks = 3; - } - } - else { - if (latency == 1 ) { - clocks = 3; - } - else if (latency == 5 ) { - clocks = 4; - } - else if (latency == 2 ) { - clocks = 4; - } - } - } - if ((clocks < 1 ) || (clocks > 6 )) { - die("Unknown Trwt"); - } - - dth = pci_read_config32(ctrl->f2, 0x8c ); - dth &= ~(0x7 << 4 ); - dth |= ((clocks - 1 ) << 4 ); - pci_write_config32(ctrl->f2, 0x8c , dth); - return; -} -static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param) -{ - - uint32_t dth; - unsigned clocks; - if (is_registered(ctrl)) { - clocks = 2; - } else { - clocks = 1; - } - dth = pci_read_config32(ctrl->f2, 0x8c ); - dth &= ~(0x7 << 20 ); - dth |= ((clocks - 1 ) << 20 ); - pci_write_config32(ctrl->f2, 0x8c , dth); -} -static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dch; - unsigned divisor; - unsigned rdpreamble; - divisor = param->divisor; - dch = pci_read_config32(ctrl->f2, 0x94 ); - dch &= ~(0xf << 8 ); - rdpreamble = 0; - if (is_registered(ctrl)) { - if (divisor == ((10 << 1)+0)) { - - rdpreamble = ((9 << 1)+ 0); - } - else if (divisor == ((7 << 1)+1)) { - - rdpreamble = ((8 << 1)+0); - } - else if (divisor == ((6 << 1)+0)) { - - rdpreamble = ((7 << 1)+1); - } - else if (divisor == ((5 << 1)+0)) { - - rdpreamble = ((7 << 1)+0); - } - } - else { - int slots; - int i; - slots = 0; - for(i = 0; i < 4; i++) { - if (ctrl->channel0[i]) { - slots += 1; - } - } - if (divisor == ((10 << 1)+0)) { - - if (slots <= 2) { - - rdpreamble = ((9 << 1)+0); - } else { - - rdpreamble = ((14 << 1)+0); - } - } - else if (divisor == ((7 << 1)+1)) { - - if (slots <= 2) { - - rdpreamble = ((7 << 1)+0); - } else { - - rdpreamble = ((11 << 1)+0); - } - } - else if (divisor == ((6 << 1)+0)) { - - if (slots <= 2) { - - rdpreamble = ((7 << 1)+0); - } else { - - rdpreamble = ((9 << 1)+0); - } - } - else if (divisor == ((5 << 1)+0)) { - - if (slots <= 2) { - - rdpreamble = ((5 << 1)+0); - } else { - - rdpreamble = ((7 << 1)+0); - } - } - } - if ((rdpreamble < ((2<<1)+0) ) || (rdpreamble > ((9<<1)+1) )) { - die("Unknown rdpreamble"); - } - dch |= (rdpreamble - ((2<<1)+0) ) << 8 ; - pci_write_config32(ctrl->f2, 0x94 , dch); -} -static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dch; - int i; - unsigned async_lat; - int dimms; - dimms = count_dimms(ctrl); - dch = pci_read_config32(ctrl->f2, 0x94 ); - dch &= ~(0xf << 0 ); - async_lat = 0; - if (is_registered(ctrl)) { - if (dimms == 4) { - - async_lat = 9; - } - else { - - async_lat = 8; - } - } - else { - if (dimms > 3) { - die("Too many unbuffered dimms"); - } - else if (dimms == 3) { - - async_lat = 7; - } - else { - - async_lat = 6; - } - } - dch |= ((async_lat - 0 ) << 0 ); - pci_write_config32(ctrl->f2, 0x94 , dch); -} -static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) -{ - uint32_t dch; - - dch = pci_read_config32(ctrl->f2, 0x94 ); - dch &= ~(0x7 << 16 ); - dch |= 3 << 16 ; - dch |= (1 << 19) ; - pci_write_config32(ctrl->f2, 0x94 , dch); -} -static void spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param) -{ - int dimms; - int i; - int rc; - - init_Tref(ctrl, param); - for(i = 0; (i < 4) && ctrl->channel0[i]; i++) { - int rc; - - if (update_dimm_Trc (ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Trfc(ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Trcd(ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Trrd(ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Tras(ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_Trp (ctrl, param, i) < 0) goto dimm_err; - - if (update_dimm_Tref(ctrl, param, i) < 0) goto dimm_err; - - if (update_dimm_x4 (ctrl, param, i) < 0) goto dimm_err; - if (update_dimm_ecc(ctrl, param, i) < 0) goto dimm_err; - continue; - dimm_err: - disable_dimm(ctrl, i); - - } - - set_Twr(ctrl, param); - - set_Twtr(ctrl, param); - set_Trwt(ctrl, param); - set_Twcl(ctrl, param); - - set_read_preamble(ctrl, param); - set_max_async_latency(ctrl, param); - set_idle_cycle_limit(ctrl, param); -} -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - const struct mem_param *param; - spd_enable_2channels(ctrl); - spd_set_ram_size(ctrl); - spd_handle_unbuffered_dimms(ctrl); - param = spd_set_memclk(ctrl); - spd_set_dram_timing(ctrl, param); - order_dimms(ctrl); -} -static void sdram_enable(int controllers, const struct mem_controller *ctrl) -{ - int i; - - for(i = 0; i < controllers; i++) { - uint32_t dch; - dch = pci_read_config32(ctrl[i].f2, 0x94 ); - dch |= (1 << 25) ; - pci_write_config32(ctrl[i].f2, 0x94 , dch); - } - - memreset(controllers, ctrl); - for(i = 0; i < controllers; i++) { - uint32_t dcl; - - dcl = pci_read_config32(ctrl[i].f2, 0x90 ); - if (dcl & (1<<17) ) { - uint32_t mnc; - print_debug("ECC enabled\r\n"); - mnc = pci_read_config32(ctrl[i].f3, 0x44 ); - mnc |= (1 << 22) ; - if (dcl & (1<<16) ) { - mnc |= (1 << 23) ; - } - pci_write_config32(ctrl[i].f3, 0x44 , mnc); - } - dcl |= (1<<3) ; - pci_write_config32(ctrl[i].f2, 0x90 , dcl); - dcl &= ~(1<<3) ; - dcl &= ~(1<<0) ; - dcl &= ~(1<<1) ; - dcl &= ~(1<<2) ; - dcl |= (1<<8) ; - pci_write_config32(ctrl[i].f2, 0x90 , dcl); - } - for(i = 0; i < controllers; i++) { - uint32_t dcl; - print_debug("Initializing memory: "); - int loops = 0; - do { - dcl = pci_read_config32(ctrl[i].f2, 0x90 ); - loops += 1; - if ((loops & 1023) == 0) { - print_debug("."); - } - } while(((dcl & (1<<8) ) != 0) && (loops < 300000 )); - if (loops >= 300000 ) { - print_debug(" failed\r\n"); - } else { - print_debug(" done\r\n"); - } - if (dcl & (1<<17) ) { - print_debug("Clearing memory: "); - if (!is_cpu_pre_c0()) { - - dcl &= ~((1<<11) | (1<<10) ); - pci_write_config32(ctrl[i].f2, 0x90 , dcl); - do { - dcl = pci_read_config32(ctrl[i].f2, 0x90 ); - } while(((dcl & (1<<11) ) == 0) || ((dcl & (1<<10) ) == 0) ); - } - uint32_t base, last_scrub_k, scrub_k; - uint32_t cnt,zstart,zend; - msr_t msr,msr_201; - - pci_write_config32(ctrl[i].f3, 0x58 , - (0 << 16) | (0 << 8) | (0 << 0)); - - msr_201 = rdmsr(0x201); - zstart = pci_read_config32(ctrl[0].f1, 0x40 + (i*8)); - zend = pci_read_config32(ctrl[0].f1, 0x44 + (i*8)); - zstart >>= 16; - zend >>=16; - print_debug("addr "); - print_debug_hex32(zstart); - print_debug("-"); - print_debug_hex32(zend); - print_debug("\r\n"); - - - msr = rdmsr(0x2ff ); - msr.lo &= ~(1<<10); - wrmsr(0x2ff , msr); - - msr = rdmsr(0xc0010015); - msr.lo |= (1<<17); - wrmsr(0xc0010015,msr); - for(;zstart<zend;zstart+=4) { - - if(zstart == 0x0fc) - continue; - - - __asm__ volatile( - "movl %%cr0, %0\n\t" - "orl $0x40000000, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) - ); - - - msr.lo = 1 + ((zstart&0x0ff)<<24); - msr.hi = (zstart&0x0ff00)>>8; - wrmsr(0x200,msr); - - msr.hi = 0x000000ff; - msr.lo = 0xfc000800; - wrmsr(0x201,msr); - - __asm__ volatile( - "movl %%cr0, %0\n\t" - "andl $0x9fffffff, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) - ); - - msr.lo = (zstart&0xff) << 24; - msr.hi = (zstart&0xff00) >> 8; - wrmsr(0xc0000100,msr); - print_debug_char((zstart > 0x0ff)?'+':'-'); - - - __asm__ volatile( - "1: \n\t" - "movl %0, %%fs:(%1)\n\t" - "addl $4,%1\n\t" - "subl $1,%2\n\t" - "jnz 1b\n\t" - : - : "a" (0), "D" (0), "c" (0x01000000) - ); - } - - - __asm__ volatile( - "movl %%cr0, %0\n\t" - "orl $0x40000000, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) - ); - - - msr = rdmsr(0x2ff ); - msr.lo |= 0x0400; - wrmsr(0x2ff , msr); - - msr.lo = 6; - msr.hi = 0; - wrmsr(0x200,msr); - wrmsr(0x201,msr_201); - - msr.lo = 0; - msr.hi = 0; - wrmsr(0xc0000100,msr); - - __asm__ volatile( - "movl %%cr0, %0\n\t" - "andl $0x9fffffff, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) - ); - - - msr = rdmsr(0xc0010015); - msr.lo &= ~(1<<17); - wrmsr(0xc0010015,msr); - - base = pci_read_config32(ctrl[i].f1, 0x40 + (ctrl[i].node_id << 3)); - base &= 0xffff0000; - - pci_write_config32(ctrl[i].f3, 0x5C , base << 8); - pci_write_config32(ctrl[i].f3, 0x60 , base >> 24); - - pci_write_config32(ctrl[i].f3, 0x58 , - (22 << 16) | (22 << 8) | (22 << 0)); - print_debug("done\r\n"); - } - } -} - - - - - -typedef uint8_t u8; -typedef uint32_t u32; -typedef int8_t bool; -static void disable_probes(void) -{ - - - u32 val; - print_debug("Disabling read/write/fill probes for UP... "); - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68); - val |= (1<<10)|(1<<9)|(1<<8)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1 << 0); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68, val); - print_debug("done.\r\n"); -} - -static void wait_ap_stop(u8 node) -{ - unsigned long reg; - unsigned long i; - for(i=0;i< 1000 ;i++) { - unsigned long regx; - regx = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x6c); - if((regx & (1<<4))==1) break; - } - reg = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x6c); - reg &= ~(1<<4); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c, reg); -} -static void notify_bsp_ap_is_stopped(void) -{ - unsigned long reg; - unsigned long apic_id; - apic_id = *((volatile unsigned long *)(0xfee00000 + 0x020 )); - apic_id >>= 24; - - if(apic_id != 0) { - - reg = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ apic_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6C); - reg |= 1<<4; - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ apic_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6C, reg); - } - -} - -static void enable_routing(u8 node) -{ - u32 val; - - - print_debug("Enabling routing table for node "); - print_debug_hex32(node); - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c); - val &= ~((1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c, val); - - if(node!=0) { - wait_ap_stop(node); - } - - print_debug(" done.\r\n"); -} -static void rename_temp_node(u8 node) -{ - uint32_t val; - print_debug("Renaming current temp node to "); - print_debug_hex32(node); - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60); - val &= (~7); - val |= node; - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60, val); - print_debug(" done.\r\n"); -} -static bool check_connection(u8 src, u8 dest, u8 link) -{ - - u32 val; - - - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ src ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x98+link); - if ( (val&0x17) != 0x03) - return 0; - - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ dest ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0); - if(val != 0x11001022) - return 0; - return 1; -} -static void optimize_connection(u8 node1, u8 link1, u8 node2, u8 link2) -{ - static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; - static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; - uint16_t freq_cap1, freq_cap2, freq_cap, freq_mask; - uint8_t width_cap1, width_cap2, width_cap, width, ln_width1, ln_width2; - uint8_t freq; - - - freq_cap1 = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 0x0a ); - freq_cap2 = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 0x0a ); - - - freq = log2(freq_cap1 & freq_cap2 & 0xff); - - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 0x09 , freq); - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 0x09 , freq); - - width_cap1 = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 6 ); - width_cap2 = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 6 ); - - ln_width1 = link_width_to_pow2[width_cap1 & 7]; - ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; - if (ln_width1 > ln_width2) { - ln_width1 = ln_width2; - } - width = pow2_to_link_width[ln_width1]; - - ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; - ln_width2 = link_width_to_pow2[width_cap2 & 7]; - if (ln_width1 > ln_width2) { - ln_width1 = ln_width2; - } - width |= pow2_to_link_width[ln_width1] << 4; - - - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 6 + 1, width); - - width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); - pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 6 + 1, width); -} -static void fill_row(u8 node, u8 row, u32 value) -{ - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x40+(row<<2), value); -} -static void setup_row(u8 source, u8 dest, u8 cpus) -{ - fill_row(source,dest,generate_row(source,dest,cpus)); -} -static void setup_temp_row(u8 source, u8 dest, u8 cpus) -{ - fill_row(source,7,((generate_row( source,dest,cpus )&(~0x0f0000))|0x010000) ); -} -static void setup_node(u8 node, u8 cpus) -{ - u8 row; - for(row=0; row<cpus; row++) - setup_row(node, row, cpus); -} -static void setup_remote_row(u8 source, u8 dest, u8 cpus) -{ - fill_row(7, dest, generate_row(source, dest, cpus)); -} -static void setup_remote_node(u8 node, u8 cpus) -{ - static const uint8_t pci_reg[] = { - 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, - 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78, - 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, - 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, - 0xc4, 0xcc, 0xd4, 0xdc, - 0xc0, 0xc8, 0xd0, 0xd8, - 0xe0, 0xe4, 0xe8, 0xec, - }; - uint8_t row; - int i; - print_debug("setup_remote_node\r\n"); - for(row=0; row<cpus; row++) - setup_remote_row(node, row, cpus); - - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { - uint32_t value; - uint8_t reg; - reg = pci_reg[i]; - value = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) , reg); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) , reg, value); - } - print_debug("setup_remote_done\r\n"); -} -static u8 setup_uniprocessor(void) -{ - print_debug("Enabling UP settings\r\n"); - disable_probes(); - return 1; -} -static u8 setup_smp(void) -{ - u8 cpus=2; - print_debug("Enabling SMP settings\r\n"); - setup_row(0,0,cpus); - - setup_temp_row(0,1,cpus); - - if (!check_connection(0, 7, 0x20 )) { - print_debug("No connection to Node 1.\r\n"); - fill_row( 0 ,7,0x00010101 ) ; - setup_uniprocessor(); - return 1; - } - - optimize_connection(0, 0x20 , 7, 0x20 ); - setup_node(0, cpus); - setup_remote_node(1, cpus); - rename_temp_node(1); - enable_routing(1); - - fill_row( 0 ,7,0x00010101 ) ; - - print_debug_hex32(cpus); - print_debug(" nodes initialized.\r\n"); - return cpus; -} -static unsigned detect_mp_capabilities(unsigned cpus) -{ - unsigned node, row, mask; - bool mp_cap= (-1) ; - print_debug("detect_mp_capabilities: "); - print_debug_hex32(cpus); - print_debug("\r\n"); - if (cpus>2) - mask=0x06; - else - mask=0x02; - for (node=0; node<cpus; node++) { - if ((pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , 0xe8) & mask)!=mask) - mp_cap= (0) ; - } - if (mp_cap) - return cpus; - - print_debug("One of the CPUs is not MP capable. Going back to UP\r\n"); - for (node=cpus; node>0; node--) - for (row=cpus; row>0; row--) - fill_row(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node-1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , row-1, 0x00010101 ); - - return setup_uniprocessor(); -} -static void coherent_ht_finalize(unsigned cpus) -{ - int node; - bool rev_a0; - - - print_debug("coherent_ht_finalize\r\n"); - rev_a0= is_cpu_rev_a0(); - for (node=0; node<cpus; node++) { - u32 val; - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60); - val &= (~0x000F0070); - val |= ((cpus-1)<<16)|((cpus-1)<<4); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x60,val); - val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68); - val |= 0x00008000; - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x68,val); - if (rev_a0) { - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x94,0); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0xb4,0); - pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0xd4,0); - } - } - print_debug("done\r\n"); -} -static int setup_coherent_ht_domain(void) -{ - unsigned cpus; - int reset_needed = 0; - enable_routing(0) ; - cpus=setup_smp(); - cpus=detect_mp_capabilities(cpus); - coherent_ht_finalize(cpus); - - coherent_ht_mainboard(cpus); - return reset_needed; -} -void sdram_no_memory(void) -{ - print_err("No memory!!\r\n"); - while(1) { - hlt(); - } -} - -void sdram_initialize(int controllers, const struct mem_controller *ctrl) -{ - int i; - - for(i = 0; i < controllers; i++) { - print_debug("Ram1."); - print_debug_hex8(i); - print_debug("\r\n"); - sdram_set_registers(ctrl + i); - } - - for(i = 0; i < controllers; i++) { - print_debug("Ram2."); - print_debug_hex8(i); - print_debug("\r\n"); - sdram_set_spd_registers(ctrl + i); - } - - print_debug("Ram3\r\n"); - sdram_enable(controllers, ctrl); - print_debug("Ram4\r\n"); -} -static void enable_lapic(void) -{ - msr_t msr; - msr = rdmsr(0x1b); - msr.hi &= 0xffffff00; - msr.lo &= 0x000007ff; - msr.lo |= 0xfee00000 | (1 << 11); - wrmsr(0x1b, msr); -} -static void stop_this_cpu(void) -{ - unsigned apicid; - apicid = apic_read(0x020 ) >> 24; - - apic_write(0x310 , (( apicid )<<24) ); - apic_write(0x300 , 0x08000 | 0x04000 | 0x00500 ); - - apic_wait_icr_idle(); - - apic_write(0x310 , (( apicid )<<24) ); - apic_write(0x300 , 0x08000 | 0x00500 ); - - apic_wait_icr_idle(); - - for(;;) { - hlt(); - } -} -static void pc87360_enable_serial(void) -{ - pnp_set_logical_device(0x2e , 0x03 ); - pnp_set_enable(0x2e , 1); - pnp_set_iobase0(0x2e , 0x3f8); -} -static void main(void) -{ - - static const struct mem_controller cpu[] = { - { - .node_id = 0, - .f0 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , - .f1 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) , - .f2 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) , - .f3 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, - }, - { - .node_id = 1, - .f0 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x19 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , - .f1 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x19 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) , - .f2 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x19 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) , - .f3 = ( ((( 0 ) & 0xFF) << 16) | ((( 0x19 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, - }, - }; - if (cpu_init_detected()) { - asm("jmp __cpu_reset"); - } - enable_lapic(); - init_timer(); - if (!boot_cpu()) { - stop_this_cpu(); - } - pc87360_enable_serial(); - uart_init(); - console_init(); - setup_default_resource_map(); - setup_coherent_ht_domain(); - enumerate_ht_chain(0); - distinguish_cpu_resets(0); - - enable_smbus(); - memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - -} diff --git a/util/romcc/tests/simple_test.c b/util/romcc/tests/simple_test.c deleted file mode 100644 index 9791d9e352..0000000000 --- a/util/romcc/tests/simple_test.c +++ /dev/null @@ -1,252 +0,0 @@ -void land_test(void) -{ - int i; - i = 1 && 2; -} -void lor_test(void) -{ - int i; - i = 1 || 2; -} - -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned where) -{ - return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3) ; -} - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - -void dummy(void) -{ - uart_tx_byte(5); -} - -#define PIIX4_DEVFN 0x90 -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - - -#define PM_BUS 0 -#define PM_DEVFN (PIIX4_DEVFN+3) - -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - }while((byte &1) == 1); -#if 1 - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } -#endif -} - -#if 0 -void ifthenelse(void) -{ - int i; - if (5 > 2) { - i = 1; - } - else { - i = 2; - } - i = i + 3; -} -#endif -#if 0 -static int add(int left, int right) -{ - { - return left + right; - } -} -#else -#if 0 -static int add(int left, int right) -{ - return left + right; -} -#endif -#endif - -#if 0 -static void assign(void) -{ - int i, j; - i = j = 1; -} -#endif - -#if 0 -static void and(void) -{ - int i, j, k; - i = 1; - j = 2; - k = i && j; - -} -static void and_test(void) -{ - and(); -} -#endif -#if 0 -#define INC_TEST 2 -static void inc(void) -{ - int i; - i = 5; -#if (INC_TEST == 1) - i += 7; -#endif -#if (INC_TEST == 2) - ++i; -#endif -#if (INC_TEST == 3) - i++; -#endif -} - -#if 0 -static void inc_test(void) -{ - inc(); -} -#endif -#endif -#if 0 -static void loop(void) -{ - int i; - for(i = 0; i < 10; i++) { - ; - } while(i < 10); -} - -static void loop_test(void) -{ - loop(); -} -#endif - -#if 0 -static void simple(void) -{ - add(1,2); -} -#endif - -#if 0 -static void fun(void) -{ - int bar; - bar = add(1, 2); -} -#endif - - -#if 0 -static void func(void) -{ - int bar, baz; - int i; - - baz = add(1, 2); - baz = add(1, 2); - bar = 1; - baz = 2; - for(i = 0; i < 10; i = i + 1) { - baz = i; - } - bar = 1 + 2 * 3; - bar = add(3, 4); - bar = add(bar, baz); -} -#endif diff --git a/util/romcc/tests/simple_test1.c b/util/romcc/tests/simple_test1.c deleted file mode 100644 index 9791d9e352..0000000000 --- a/util/romcc/tests/simple_test1.c +++ /dev/null @@ -1,252 +0,0 @@ -void land_test(void) -{ - int i; - i = 1 && 2; -} -void lor_test(void) -{ - int i; - i = 1 || 2; -} - -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned where) -{ - return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3) ; -} - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - -void dummy(void) -{ - uart_tx_byte(5); -} - -#define PIIX4_DEVFN 0x90 -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - - -#define PM_BUS 0 -#define PM_DEVFN (PIIX4_DEVFN+3) - -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - }while((byte &1) == 1); -#if 1 - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } -#endif -} - -#if 0 -void ifthenelse(void) -{ - int i; - if (5 > 2) { - i = 1; - } - else { - i = 2; - } - i = i + 3; -} -#endif -#if 0 -static int add(int left, int right) -{ - { - return left + right; - } -} -#else -#if 0 -static int add(int left, int right) -{ - return left + right; -} -#endif -#endif - -#if 0 -static void assign(void) -{ - int i, j; - i = j = 1; -} -#endif - -#if 0 -static void and(void) -{ - int i, j, k; - i = 1; - j = 2; - k = i && j; - -} -static void and_test(void) -{ - and(); -} -#endif -#if 0 -#define INC_TEST 2 -static void inc(void) -{ - int i; - i = 5; -#if (INC_TEST == 1) - i += 7; -#endif -#if (INC_TEST == 2) - ++i; -#endif -#if (INC_TEST == 3) - i++; -#endif -} - -#if 0 -static void inc_test(void) -{ - inc(); -} -#endif -#endif -#if 0 -static void loop(void) -{ - int i; - for(i = 0; i < 10; i++) { - ; - } while(i < 10); -} - -static void loop_test(void) -{ - loop(); -} -#endif - -#if 0 -static void simple(void) -{ - add(1,2); -} -#endif - -#if 0 -static void fun(void) -{ - int bar; - bar = add(1, 2); -} -#endif - - -#if 0 -static void func(void) -{ - int bar, baz; - int i; - - baz = add(1, 2); - baz = add(1, 2); - bar = 1; - baz = 2; - for(i = 0; i < 10; i = i + 1) { - baz = i; - } - bar = 1 + 2 * 3; - bar = add(3, 4); - bar = add(bar, baz); -} -#endif diff --git a/util/romcc/tests/simple_test10.c b/util/romcc/tests/simple_test10.c deleted file mode 100644 index b2e0ba5219..0000000000 --- a/util/romcc/tests/simple_test10.c +++ /dev/null @@ -1,30 +0,0 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - -static void spd_set_drb(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRB registers which holds the ending memory address assigned - * to each DIMM. - */ - unsigned end_of_memory; - unsigned char device; - - end_of_memory = 0; /* in multiples of 8MiB */ - device = SMBUS_MEM_DEVICE_START; - while (device <= SMBUS_MEM_DEVICE_END) { - unsigned side1_bits, side2_bits; - int byte, byte2; - - side1_bits = side2_bits = -1; - - /* Compute the end address for the DRB register */ - /* Only process dimms < 2GB (2^8 * 8MB) */ - if (side1_bits < 8) { - end_of_memory += (1 << side1_bits); - } - device += SMBUS_MEM_DEVICE_INC; - } -} diff --git a/util/romcc/tests/simple_test11.c b/util/romcc/tests/simple_test11.c deleted file mode 100644 index 7e6b0fbef8..0000000000 --- a/util/romcc/tests/simple_test11.c +++ /dev/null @@ -1,13 +0,0 @@ -static void spd_set_drb(void) -{ - unsigned char ch; - char *str; - str = "test_string"; - ch = *str; - __builtin_outb(ch, 0xab); -} - -void sdram_set_spd_registers(void) -{ - spd_set_drb(); -} diff --git a/util/romcc/tests/simple_test12.c b/util/romcc/tests/simple_test12.c deleted file mode 100644 index cbc00c91ff..0000000000 --- a/util/romcc/tests/simple_test12.c +++ /dev/null @@ -1,8 +0,0 @@ -static void spd_set_drb(void) -{ - unsigned char ch; - char *str; - str = "test_string"; - ch = *str; - __builtin_outb(ch, 0xab); -} diff --git a/util/romcc/tests/simple_test13.c b/util/romcc/tests/simple_test13.c deleted file mode 100644 index 563ba54bc4..0000000000 --- a/util/romcc/tests/simple_test13.c +++ /dev/null @@ -1,23 +0,0 @@ -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -static void uart_init(void) -{ - - int a; - if (1 == 1) { - a = 1; - outb(a, 0x3f8); - } else { - a = 2; - outb(a, 0x3f8); - } - outb(a, 0x3f8); -} - -static void main(void) -{ - uart_init(); -} diff --git a/util/romcc/tests/simple_test14.c b/util/romcc/tests/simple_test14.c deleted file mode 100644 index cc2f67c8a4..0000000000 --- a/util/romcc/tests/simple_test14.c +++ /dev/null @@ -1,288 +0,0 @@ -static void ram_set_registers(void) -{ - static const unsigned int register_values[] = { - 0x000c, 0x00000000, - 0x0010, 0x90000008, - 0x0014, 0x00000000, - 0x002c, 0x74541022, - 0x0030, 0x00000000, - 0x0034, 0x000000a0, - 0x0038, 0x00000000, - 0x0040, 0x00000001, - 0x0044, 0x00000000, - 0x0050, 0x0016000b, - 0x0058, 0x00000000, - 0x0060, 0xd02950e1, - 0x0064, 0x00000000, - 0x00a0, 0x0030c002, - 0x00a4, 0x1f000b77, - 0x00a8, 0x00000b21, - 0x00ac, 0x00000000, - 0x00b0, 0x00000100, - 0x00b4, 0x00010900, - 0x00b8, 0x00000000, - 0x00c0, 0x00600008, - 0x00c4, 0x11110020, - 0x00c8, 0x00000020, - 0x00cc, 0x00350522, - 0x00d0, 0x00350002, - 0x00d4, 0x00000000, - 0x00e0, 0x000d0808, - 0x00e4, 0x000c0808, - 0x00e8, 0x00130f0f, - 0x00ec, 0x00000000, - 0x00f0, 0x00040008, - 0x00f4, 0x00000000, - - - - - - 0x080c, 0x00012000, - 0x0810, 0x00000000, - 0x0818, 0x20010100, - 0x081c, 0x2220c1c1, - 0x0820, 0xe1f0e000, - 0x0824, 0xdff0d800, - 0x0828, 0x00000000, - 0x083c, 0x000c00ff, - 0x0840, 0x00000000, - - - - - - 0x300c, 0x00012000, - 0x3010, 0x00000000, - 0x3018, 0x20020200, - 0x301c, 0x220000f0, - 0x3020, 0xe3f0e200, - 0x3024, 0x0000fff0, - 0x3028, 0x00000000, - 0x3034, 0x000000c0, - 0x3038, 0x00000000, - 0x303c, 0x000600ff, - 0x3040, 0x00000000, - 0x3060, 0x06040000, - 0x3064, 0x00000000, - 0x30c0, 0x0086f008, - 0x30c4, 0x00000020, - 0x30c8, 0x000000d0, - 0x30cc, 0x00010022, - 0x30d0, 0x00000002, - 0x30d4, 0x00000000, - 0x30e0, 0x000d0008, - 0x30e4, 0x000e0008, - 0x30e8, 0x0016000f, - 0x30ec, 0x00000000, - 0x30f0, 0x80000008, - 0x30f4, 0x00000000, - - - - - - 0x3a0c, 0x00002000, - 0x3a10, 0x0000d401, - 0x3a14, 0x00000000, - 0x3a2c, 0x746a1022, - 0x3a30, 0x00000000, - 0x3a3c, 0x0000040c, - 0x3a40, 0x0c050002, - 0x3a44, 0x746a1022, - 0x3a48, 0x00000006, - 0x3a4c, 0x00000000, - - - - - - 0x3b0c, 0x00002000, - 0x3b10, 0x00000000, - 0x3b2c, 0x746b1022, - 0x3b30, 0x00000000, - 0x3b40, 0x84099100, - 0x3b44, 0x00000000, - 0x3b48, 0x00500420, - 0x3b4c, 0x00000000, - 0x3b50, 0x00008101, - 0x3b54, 0xc5ba000f, - 0x3b58, 0x00005001, - 0x3b5c, 0x00000000, - 0x3b60, 0x06800000, - 0x3b64, 0x00000013, - 0x3b68, 0x00000000, - 0x3b70, 0xd54b2906, - 0x3b74, 0x0000000c, - 0x3b78, 0x00000000, - 0x3b7c, 0x746b1022, - 0x3b80, 0x00000000, - 0x3b84, 0x00000001, - 0x3b88, 0x00000000, - 0x3bf0, 0x0072ff93, - 0x3bf4, 0x00000000, - - - - - - 0x900c, 0x00800000, - 0x9010, 0x00000000, - 0x9014, 0x00000000, - 0x9018, 0x00000000, - 0x901C, 0x00000000, - 0x9020, 0x00000000, - 0x9024, 0x00000000, - 0x9028, 0x00000000, - 0x902C, 0x00000000, - 0x9030, 0x00000000, - 0x9034, 0x00000080, - 0x9038, 0x00000000, - 0x903C, 0x00000000, - 0x9040, 0x00010101, - 0x9044, 0x00000000, - 0x9048, 0x00000000, - 0x904C, 0x00000000, - 0x9050, 0x00000000, - 0x9054, 0x00000000, - 0x9058, 0x00000000, - 0x905C, 0x00000000, - 0x9060, 0x00000000, - 0x9064, 0x000000e4, - 0x9068, 0x0f008c0f, - 0x906c, 0x0000002c, - 0x9070, 0x00000000, - 0x9074, 0x00000000, - 0x9078, 0x00000000, - 0x907C, 0x00000000, - 0x9080, 0x21010008, - 0x9084, 0x11110020, - 0x9088, 0x80750522, - 0x908c, 0x00000002, - 0x9090, 0x02510456, - 0x9094, 0x00ff0000, - 0x9098, 0x00000007, - 0x909c, 0x00000000, - 0x90a0, 0x00000000, - 0x90a4, 0x00000000, - 0x90a8, 0x00000000, - 0x90aC, 0x00000000, - 0x90b0, 0x00000000, - 0x90b4, 0x00000000, - 0x90b8, 0x00000000, - 0x90bC, 0x00000000, - 0x90c0, 0x00000000, - 0x90c4, 0x00000000, - 0x90c8, 0x00000000, - 0x90cC, 0x00000000, - - - - - 0x910c, 0x00800000, - 0x9110, 0x00000000, - 0x9140, 0x00000003, - 0x9144, 0x001f0000, - 0x9148, 0x00200000, - 0x914c, 0x00000001, - 0x9150, 0x00200000, - 0x9154, 0x00000002, - 0x9158, 0x00200000, - 0x915c, 0x00000003, - 0x9160, 0x00200000, - 0x9164, 0x00000004, - 0x9168, 0x00200000, - 0x916c, 0x00000005, - 0x9170, 0x00200000, - 0x9174, 0x00000006, - 0x9178, 0x00200000, - 0x917c, 0x00000007, - 0x9180, 0x00e00003, - 0x9184, 0x00e1ff00, - 0x9188, 0x00d80003, - 0x918c, 0x00dfff00, - 0x9190, 0x00e20003, - 0x9194, 0x00e3ff00, - 0x9198, 0x00000000, - 0x91b0, 0x00000a03, - 0x91b4, 0x00000b00, - 0x91b8, 0x00200003, - 0x91bc, 0x00fe0b00, - 0x91c0, 0x0000c003, - 0x91c4, 0x0000c000, - 0x91c8, 0x00001013, - 0x91cc, 0x000ff000, - 0x91d0, 0x00000000, - 0x91e0, 0xff000003, - 0x91e4, 0x00000000, - 0x9200, 0x11021022, - 0x9204, 0x00000000, - 0x9208, 0x06000000, - 0x920c, 0x00800000, - 0x9210, 0x00000000, - 0x9240, 0x00000001, - 0x9244, 0x00800001, - 0x9248, 0x01000001, - 0x924c, 0x01800001, - 0x9250, 0x00000000, - 0x9260, 0x0060fe00, - 0x9270, 0x00000000, - 0x9280, 0x00000022, - 0x9284, 0x00000000, - 0x9288, 0x03623125, - 0x928c, 0x00000130, - 0x9290, 0x080c8000, - 0x9294, 0x0e2b0a06, - 0x9298, 0x00000000, - 0x92b0, 0xd1e8eb05, - 0x92b4, 0x000000cc, - 0x92b8, 0xdfbfe7ad, - 0x92bc, 0xdf4bdfae, - 0x92c0, 0x00000003, - 0x92c4, 0x00000000, - 0x92cc, 0x9f1f0000, - 0x92d0, 0xfbf177f5, - 0x92d4, 0x3fefda0e, - 0x92d8, 0x33bd35dc, - 0x92dc, 0x578d89c1, - 0x92e0, 0xdae70105, - 0x92e4, 0xfa835cfc, - 0x92e8, 0x404e87e6, - 0x92ec, 0xba35df44, - 0x92f0, 0x00000000, - - - - - - 0x930c, 0x00800000, - 0x9310, 0x00000000, - 0x9340, 0x00003bff, - 0x9344, 0x00000040, - 0x9348, 0x00000000, - 0x935c, 0xfe3fb540, - 0x9360, 0x00000090, - 0x9364, 0x00000000, - 0x9370, 0x51020111, - 0x9374, 0x50008011, - 0x9378, 0x08003800, - 0x937c, 0x0000221b, - 0x9380, 0x21272321, - 0x9384, 0x00232123, - 0x9388, 0x00000000, - 0x9390, 0x00000005, - 0x9394, 0x00000068, - 0x9398, 0x001fe800, - 0x939c, 0x00000000, - 0x93b8, 0xe000001d, - 0x93bc, 0x000000bb, - 0x93c0, 0x00000000, - 0x93d4, 0x000d0001, - 0x93d8, 0x00000000, - 0x93e4, 0x00001520, - 0x93e8, 0x00000108, - 0x93ec, 0x00000000, - }; - int max; - max = sizeof(register_values); -} diff --git a/util/romcc/tests/simple_test15.c b/util/romcc/tests/simple_test15.c deleted file mode 100644 index d02eaefd35..0000000000 --- a/util/romcc/tests/simple_test15.c +++ /dev/null @@ -1,47 +0,0 @@ -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -static unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} -static int uart_can_tx_byte(void) -{ - return inb(0x3f8 + 0x05) & 0x20; -} - -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -static void uart_wait_until_sent(void) -{ - while(!(inb(0x3f8 + 0x05) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, 0x3f8 + 0x00); - - uart_wait_until_sent(); -} - -static void print_debug(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - uart_tx_byte(ch); - } -} - -static void main(void) -{ - print_debug("one\r\n"); - print_debug("two\r\n"); -} diff --git a/util/romcc/tests/simple_test16.c b/util/romcc/tests/simple_test16.c deleted file mode 100644 index 0620f1a1d4..0000000000 --- a/util/romcc/tests/simple_test16.c +++ /dev/null @@ -1,18 +0,0 @@ -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; - - -static void outb(uint8_t value, uint16_t port) -{ - __builtin_outb(value, port); -} - - -static void main(void) -{ - uint32_t i; - for(i = 0; i < 32; i++) { - outb(i, 0x80); - } -} diff --git a/util/romcc/tests/simple_test17.c b/util/romcc/tests/simple_test17.c deleted file mode 100644 index 2e3005ea9a..0000000000 --- a/util/romcc/tests/simple_test17.c +++ /dev/null @@ -1,38 +0,0 @@ -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; - - -struct iter { - uint32_t i; -}; - -struct point { - uint32_t i, j; -}; - -static void outb(uint8_t value, uint16_t port) -{ - __builtin_outb(value, port); -} - - -static struct point mkpoint(void) -{ - struct point p; - p.i = 1000; - p.j = 2000; - return p; -} - -static void main(void) -{ - struct iter iter; - for(iter.i = 0; iter.i < 32; iter.i++) { - outb(iter.i, 0x80); - } - struct point p; - p = mkpoint(); - outb(p.i, 0x80); - outb(p.j, 0x80); -} diff --git a/util/romcc/tests/simple_test18.c b/util/romcc/tests/simple_test18.c deleted file mode 100644 index bd4a3550af..0000000000 --- a/util/romcc/tests/simple_test18.c +++ /dev/null @@ -1,3 +0,0 @@ -static void main(void) -{ -} diff --git a/util/romcc/tests/simple_test19.c b/util/romcc/tests/simple_test19.c deleted file mode 100644 index cb1f4940d7..0000000000 --- a/util/romcc/tests/simple_test19.c +++ /dev/null @@ -1,24 +0,0 @@ -static void hlt(void) -{ - __builtin_hlt(); -} - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void wrmsr(unsigned long index, msr_t msr) -{ - __builtin_wrmsr(index, msr.lo, msr.hi); -} - -static void main(void) -{ - msr_t msr; - msr = rdmsr(0x1234); - msr.lo &= ~(1<<5); - wrmsr(0x1234, msr); -} diff --git a/util/romcc/tests/simple_test2.c b/util/romcc/tests/simple_test2.c deleted file mode 100644 index b576d3064d..0000000000 --- a/util/romcc/tests/simple_test2.c +++ /dev/null @@ -1,36 +0,0 @@ -void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - -#define PIIX4_DEVFN 0x90 -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - - -static void spd_set_drb(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRB registers which holds the ending memory address assigned - * to each DIMM. - */ - unsigned end_of_memory; - unsigned device; - - end_of_memory = 0; /* in multiples of 8MiB */ - device = SMBUS_MEM_DEVICE_START; - while (device <= SMBUS_MEM_DEVICE_END) { - unsigned side1_bits; - - side1_bits = -1; - - /* Compute the end address for the DRB register */ - /* Only process dimms < 2GB (2^8 * 8MB) */ - if (side1_bits < 8) { - end_of_memory += (1 << side1_bits); - } - outl(end_of_memory, 0x1234); - } -} diff --git a/util/romcc/tests/simple_test20.c b/util/romcc/tests/simple_test20.c deleted file mode 100644 index f32aeac8af..0000000000 --- a/util/romcc/tests/simple_test20.c +++ /dev/null @@ -1,148 +0,0 @@ -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -static void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - -static unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -static unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where) -{ - return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3); -} - -static unsigned int pcibios_read_config_dword( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inl(0xCFC); -} - - - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - -void __console_tx_char(unsigned char byte) -{ - uart_tx_byte(byte); -} -void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_char(digit); -} - -void __console_tx_hex32(unsigned int value) -{ - __console_tx_nibble((value >> 28) & 0x0f); - __console_tx_nibble((value >> 24) & 0x0f); - __console_tx_nibble((value >> 20) & 0x0f); - __console_tx_nibble((value >> 16) & 0x0f); - __console_tx_nibble((value >> 12) & 0x0f); - __console_tx_nibble((value >> 8) & 0x0f); - __console_tx_nibble((value >> 4) & 0x0f); - __console_tx_nibble(value & 0x0f); -} - -void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); } - - -void main(void) -{ - unsigned long htic; - htic = pcibios_read_config_dword(0, 0xc0, 0x6c); - print_debug_hex32(htic); -} diff --git a/util/romcc/tests/simple_test21.c b/util/romcc/tests/simple_test21.c deleted file mode 100644 index 7f7b87122b..0000000000 --- a/util/romcc/tests/simple_test21.c +++ /dev/null @@ -1,6 +0,0 @@ - - -static void main(void) -{ - asm("hlt"); -} diff --git a/util/romcc/tests/simple_test22.c b/util/romcc/tests/simple_test22.c deleted file mode 100644 index a67f5fd36c..0000000000 --- a/util/romcc/tests/simple_test22.c +++ /dev/null @@ -1,306 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} - -static struct syscall_result syscall0(unsigned long nr) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr)); - return syscall_return(res); -} - -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - -static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2)); - return syscall_return(res); - -} - - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); - return syscall_return(res); - -} - -static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, unsigned long arg5) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), - "S" (arg4), "D" (arg5)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_fork 2 -#define NR_read 3 -#define NR_write 4 -#define NR_open 5 -#define NR_close 6 -#define NR_waitpid 7 -#define NR_creat 8 -#define NR_link 9 -#define NR_unlink 10 -#define NR_execve 11 -#define NR_chdir 12 -#define NR_time 13 -#define NR_mknod 14 -#define NR_chmod 15 -#define NR_lchown 16 -#define NR_break 17 -#define NR_oldstat 18 -#define NR_lseek 19 -#define NR_getpid 20 -#define NR_mount 21 -#define NR_umount 22 -#define NR_setuid 23 -#define NR_getuid 24 -#define NR_stime 25 -#define NR_ptrace 26 -#define NR_alarm 27 -#define NR_oldfstat 28 -#define NR_pause 29 -#define NR_utime 30 -#define NR_stty 31 -#define NR_gtty 32 -#define NR_access 33 -#define NR_nice 34 -#define NR_ftime 35 -#define NR_sync 36 -#define NR_kill 37 -#define NR_rename 38 -#define NR_mkdir 39 -#define NR_rmdir 40 -#define NR_dup 41 -#define NR_pipe 42 -#define NR_times 43 -#define NR_prof 44 -#define NR_brk 45 -#define NR_setgid 46 -#define NR_getgid 47 -#define NR_signal 48 -#define NR_geteuid 49 -#define NR_getegid 50 -#define NR_acct 51 -#define NR_umount2 52 -#define NR_lock 53 -#define NR_ioctl 54 -#define NR_fcntl 55 -#define NR_mpx 56 -#define NR_setpgid 57 -#define NR_ulimit 58 -#define NR_oldolduname 59 -#define NR_umask 60 -#define NR_chroot 61 -#define NR_ustat 62 -#define NR_dup2 63 -#define NR_getppid 64 -#define NR_getpgrp 65 -#define NR_setsid 66 -#define NR_sigaction 67 -#define NR_sgetmask 68 -#define NR_ssetmask 69 -#define NR_setreuid 70 -#define NR_setregid 71 -#define NR_sigsuspend 72 -#define NR_sigpending 73 -#define NR_sethostname 74 -#define NR_setrlimit 75 -#define NR_getrlimit 76 -#define NR_getrusage 77 -#define NR_gettimeofday 78 -#define NR_settimeofday 79 -#define NR_getgroups 80 -#define NR_setgroups 81 -#define NR_select 82 -#define NR_symlink 83 -#define NR_oldlstat 84 -#define NR_readlink 85 -#define NR_uselib 86 -#define NR_swapon 87 -#define NR_reboot 88 -#define NR_readdir 89 -#define NR_mmap 90 -#define NR_munmap 91 -#define NR_truncate 92 -#define NR_ftruncate 93 -#define NR_fchmod 94 -#define NR_fchown 95 -#define NR_getpriority 96 -#define NR_setpriority 97 -#define NR_profil 98 -#define NR_statfs 99 -#define NR_fstatfs 100 -#define NR_ioperm 101 -#define NR_socketcall 102 -#define NR_syslog 103 -#define NR_setitimer 104 -#define NR_getitimer 105 -#define NR_stat 106 -#define NR_lstat 107 -#define NR_fstat 108 -#define NR_olduname 109 -#define NR_iopl 110 -#define NR_vhangup 111 -#define NR_idle 112 -#define NR_vm86old 113 -#define NR_wait4 114 -#define NR_swapoff 115 -#define NR_sysinfo 116 -#define NR_ipc 117 -#define NR_fsync 118 -#define NR_sigreturn 119 -#define NR_clone 120 -#define NR_setdomainname 121 -#define NR_uname 122 -#define NR_modify_ldt 123 -#define NR_adjtimex 124 -#define NR_mprotect 125 -#define NR_sigprocmask 126 -#define NR_create_module 127 -#define NR_init_module 128 -#define NR_delete_module 129 -#define NR_get_kernel_syms 130 -#define NR_quotactl 131 -#define NR_getpgid 132 -#define NR_fchdir 133 -#define NR_bdflush 134 -#define NR_sysfs 135 -#define NR_personality 136 -#define NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define NR_setfsuid 138 -#define NR_setfsgid 139 -#define NR__llseek 140 -#define NR_getdents 141 -#define NR__newselect 142 -#define NR_flock 143 -#define NR_msync 144 -#define NR_readv 145 -#define NR_writev 146 -#define NR_getsid 147 -#define NR_fdatasync 148 -#define NR__sysctl 149 -#define NR_mlock 150 -#define NR_munlock 151 -#define NR_mlockall 152 -#define NR_munlockall 153 -#define NR_sched_setparam 154 -#define NR_sched_getparam 155 -#define NR_sched_setscheduler 156 -#define NR_sched_getscheduler 157 -#define NR_sched_yield 158 -#define NR_sched_get_priority_max 159 -#define NR_sched_get_priority_min 160 -#define NR_sched_rr_get_interval 161 -#define NR_nanosleep 162 -#define NR_mremap 163 -#define NR_setresuid 164 -#define NR_getresuid 165 -#define NR_vm86 166 -#define NR_query_module 167 -#define NR_poll 168 -#define NR_nfsservctl 169 -#define NR_setresgid 170 -#define NR_getresgid 171 -#define NR_prctl 172 -#define NR_rt_sigreturn 173 -#define NR_rt_sigaction 174 -#define NR_rt_sigprocmask 175 -#define NR_rt_sigpending 176 -#define NR_rt_sigtimedwait 177 -#define NR_rt_sigqueueinfo 178 -#define NR_rt_sigsuspend 179 -#define NR_pread 180 -#define NR_pwrite 181 -#define NR_chown 182 -#define NR_getcwd 183 -#define NR_capget 184 -#define NR_capset 185 -#define NR_sigaltstack 186 -#define NR_sendfile 187 -#define NR_getpmsg 188 /* some people actually want streams */ -#define NR_putpmsg 189 /* some people actually want streams */ -#define NR_vfork 190 - -typedef long ssize_t; -typedef unsigned long size_t; - -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} - -static void main(void) -{ - static const char msg[] = "hello world\r\n"; - write(STDOUT_FILENO, msg, sizeof(msg)); - _exit(0); -} diff --git a/util/romcc/tests/simple_test23.c b/util/romcc/tests/simple_test23.c deleted file mode 100644 index 33acd047a2..0000000000 --- a/util/romcc/tests/simple_test23.c +++ /dev/null @@ -1,18 +0,0 @@ -static void print(char *str) -{ - while(1) { - unsigned char ch; - ch = *str; - if (ch == '\0') { - break; - } - __builtin_outb(ch, 0x1234); - str += 1; - } -} - -static void main(void) -{ - print("hello world\r\n"); - print("how are you today\r\n"); -} diff --git a/util/romcc/tests/simple_test24.c b/util/romcc/tests/simple_test24.c deleted file mode 100644 index 01413c2dad..0000000000 --- a/util/romcc/tests/simple_test24.c +++ /dev/null @@ -1,16 +0,0 @@ -void smbus_read_byte(void) -{ - unsigned char host_status_register; - unsigned char byte; - int result; - - host_status_register = __builtin_inb(0x1234); - - /* read results of transaction */ - byte = __builtin_inb(0x4567); - - result = byte; - if (host_status_register != 0x02) { - result = -1; - } -} diff --git a/util/romcc/tests/simple_test25.c b/util/romcc/tests/simple_test25.c deleted file mode 100644 index 80ddfa6740..0000000000 --- a/util/romcc/tests/simple_test25.c +++ /dev/null @@ -1,109 +0,0 @@ -#define COUNT 26 -static void main(void) -{ - unsigned char a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z; - a = 1; - b = 2; - c = 3; - d = 4; - e = 5; - f = 6; - g = 7; - h = 8; - i = 9; - j = 10; - k = 11; - l = 12; - m = 13; - n = 14; - o = 15; - p = 16; - q = 17; - r = 18; - s = 19; - t = 20; - u = 21; - v = 22; - w = 23; - x = 24; - y = 25; - z = 26; -#if COUNT >= 26 - __builtin_outb(z, 0xab); -#endif -#if COUNT >= 25 - __builtin_outb(y, 0xab); -#endif -#if COUNT >= 24 - __builtin_outb(x, 0xab); -#endif -#if COUNT >= 23 - __builtin_outb(w, 0xab); -#endif -#if COUNT >= 22 - __builtin_outb(v, 0xab); -#endif -#if COUNT >= 21 - __builtin_outb(u, 0xab); -#endif -#if COUNT >= 20 - __builtin_outb(t, 0xab); -#endif -#if COUNT >= 19 - __builtin_outb(s, 0xab); -#endif -#if COUNT >= 18 - __builtin_outb(r, 0xab); -#endif -#if COUNT >= 17 - __builtin_outb(q, 0xab); -#endif -#if COUNT >= 16 - __builtin_outb(p, 0xab); -#endif -#if COUNT >= 15 - __builtin_outb(o, 0xab); -#endif -#if COUNT >= 14 - __builtin_outb(n, 0xab); -#endif -#if COUNT >= 13 - __builtin_outb(m, 0xab); -#endif -#if COUNT >= 12 - __builtin_outb(l, 0xab); -#endif -#if COUNT >= 11 - __builtin_outb(k, 0xab); -#endif -#if COUNT >= 10 - __builtin_outb(j, 0xab); -#endif -#if COUNT >= 9 - __builtin_outb(i, 0xab); -#endif -#if COUNT >= 8 - __builtin_outb(h, 0xab); -#endif -#if COUNT >= 7 - __builtin_outb(g, 0xab); -#endif -#if COUNT >= 6 - __builtin_outb(f, 0xab); -#endif -#if COUNT >= 5 - __builtin_outb(e, 0xab); -#endif -#if COUNT >= 4 - __builtin_outb(d, 0xab); -#endif -#if COUNT >= 3 - __builtin_outb(c, 0xab); -#endif -#if COUNT >= 2 - __builtin_outb(b, 0xab); -#endif -#if COUNT >= 1 - __builtin_outb(a, 0xab); -#endif -} diff --git a/util/romcc/tests/simple_test26.c b/util/romcc/tests/simple_test26.c deleted file mode 100644 index b26bbb2ed7..0000000000 --- a/util/romcc/tests/simple_test26.c +++ /dev/null @@ -1,109 +0,0 @@ -#define COUNT 23 -static void main(void) -{ - unsigned int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z; - a = __builtin_inb(0xab); - b = __builtin_inb(0xab); - c = __builtin_inb(0xab); - d = __builtin_inb(0xab); - e = __builtin_inb(0xab); - f = __builtin_inb(0xab); - g = __builtin_inb(0xab); - h = __builtin_inb(0xab); - i = __builtin_inb(0xab); - j = __builtin_inb(0xab); - k = __builtin_inb(0xab); - l = __builtin_inb(0xab); - m = __builtin_inb(0xab); - n = __builtin_inb(0xab); - o = __builtin_inb(0xab); - p = __builtin_inb(0xab); - q = __builtin_inb(0xab); - r = __builtin_inb(0xab); - s = __builtin_inb(0xab); - t = __builtin_inb(0xab); - u = __builtin_inb(0xab); - v = __builtin_inb(0xab); - w = __builtin_inb(0xab); - x = __builtin_inb(0xab); - y = __builtin_inb(0xab); - z = __builtin_inb(0xab); -#if COUNT >= 26 - __builtin_outb(z, 0xab); -#endif -#if COUNT >= 25 - __builtin_outb(y, 0xab); -#endif -#if COUNT >= 24 - __builtin_outb(x, 0xab); -#endif -#if COUNT >= 23 - __builtin_outb(w, 0xab); -#endif -#if COUNT >= 22 - __builtin_outb(v, 0xab); -#endif -#if COUNT >= 21 - __builtin_outb(u, 0xab); -#endif -#if COUNT >= 20 - __builtin_outb(t, 0xab); -#endif -#if COUNT >= 19 - __builtin_outb(s, 0xab); -#endif -#if COUNT >= 18 - __builtin_outb(r, 0xab); -#endif -#if COUNT >= 17 - __builtin_outb(q, 0xab); -#endif -#if COUNT >= 16 - __builtin_outb(p, 0xab); -#endif -#if COUNT >= 15 - __builtin_outb(o, 0xab); -#endif -#if COUNT >= 14 - __builtin_outb(n, 0xab); -#endif -#if COUNT >= 13 - __builtin_outb(m, 0xab); -#endif -#if COUNT >= 12 - __builtin_outb(l, 0xab); -#endif -#if COUNT >= 11 - __builtin_outb(k, 0xab); -#endif -#if COUNT >= 10 - __builtin_outb(j, 0xab); -#endif -#if COUNT >= 9 - __builtin_outb(i, 0xab); -#endif -#if COUNT >= 8 - __builtin_outb(h, 0xab); -#endif -#if COUNT >= 7 - __builtin_outb(g, 0xab); -#endif -#if COUNT >= 6 - __builtin_outb(f, 0xab); -#endif -#if COUNT >= 5 - __builtin_outb(e, 0xab); -#endif -#if COUNT >= 4 - __builtin_outb(d, 0xab); -#endif -#if COUNT >= 3 - __builtin_outb(c, 0xab); -#endif -#if COUNT >= 2 - __builtin_outb(b, 0xab); -#endif -#if COUNT >= 1 - __builtin_outb(a, 0xab); -#endif -} diff --git a/util/romcc/tests/simple_test27.c b/util/romcc/tests/simple_test27.c deleted file mode 100644 index ac52368061..0000000000 --- a/util/romcc/tests/simple_test27.c +++ /dev/null @@ -1,133 +0,0 @@ -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#if CONFIG_TTYS0_BAUD == 115200 -#define CONFIG_TTYS0_DIV (1) -#else -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) -#endif - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - - -void __console_tx_char(unsigned char byte) -{ - uart_tx_byte(byte); - -} - -void __console_tx_string(char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_char(ch); - } -} - - -void print_debug_char(unsigned char byte) { __console_tx_char(byte); } -void print_debug(char *str) { __console_tx_string(str); } - -void main(void) -{ - static const char msg[] = "hello world\r\n"; - uart_init(); -#if 0 - print_debug(msg); -#endif -#if 1 - print_debug("hello world\r\n"); - print_debug("how are you today\r\n"); -#endif - while(1) { - ; - } -} - -void main2(void) -{ - main(); -} diff --git a/util/romcc/tests/simple_test28.c b/util/romcc/tests/simple_test28.c deleted file mode 100644 index 8d83383124..0000000000 --- a/util/romcc/tests/simple_test28.c +++ /dev/null @@ -1,24 +0,0 @@ -static void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - -static unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - - -static void setup_coherent_ht_domain(void) -{ - static const unsigned int register_values[] = { - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101, - - }; - unsigned long reg; - reg = inl(0xFC); - reg &= register_values[1]; - reg |= register_values[2] & ~register_values[1]; - outl(register_values[0], 0xF8); - outl(reg, 0xFC); -} diff --git a/util/romcc/tests/simple_test29.c b/util/romcc/tests/simple_test29.c deleted file mode 100644 index 7eb8f4fa75..0000000000 --- a/util/romcc/tests/simple_test29.c +++ /dev/null @@ -1,37 +0,0 @@ -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -static unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -static void __console_tx_byte(unsigned char byte) -{ - while(inb(0x3f8 + 0x05)) - ; - outb(byte, 0x3f8 + 0x00); -} - -static void __console_tx_string(int loglevel, const char *str) -{ - if (8 > loglevel) { - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_byte(ch); - } - } -} -static void console_init(void) -{ - static const char console_test[] = - "\r\n\r\nLinuxBIOS-" - "1.1.0" - ".0Fallback" - " " - "Mon Jun 9 18:15:20 MDT 2003" - " starting...\r\n"; - __console_tx_string(6, console_test); -} diff --git a/util/romcc/tests/simple_test3.c b/util/romcc/tests/simple_test3.c deleted file mode 100644 index 864760c418..0000000000 --- a/util/romcc/tests/simple_test3.c +++ /dev/null @@ -1,38 +0,0 @@ -static void spd_set_drb(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRB registers which holds the ending memory address assigned - * to each DIMM. - */ - unsigned end_of_memory; - unsigned device; - - end_of_memory = 0; /* in multiples of 8MiB */ - device = 0x50; - while (device <= 0x53) { - unsigned side1_bits, side2_bits; - int byte, byte2; - - side1_bits = side2_bits = -1; - - /* rows */ - byte = -1; - if (1) { - /* now I have the ram size in bits as a power of two (less 1) */ - /* Make it mulitples of 8MB */ - side1_bits -= 25; - } - - /* Compute the end address for the DRB register */ - /* Only process dimms < 2GB (2^8 * 8MB) */ - if (1) { - end_of_memory += side1_bits; - } - __builtin_outl(end_of_memory, 0x1234); - - if (1) { - end_of_memory += side2_bits; - } - } -} diff --git a/util/romcc/tests/simple_test30.c b/util/romcc/tests/simple_test30.c deleted file mode 100644 index 6130ca7b64..0000000000 --- a/util/romcc/tests/simple_test30.c +++ /dev/null @@ -1,1087 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} - -static struct syscall_result syscall0(unsigned long nr) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr)); - return syscall_return(res); -} - -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - -static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2)); - return syscall_return(res); - -} - - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); - return syscall_return(res); - -} - -static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, unsigned long arg5) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), - "S" (arg4), "D" (arg5)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_fork 2 -#define NR_read 3 -#define NR_write 4 -#define NR_open 5 -#define NR_close 6 -#define NR_waitpid 7 -#define NR_creat 8 -#define NR_link 9 -#define NR_unlink 10 -#define NR_execve 11 -#define NR_chdir 12 -#define NR_time 13 -#define NR_mknod 14 -#define NR_chmod 15 -#define NR_lchown 16 -#define NR_break 17 -#define NR_oldstat 18 -#define NR_lseek 19 -#define NR_getpid 20 -#define NR_mount 21 -#define NR_umount 22 -#define NR_setuid 23 -#define NR_getuid 24 -#define NR_stime 25 -#define NR_ptrace 26 -#define NR_alarm 27 -#define NR_oldfstat 28 -#define NR_pause 29 -#define NR_utime 30 -#define NR_stty 31 -#define NR_gtty 32 -#define NR_access 33 -#define NR_nice 34 -#define NR_ftime 35 -#define NR_sync 36 -#define NR_kill 37 -#define NR_rename 38 -#define NR_mkdir 39 -#define NR_rmdir 40 -#define NR_dup 41 -#define NR_pipe 42 -#define NR_times 43 -#define NR_prof 44 -#define NR_brk 45 -#define NR_setgid 46 -#define NR_getgid 47 -#define NR_signal 48 -#define NR_geteuid 49 -#define NR_getegid 50 -#define NR_acct 51 -#define NR_umount2 52 -#define NR_lock 53 -#define NR_ioctl 54 -#define NR_fcntl 55 -#define NR_mpx 56 -#define NR_setpgid 57 -#define NR_ulimit 58 -#define NR_oldolduname 59 -#define NR_umask 60 -#define NR_chroot 61 -#define NR_ustat 62 -#define NR_dup2 63 -#define NR_getppid 64 -#define NR_getpgrp 65 -#define NR_setsid 66 -#define NR_sigaction 67 -#define NR_sgetmask 68 -#define NR_ssetmask 69 -#define NR_setreuid 70 -#define NR_setregid 71 -#define NR_sigsuspend 72 -#define NR_sigpending 73 -#define NR_sethostname 74 -#define NR_setrlimit 75 -#define NR_getrlimit 76 -#define NR_getrusage 77 -#define NR_gettimeofday 78 -#define NR_settimeofday 79 -#define NR_getgroups 80 -#define NR_setgroups 81 -#define NR_select 82 -#define NR_symlink 83 -#define NR_oldlstat 84 -#define NR_readlink 85 -#define NR_uselib 86 -#define NR_swapon 87 -#define NR_reboot 88 -#define NR_readdir 89 -#define NR_mmap 90 -#define NR_munmap 91 -#define NR_truncate 92 -#define NR_ftruncate 93 -#define NR_fchmod 94 -#define NR_fchown 95 -#define NR_getpriority 96 -#define NR_setpriority 97 -#define NR_profil 98 -#define NR_statfs 99 -#define NR_fstatfs 100 -#define NR_ioperm 101 -#define NR_socketcall 102 -#define NR_syslog 103 -#define NR_setitimer 104 -#define NR_getitimer 105 -#define NR_stat 106 -#define NR_lstat 107 -#define NR_fstat 108 -#define NR_olduname 109 -#define NR_iopl 110 -#define NR_vhangup 111 -#define NR_idle 112 -#define NR_vm86old 113 -#define NR_wait4 114 -#define NR_swapoff 115 -#define NR_sysinfo 116 -#define NR_ipc 117 -#define NR_fsync 118 -#define NR_sigreturn 119 -#define NR_clone 120 -#define NR_setdomainname 121 -#define NR_uname 122 -#define NR_modify_ldt 123 -#define NR_adjtimex 124 -#define NR_mprotect 125 -#define NR_sigprocmask 126 -#define NR_create_module 127 -#define NR_init_module 128 -#define NR_delete_module 129 -#define NR_get_kernel_syms 130 -#define NR_quotactl 131 -#define NR_getpgid 132 -#define NR_fchdir 133 -#define NR_bdflush 134 -#define NR_sysfs 135 -#define NR_personality 136 -#define NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define NR_setfsuid 138 -#define NR_setfsgid 139 -#define NR__llseek 140 -#define NR_getdents 141 -#define NR__newselect 142 -#define NR_flock 143 -#define NR_msync 144 -#define NR_readv 145 -#define NR_writev 146 -#define NR_getsid 147 -#define NR_fdatasync 148 -#define NR__sysctl 149 -#define NR_mlock 150 -#define NR_munlock 151 -#define NR_mlockall 152 -#define NR_munlockall 153 -#define NR_sched_setparam 154 -#define NR_sched_getparam 155 -#define NR_sched_setscheduler 156 -#define NR_sched_getscheduler 157 -#define NR_sched_yield 158 -#define NR_sched_get_priority_max 159 -#define NR_sched_get_priority_min 160 -#define NR_sched_rr_get_interval 161 -#define NR_nanosleep 162 -#define NR_mremap 163 -#define NR_setresuid 164 -#define NR_getresuid 165 -#define NR_vm86 166 -#define NR_query_module 167 -#define NR_poll 168 -#define NR_nfsservctl 169 -#define NR_setresgid 170 -#define NR_getresgid 171 -#define NR_prctl 172 -#define NR_rt_sigreturn 173 -#define NR_rt_sigaction 174 -#define NR_rt_sigprocmask 175 -#define NR_rt_sigpending 176 -#define NR_rt_sigtimedwait 177 -#define NR_rt_sigqueueinfo 178 -#define NR_rt_sigsuspend 179 -#define NR_pread 180 -#define NR_pwrite 181 -#define NR_chown 182 -#define NR_getcwd 183 -#define NR_capget 184 -#define NR_capset 185 -#define NR_sigaltstack 186 -#define NR_sendfile 187 -#define NR_getpmsg 188 /* some people actually want streams */ -#define NR_putpmsg 189 /* some people actually want streams */ -#define NR_vfork 190 - -typedef long ssize_t; -typedef unsigned long size_t; - -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} - -static const char *addr_of_char(unsigned char ch) -{ - static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - return byte + ch; -} - -static void console_tx_byte(unsigned char ch) -{ - write(STDOUT_FILENO, addr_of_char(ch), 1); -} - -static void console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - console_tx_byte(digit); -} - -static void console_tx_char(unsigned char byte) -{ - console_tx_byte(byte); -} - -static void console_tx_hex8(unsigned char value) -{ - console_tx_nibble((value >> 4U) & 0x0fU); - console_tx_nibble(value & 0x0fU); -} - -static void console_tx_hex16(unsigned short value) -{ - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_hex32(unsigned short value) -{ - console_tx_nibble((value >> 28U) & 0x0FU); - console_tx_nibble((value >> 24U) & 0x0FU); - console_tx_nibble((value >> 20U) & 0x0FU); - console_tx_nibble((value >> 16U) & 0x0FU); - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_string(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - console_tx_byte(ch); - } -} - -static void print_debug_char(unsigned char byte) { console_tx_char(byte); } -static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_debug(const char *str) { console_tx_string(str); } - - -static void setup_coherent_ht_domain(void) -{ - static const unsigned int register_values[] = { -#if 1 - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101, -# 983 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f, -# 1005 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4), -# 1082 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020, -# 1127 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200, -# 1148 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000, -# 1182 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000, - - - - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007, -# 1224 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000, -# 1276 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00, -# 1311 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03, - - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003, -# 1350 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000, -# 1380 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000, -# 1421 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000, - ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000, -#else -#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x07) << 8) | \ - ((WHERE) & 0xFF)) - - /* Routing Table Node i - * F0:0x40 i = 0, - * F0:0x44 i = 1, - * F0:0x48 i = 2, - * F0:0x4c i = 3, - * F0:0x50 i = 4, - * F0:0x54 i = 5, - * F0:0x58 i = 6, - * F0:0x5c i = 7 - * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [11: 8] Response Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [19:16] Broadcast route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - */ - PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x48), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x4c), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x50), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x54), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101, - PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101, - - /* Hypetransport Transaction Control Register - * F0:0x68 - * [ 0: 0] Disable read byte probe - * 0 = Probes issues - * 1 = Probes not issued - * [ 1: 1] Disable Read Doubleword probe - * 0 = Probes issued - * 1 = Probes not issued - * [ 2: 2] Disable write byte probes - * 0 = Probes issued - * 1 = Probes not issued - * [ 3: 3] Disable Write Doubleword Probes - * 0 = Probes issued - * 1 = Probes not issued. - * [ 4: 4] Disable Memroy Controller Target Start - * 0 = TgtStart packets are generated - * 1 = TgtStart packets are not generated. - * [ 5: 5] CPU1 Enable - * 0 = Second CPU disabled or not present - * 1 = Second CPU enabled. - * [ 6: 6] CPU Request PassPW - * 0 = CPU requests do not pass posted writes - * 1 = CPU requests pass posted writes. - * [ 7: 7] CPU read Respons PassPW - * 0 = CPU Responses do not pass posted writes - * 1 = CPU responses pass posted writes. - * [ 8: 8] Disable Probe Memory Cancel - * 0 = Probes may generate MemCancels - * 1 = Probes may not generate MemCancels - * [ 9: 9] Disable Remote Probe Memory Cancel. - * 0 = Probes hitting dirty blocks generate memory cancel packets - * 1 = Only probed caches on the same node as the memory controller - * generate cancel packets. - * [10:10] Disable Fill Probe - * 0 = Probes issued for cache fills - * 1 = Probes not issued for cache fills. - * [11:11] Response PassPw - * 0 = Downstream response PassPW based on original request - * 1 = Downstream response PassPW set to 1 - * [12:12] Change ISOC to Ordered - * 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization - * 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering. - * [14:13] Buffer Release Priority select - * 00 = 64 - * 01 = 16 - * 10 = 8 - * 11 = 2 - * [15:15] Limit Coherent HT Configuration Space Range - * 0 = No coherent HT configuration space restrictions - * 1 = Limit coherent HT configuration space based on node count - * [16:16] Local Interrupt Conversion Enable. - * 0 = ExtInt/NMI interrupts unaffected. - * 1 = ExtInt/NMI broadcast interrupts converted to LINT0/1 - * [17:17] APIC Extended Broadcast Enable. - * 0 = APIC broadcast is 0F - * 1 = APIC broadcast is FF - * [18:18] APIC Extended ID Enable - * 0 = APIC ID is 4 bits. - * 1 = APIC ID is 8 bits. - * [19:19] APIC Extended Spurious Vector Enable - * 0 = Lower 4 bits of spurious vector are read-only 1111 - * 1 = Lower 4 bits of spurious vecotr are writeable. - * [20:20] Sequence ID Source Node Enable - * 0 = Normal operation - * 1 = Keep SeqID on routed packets for debugging. - * [22:21] Downstream non-posted request limit - * 00 = No limit - * 01 = Limited to 1 - * 10 = Limited to 4 - * 11 = Limited to 8 - * [23:23] RESERVED - * [25:24] Medium-Priority Bypass Count - * - Maximum # of times a medium priority access can pass a low - * priority access before Medium-Priority mode is disabled for one access. - * [27:26] High-Priority Bypass Count - * - Maximum # of times a high prioirty access can pass a medium or low - * priority access before High-prioirty mode is disabled for one access. - * [28:28] Enable High Priority CPU Reads - * 0 = Cpu reads are medium prioirty - * 1 = Cpu reads are high prioirty - * [29:29] Disable Low Priority Writes - * 0 = Non-isochronous writes are low priority - * 1 = Non-isochronous writes are medium prioirty - * [30:30] Disable High Priority Isochronous writes - * 0 = Isochronous writes are high priority - * 1 = Isochronous writes are medium priority - * [31:31] Disable Medium Priority Isochronous writes - * 0 = Isochronous writes are medium are high - * 1 = With bit 30 set makes Isochrouns writes low priority. - */ - PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00840f, - /* HT Initialization Control Register - * F0:0x6C - * [ 0: 0] Routing Table Disable - * 0 = Packets are routed according to routing tables - * 1 = Packets are routed according to the default link field - * [ 1: 1] Request Disable (BSP should clear this) - * 0 = Request packets may be generated - * 1 = Request packets may not be generated. - * [ 3: 2] Default Link (Read-only) - * 00 = LDT0 - * 01 = LDT1 - * 10 = LDT2 - * 11 = CPU on same node - * [ 4: 4] Cold Reset - * - Scratch bit cleared by a cold reset - * [ 5: 5] BIOS Reset Detect - * - Scratch bit cleared by a cold reset - * [ 6: 6] INIT Detect - * - Scratch bit cleared by a warm or cold reset not by an INIT - * - */ - PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4), - /* LDTi Capabilities Registers - * F0:0x80 i = 0, - * F0:0xA0 i = 1, - * F0:0xC0 i = 2, - */ - /* LDTi Link Control Registrs - * F0:0x84 i = 0, - * F0:0xA4 i = 1, - * F0:0xC4 i = 2, - * [ 1: 1] CRC Flood Enable - * 0 = Do not generate sync packets on CRC error - * 1 = Generate sync packets on CRC error - * [ 2: 2] CRC Start Test (Read-Only) - * [ 3: 3] CRC Force Frame Error - * 0 = Do not generate bad CRC - * 1 = Generate bad CRC - * [ 4: 4] Link Failure - * 0 = No link failure detected - * 1 = Link failure detected - * [ 5: 5] Initialization Complete - * 0 = Initialization not complete - * 1 = Initialization complete - * [ 6: 6] Receiver off - * 0 = Recevier on - * 1 = Receiver off - * [ 7: 7] Transmitter Off - * 0 = Transmitter on - * 1 = Transmitter off - * [ 9: 8] CRC_Error - * 00 = No error - * [0] = 1 Error on byte lane 0 - * [1] = 1 Error on byte lane 1 - * [12:12] Isochrnous Enable (Read-Only) - * [13:13] HT Stop Tristate Enable - * 0 = Driven during an LDTSTOP_L - * 1 = Tristated during and LDTSTOP_L - * [14:14] Extended CTL Time - * 0 = CTL is asserted for 16 bit times during link initialization - * 1 = CTL is asserted for 50us during link initialization - * [18:16] Max Link Width In (Read-Only?) - * 000 = 8 bit link - * 001 = 16bit link - * [19:19] Doubleword Flow Control in (Read-Only) - * 0 = This link does not support doubleword flow control - * 1 = This link supports doubleword flow control - * [22:20] Max Link Width Out (Read-Only?) - * 000 = 8 bit link - * 001 = 16bit link - * [23:23] Doubleworld Flow Control out (Read-Only) - * 0 = This link does not support doubleword flow control - * 1 = This link supports doubleworkd flow control - * [26:24] Link Width In - * 000 = Use 8 bits - * 001 = Use 16 bits - * 010 = reserved - * 011 = Use 32 bits - * 100 = Use 2 bits - * 101 = Use 4 bits - * 110 = reserved - * 111 = Link physically not connected - * [27:27] Doubleword Flow Control In Enable - * 0 = Doubleword flow control disabled - * 1 = Doubleword flow control enabled (Not currently supported) - * [30:28] Link Width Out - * 000 = Use 8 bits - * 001 = Use 16 bits - * 010 = reserved - * 011 = Use 32 bits - * 100 = Use 2 bits - * 101 = Use 4 bits - * 110 = reserved - * 111 = Link physically not connected - * [31:31] Doubleworld Flow Control Out Enable - * 0 = Doubleworld flow control disabled - * 1 = Doubleword flow control enabled (Not currently supported) - */ - PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020, - /* LDTi Frequency/Revision Registers - * F0:0x88 i = 0, - * F0:0xA8 i = 1, - * F0:0xC8 i = 2, - * [ 4: 0] Minor Revision - * Contains the HT Minor revision - * [ 7: 5] Major Revision - * Contains the HT Major revision - * [11: 8] Link Frequency (Takes effect the next time the link is reconnected) - * 0000 = 200Mhz - * 0001 = reserved - * 0010 = 400Mhz - * 0011 = reserved - * 0100 = 600Mhz - * 0101 = 800Mhz - * 0110 = 1000Mhz - * 0111 = reserved - * 1000 = reserved - * 1001 = reserved - * 1010 = reserved - * 1011 = reserved - * 1100 = reserved - * 1101 = reserved - * 1110 = reserved - * 1111 = 100 Mhz - * [15:12] Error (Not currently Implemented) - * [31:16] Indicates the frequency capabilities of the link - * [16] = 1 encoding 0000 of freq supported - * [17] = 1 encoding 0001 of freq supported - * [18] = 1 encoding 0010 of freq supported - * [19] = 1 encoding 0011 of freq supported - * [20] = 1 encoding 0100 of freq supported - * [21] = 1 encoding 0101 of freq supported - * [22] = 1 encoding 0110 of freq supported - * [23] = 1 encoding 0111 of freq supported - * [24] = 1 encoding 1000 of freq supported - * [25] = 1 encoding 1001 of freq supported - * [26] = 1 encoding 1010 of freq supported - * [27] = 1 encoding 1011 of freq supported - * [28] = 1 encoding 1100 of freq supported - * [29] = 1 encoding 1101 of freq supported - * [30] = 1 encoding 1110 of freq supported - * [31] = 1 encoding 1111 of freq supported - */ - PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000200, - /* LDTi Feature Capability - * F0:0x8C i = 0, - * F0:0xAC i = 1, - * F0:0xCC i = 2, - */ - /* LDTi Buffer Count Registers - * F0:0x90 i = 0, - * F0:0xB0 i = 1, - * F0:0xD0 i = 2, - */ - /* LDTi Bus Number Registers - * F0:0x94 i = 0, - * F0:0xB4 i = 1, - * F0:0xD4 i = 2, - * For NonCoherent HT specifies the bus number downstream (behind the host bridge) - * [ 0: 7] Primary Bus Number - * [15: 8] Secondary Bus Number - * [23:15] Subordiante Bus Number - * [31:24] reserved - */ - PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000, - /* LDTi Type Registers - * F0:0x98 i = 0, - * F0:0xB8 i = 1, - * F0:0xD8 i = 2, - */ - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ -#if MEMORY_1024MB - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000, -#endif -#if MEMORY_512MB - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000, -#endif - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003, -#if MEMORY_1024MB - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000, -#endif -#if MEMORY_512MB - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000, -#endif - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp address bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03, -#if MEMORY_1024MB - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003, -#endif -#if MEMORY_512MB - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003, -#endif - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, -#endif - }; - int i; - int max; - print_debug("setting up coherent ht domain....\r\n"); - max = sizeof(register_values)/sizeof(register_values[0]); - for(i = 0; i < max; i += 3) { - unsigned long reg; -#if 1 - print_debug_hex32(register_values[i]); - print_debug(" <-"); - print_debug_hex32(register_values[i+2]); - print_debug("\r\n"); -#endif -#if 0 - reg = pci_read_config32(register_values[i]); - reg &= register_values[i+1]; - reg |= register_values[i+2] & ~register_values[i+1]; - pci_write_config32(register_values[i], reg); -#endif - } - print_debug("done.\r\n"); -} - -static void main(void) -{ - static const char msg[] = "hello world\r\n"; -#if 0 - write(STDOUT_FILENO, msg, sizeof(msg)); -#endif -#if 1 - setup_coherent_ht_domain(); -#endif - _exit(0); -} diff --git a/util/romcc/tests/simple_test31.c b/util/romcc/tests/simple_test31.c deleted file mode 100644 index 4ce77d3f6d..0000000000 --- a/util/romcc/tests/simple_test31.c +++ /dev/null @@ -1,16 +0,0 @@ - -static unsigned pci_locate_device(unsigned addr) -{ - addr &= ~0xff; - for(; addr <= 0x00ffff00; addr += 0x00000100) { - __builtin_outl(addr, 0x12); - } - return addr; -} - -static void main(void) -{ - unsigned long addr; - addr = pci_locate_device(0); - __builtin_outl(addr, 0x12); -} diff --git a/util/romcc/tests/simple_test32.c b/util/romcc/tests/simple_test32.c deleted file mode 100644 index 28dbb8972e..0000000000 --- a/util/romcc/tests/simple_test32.c +++ /dev/null @@ -1,35 +0,0 @@ -void main(void) -{ - unsigned long addr, start, stop; - start = 0x00100000; - stop = 0x00180000; - - - for(addr = start; addr < stop ;) { - unsigned char ch; - const char *str = "\r"; - while((ch = *str++) != '\0') { - while(__builtin_inb(0x3f)) - ; - __builtin_outb(ch, 0x3f8); - - while(__builtin_inb(0x3f)) - ; - } - asm ( - "jmp 2f\n\t" - "1:\n\t" - "testl $0xffff, %0\n\t" - "jz 3f\n\t" - "movnti %0, (%0)\n\t" - "add $4, %0\n\t" - "2:\n\t" - "cmp %2, %0\n\t" - "jl 1b\n\t" - "3:\n\t" - : "=b" (addr) /* outputs */ - : "0" (addr), "r" (stop) /* intputs */ - : /* clobbers */ - ); - }; -} diff --git a/util/romcc/tests/simple_test33.c b/util/romcc/tests/simple_test33.c deleted file mode 100644 index 8ca9f8c08e..0000000000 --- a/util/romcc/tests/simple_test33.c +++ /dev/null @@ -1,39 +0,0 @@ -static void main(void) -{ - unsigned long loops0, loops1, loops2; - unsigned long accum; - - accum = 0; - - loops0 = 10; - do { - unsigned short val; - val = __builtin_inw(0x10e0); - if (((val & 0x08) == 0) || (val == 1)) { - break; - } - } while(--loops0); - if (loops0 < 0) return; - accum += loops0; - - - loops1 = 20; - do { - unsigned short val; - val = __builtin_inw(0x10e0); - if (((val & 0x08) == 0) || (val == 1)) { - break; - } - } while(--loops1); - - loops2 = 30; - do { - unsigned short val; - val = __builtin_inw(0x10e0); - if (((val & 0x08) == 0) || (val == 1)) { - break; - } - } while(--loops2); - - accum += loops1 + loops0; -} diff --git a/util/romcc/tests/simple_test34.c b/util/romcc/tests/simple_test34.c deleted file mode 100644 index 3c2b606fc2..0000000000 --- a/util/romcc/tests/simple_test34.c +++ /dev/null @@ -1,71 +0,0 @@ - -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void uart_tx_byte(unsigned char data) -{ - while(!(__builtin_inb(0x3f8 + 0x05) & 0x20)) - ; - __builtin_outb(data, 0x3f8 + 0x00); - - while(!(__builtin_inb(0x3f8 + 0x05) & 0x40)) - ; -} - - -static void print_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - uart_tx_byte(digit); -} - -static void print_debug_hex32(unsigned int value) -{ - print_nibble((value >> 28U) & 0x0fU); - print_nibble((value >> 24U) & 0x0fU); - print_nibble((value >> 20U) & 0x0fU); - print_nibble((value >> 16U) & 0x0fU); - print_nibble((value >> 12U) & 0x0fU); - print_nibble((value >> 8U) & 0x0fU); - print_nibble((value >> 4U) & 0x0fU); - print_nibble(value & 0x0fU); -} - -static void print_debug(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - uart_tx_byte(ch); - } -} - -static void main(void) -{ - unsigned long start, stop; - msr_t msr; - msr = rdmsr(0xC001001A); - print_debug("TOP_MEM: "); - print_debug_hex32(msr.hi); - print_debug_hex32(msr.lo); - print_debug("\r\n"); - - start = 0; - stop = msr.lo; - print_debug("Testing DRAM : "); - print_debug_hex32(start); - print_debug("-"); - print_debug_hex32(stop); - print_debug("\r\n"); - - print_debug("DRAM verify: "); - print_debug_hex32(start); - print_debug_hex32(stop); -} diff --git a/util/romcc/tests/simple_test35.c b/util/romcc/tests/simple_test35.c deleted file mode 100644 index d60b157f25..0000000000 --- a/util/romcc/tests/simple_test35.c +++ /dev/null @@ -1,9 +0,0 @@ -static void main(void) -{ - __builtin_msr_t msr; - msr = __builtin_rdmsr(0xC001001A); - while(__builtin_inb(0x3fd)) - ; - __builtin_outb(msr.hi, 0x3f8); - -} diff --git a/util/romcc/tests/simple_test36.c b/util/romcc/tests/simple_test36.c deleted file mode 100644 index 53aaf91aed..0000000000 --- a/util/romcc/tests/simple_test36.c +++ /dev/null @@ -1,41 +0,0 @@ -static void order_dimms(void) -{ - unsigned long tom; - - tom = 0; - for(;;) { - - unsigned csbase, csmask; - unsigned size; - unsigned index; - csbase = 0; - - for(index = 0; index < 1; index++) { - csbase = __builtin_inl(0x40); - } - if (csbase == 0) { - break; - } - - - size = csbase; - - csbase = (tom << 21); - - tom += size; - - - csmask = size; - csmask |= 0xfe00; - - - __builtin_outl(csbase, 0xCFC); - - __builtin_outl(0xc260, 0xCF8); - __builtin_outl(csmask, 0xCFC); - } - - tom &= ~0xff000000; - - __builtin_outl(tom, 0x1234); -} diff --git a/util/romcc/tests/simple_test37.c b/util/romcc/tests/simple_test37.c deleted file mode 100644 index d6ddc2ec98..0000000000 --- a/util/romcc/tests/simple_test37.c +++ /dev/null @@ -1,10 +0,0 @@ -static void main(void) -{ - unsigned csbase, csmask; - - csbase = 0x40; - csmask = 0xfe00; - - __builtin_outl(csbase, 0x40); - __builtin_outl(csmask, 0x60); -} diff --git a/util/romcc/tests/simple_test38.c b/util/romcc/tests/simple_test38.c deleted file mode 100644 index 9239664fdf..0000000000 --- a/util/romcc/tests/simple_test38.c +++ /dev/null @@ -1,425 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} - -static struct syscall_result syscall0(unsigned long nr) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr)); - return syscall_return(res); -} - -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - -static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2)); - return syscall_return(res); - -} - - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); - return syscall_return(res); - -} - -static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, unsigned long arg5) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), - "S" (arg4), "D" (arg5)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_fork 2 -#define NR_read 3 -#define NR_write 4 -#define NR_open 5 -#define NR_close 6 -#define NR_waitpid 7 -#define NR_creat 8 -#define NR_link 9 -#define NR_unlink 10 -#define NR_execve 11 -#define NR_chdir 12 -#define NR_time 13 -#define NR_mknod 14 -#define NR_chmod 15 -#define NR_lchown 16 -#define NR_break 17 -#define NR_oldstat 18 -#define NR_lseek 19 -#define NR_getpid 20 -#define NR_mount 21 -#define NR_umount 22 -#define NR_setuid 23 -#define NR_getuid 24 -#define NR_stime 25 -#define NR_ptrace 26 -#define NR_alarm 27 -#define NR_oldfstat 28 -#define NR_pause 29 -#define NR_utime 30 -#define NR_stty 31 -#define NR_gtty 32 -#define NR_access 33 -#define NR_nice 34 -#define NR_ftime 35 -#define NR_sync 36 -#define NR_kill 37 -#define NR_rename 38 -#define NR_mkdir 39 -#define NR_rmdir 40 -#define NR_dup 41 -#define NR_pipe 42 -#define NR_times 43 -#define NR_prof 44 -#define NR_brk 45 -#define NR_setgid 46 -#define NR_getgid 47 -#define NR_signal 48 -#define NR_geteuid 49 -#define NR_getegid 50 -#define NR_acct 51 -#define NR_umount2 52 -#define NR_lock 53 -#define NR_ioctl 54 -#define NR_fcntl 55 -#define NR_mpx 56 -#define NR_setpgid 57 -#define NR_ulimit 58 -#define NR_oldolduname 59 -#define NR_umask 60 -#define NR_chroot 61 -#define NR_ustat 62 -#define NR_dup2 63 -#define NR_getppid 64 -#define NR_getpgrp 65 -#define NR_setsid 66 -#define NR_sigaction 67 -#define NR_sgetmask 68 -#define NR_ssetmask 69 -#define NR_setreuid 70 -#define NR_setregid 71 -#define NR_sigsuspend 72 -#define NR_sigpending 73 -#define NR_sethostname 74 -#define NR_setrlimit 75 -#define NR_getrlimit 76 -#define NR_getrusage 77 -#define NR_gettimeofday 78 -#define NR_settimeofday 79 -#define NR_getgroups 80 -#define NR_setgroups 81 -#define NR_select 82 -#define NR_symlink 83 -#define NR_oldlstat 84 -#define NR_readlink 85 -#define NR_uselib 86 -#define NR_swapon 87 -#define NR_reboot 88 -#define NR_readdir 89 -#define NR_mmap 90 -#define NR_munmap 91 -#define NR_truncate 92 -#define NR_ftruncate 93 -#define NR_fchmod 94 -#define NR_fchown 95 -#define NR_getpriority 96 -#define NR_setpriority 97 -#define NR_profil 98 -#define NR_statfs 99 -#define NR_fstatfs 100 -#define NR_ioperm 101 -#define NR_socketcall 102 -#define NR_syslog 103 -#define NR_setitimer 104 -#define NR_getitimer 105 -#define NR_stat 106 -#define NR_lstat 107 -#define NR_fstat 108 -#define NR_olduname 109 -#define NR_iopl 110 -#define NR_vhangup 111 -#define NR_idle 112 -#define NR_vm86old 113 -#define NR_wait4 114 -#define NR_swapoff 115 -#define NR_sysinfo 116 -#define NR_ipc 117 -#define NR_fsync 118 -#define NR_sigreturn 119 -#define NR_clone 120 -#define NR_setdomainname 121 -#define NR_uname 122 -#define NR_modify_ldt 123 -#define NR_adjtimex 124 -#define NR_mprotect 125 -#define NR_sigprocmask 126 -#define NR_create_module 127 -#define NR_init_module 128 -#define NR_delete_module 129 -#define NR_get_kernel_syms 130 -#define NR_quotactl 131 -#define NR_getpgid 132 -#define NR_fchdir 133 -#define NR_bdflush 134 -#define NR_sysfs 135 -#define NR_personality 136 -#define NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define NR_setfsuid 138 -#define NR_setfsgid 139 -#define NR__llseek 140 -#define NR_getdents 141 -#define NR__newselect 142 -#define NR_flock 143 -#define NR_msync 144 -#define NR_readv 145 -#define NR_writev 146 -#define NR_getsid 147 -#define NR_fdatasync 148 -#define NR__sysctl 149 -#define NR_mlock 150 -#define NR_munlock 151 -#define NR_mlockall 152 -#define NR_munlockall 153 -#define NR_sched_setparam 154 -#define NR_sched_getparam 155 -#define NR_sched_setscheduler 156 -#define NR_sched_getscheduler 157 -#define NR_sched_yield 158 -#define NR_sched_get_priority_max 159 -#define NR_sched_get_priority_min 160 -#define NR_sched_rr_get_interval 161 -#define NR_nanosleep 162 -#define NR_mremap 163 -#define NR_setresuid 164 -#define NR_getresuid 165 -#define NR_vm86 166 -#define NR_query_module 167 -#define NR_poll 168 -#define NR_nfsservctl 169 -#define NR_setresgid 170 -#define NR_getresgid 171 -#define NR_prctl 172 -#define NR_rt_sigreturn 173 -#define NR_rt_sigaction 174 -#define NR_rt_sigprocmask 175 -#define NR_rt_sigpending 176 -#define NR_rt_sigtimedwait 177 -#define NR_rt_sigqueueinfo 178 -#define NR_rt_sigsuspend 179 -#define NR_pread 180 -#define NR_pwrite 181 -#define NR_chown 182 -#define NR_getcwd 183 -#define NR_capget 184 -#define NR_capset 185 -#define NR_sigaltstack 186 -#define NR_sendfile 187 -#define NR_getpmsg 188 /* some people actually want streams */ -#define NR_putpmsg 189 /* some people actually want streams */ -#define NR_vfork 190 - -typedef long ssize_t; -typedef unsigned long size_t; - -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} - -static const char *addr_of_char(unsigned char ch) -{ - static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - return byte + ch; -} - -static void console_tx_byte(unsigned char ch) -{ - write(STDOUT_FILENO, addr_of_char(ch), 1); -} - -static void console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - console_tx_byte(digit); -} - -static void console_tx_char(unsigned char byte) -{ - console_tx_byte(byte); -} - -static void console_tx_hex8(unsigned char value) -{ - console_tx_nibble((value >> 4U) & 0x0fU); - console_tx_nibble(value & 0x0fU); -} - -static void console_tx_hex16(unsigned short value) -{ - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_hex32(unsigned short value) -{ - console_tx_nibble((value >> 28U) & 0x0FU); - console_tx_nibble((value >> 24U) & 0x0FU); - console_tx_nibble((value >> 20U) & 0x0FU); - console_tx_nibble((value >> 16U) & 0x0FU); - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_string(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - console_tx_byte(ch); - } -} - -static void print_debug_char(unsigned char byte) { console_tx_char(byte); } -static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_debug(const char *str) { console_tx_string(str); } - -static void goto_test(void) -{ - int i; - print_debug("goto_test\n"); - - i = 0; - goto bottom; - { - top: - print_debug("i = "); - print_debug_hex8(i); - print_debug("\n"); - - i = i + 1; - } - bottom: - if (i < 10) { - goto top; - } -} - -static void main(void) -{ - goto_test(); - _exit(0); -} diff --git a/util/romcc/tests/simple_test39.c b/util/romcc/tests/simple_test39.c deleted file mode 100644 index 1c67cab590..0000000000 --- a/util/romcc/tests/simple_test39.c +++ /dev/null @@ -1,463 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} - -static struct syscall_result syscall0(unsigned long nr) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr)); - return syscall_return(res); -} - -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - -static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2)); - return syscall_return(res); - -} - - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); - return syscall_return(res); - -} - -static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, unsigned long arg5) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), - "S" (arg4), "D" (arg5)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_fork 2 -#define NR_read 3 -#define NR_write 4 -#define NR_open 5 -#define NR_close 6 -#define NR_waitpid 7 -#define NR_creat 8 -#define NR_link 9 -#define NR_unlink 10 -#define NR_execve 11 -#define NR_chdir 12 -#define NR_time 13 -#define NR_mknod 14 -#define NR_chmod 15 -#define NR_lchown 16 -#define NR_break 17 -#define NR_oldstat 18 -#define NR_lseek 19 -#define NR_getpid 20 -#define NR_mount 21 -#define NR_umount 22 -#define NR_setuid 23 -#define NR_getuid 24 -#define NR_stime 25 -#define NR_ptrace 26 -#define NR_alarm 27 -#define NR_oldfstat 28 -#define NR_pause 29 -#define NR_utime 30 -#define NR_stty 31 -#define NR_gtty 32 -#define NR_access 33 -#define NR_nice 34 -#define NR_ftime 35 -#define NR_sync 36 -#define NR_kill 37 -#define NR_rename 38 -#define NR_mkdir 39 -#define NR_rmdir 40 -#define NR_dup 41 -#define NR_pipe 42 -#define NR_times 43 -#define NR_prof 44 -#define NR_brk 45 -#define NR_setgid 46 -#define NR_getgid 47 -#define NR_signal 48 -#define NR_geteuid 49 -#define NR_getegid 50 -#define NR_acct 51 -#define NR_umount2 52 -#define NR_lock 53 -#define NR_ioctl 54 -#define NR_fcntl 55 -#define NR_mpx 56 -#define NR_setpgid 57 -#define NR_ulimit 58 -#define NR_oldolduname 59 -#define NR_umask 60 -#define NR_chroot 61 -#define NR_ustat 62 -#define NR_dup2 63 -#define NR_getppid 64 -#define NR_getpgrp 65 -#define NR_setsid 66 -#define NR_sigaction 67 -#define NR_sgetmask 68 -#define NR_ssetmask 69 -#define NR_setreuid 70 -#define NR_setregid 71 -#define NR_sigsuspend 72 -#define NR_sigpending 73 -#define NR_sethostname 74 -#define NR_setrlimit 75 -#define NR_getrlimit 76 -#define NR_getrusage 77 -#define NR_gettimeofday 78 -#define NR_settimeofday 79 -#define NR_getgroups 80 -#define NR_setgroups 81 -#define NR_select 82 -#define NR_symlink 83 -#define NR_oldlstat 84 -#define NR_readlink 85 -#define NR_uselib 86 -#define NR_swapon 87 -#define NR_reboot 88 -#define NR_readdir 89 -#define NR_mmap 90 -#define NR_munmap 91 -#define NR_truncate 92 -#define NR_ftruncate 93 -#define NR_fchmod 94 -#define NR_fchown 95 -#define NR_getpriority 96 -#define NR_setpriority 97 -#define NR_profil 98 -#define NR_statfs 99 -#define NR_fstatfs 100 -#define NR_ioperm 101 -#define NR_socketcall 102 -#define NR_syslog 103 -#define NR_setitimer 104 -#define NR_getitimer 105 -#define NR_stat 106 -#define NR_lstat 107 -#define NR_fstat 108 -#define NR_olduname 109 -#define NR_iopl 110 -#define NR_vhangup 111 -#define NR_idle 112 -#define NR_vm86old 113 -#define NR_wait4 114 -#define NR_swapoff 115 -#define NR_sysinfo 116 -#define NR_ipc 117 -#define NR_fsync 118 -#define NR_sigreturn 119 -#define NR_clone 120 -#define NR_setdomainname 121 -#define NR_uname 122 -#define NR_modify_ldt 123 -#define NR_adjtimex 124 -#define NR_mprotect 125 -#define NR_sigprocmask 126 -#define NR_create_module 127 -#define NR_init_module 128 -#define NR_delete_module 129 -#define NR_get_kernel_syms 130 -#define NR_quotactl 131 -#define NR_getpgid 132 -#define NR_fchdir 133 -#define NR_bdflush 134 -#define NR_sysfs 135 -#define NR_personality 136 -#define NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define NR_setfsuid 138 -#define NR_setfsgid 139 -#define NR__llseek 140 -#define NR_getdents 141 -#define NR__newselect 142 -#define NR_flock 143 -#define NR_msync 144 -#define NR_readv 145 -#define NR_writev 146 -#define NR_getsid 147 -#define NR_fdatasync 148 -#define NR__sysctl 149 -#define NR_mlock 150 -#define NR_munlock 151 -#define NR_mlockall 152 -#define NR_munlockall 153 -#define NR_sched_setparam 154 -#define NR_sched_getparam 155 -#define NR_sched_setscheduler 156 -#define NR_sched_getscheduler 157 -#define NR_sched_yield 158 -#define NR_sched_get_priority_max 159 -#define NR_sched_get_priority_min 160 -#define NR_sched_rr_get_interval 161 -#define NR_nanosleep 162 -#define NR_mremap 163 -#define NR_setresuid 164 -#define NR_getresuid 165 -#define NR_vm86 166 -#define NR_query_module 167 -#define NR_poll 168 -#define NR_nfsservctl 169 -#define NR_setresgid 170 -#define NR_getresgid 171 -#define NR_prctl 172 -#define NR_rt_sigreturn 173 -#define NR_rt_sigaction 174 -#define NR_rt_sigprocmask 175 -#define NR_rt_sigpending 176 -#define NR_rt_sigtimedwait 177 -#define NR_rt_sigqueueinfo 178 -#define NR_rt_sigsuspend 179 -#define NR_pread 180 -#define NR_pwrite 181 -#define NR_chown 182 -#define NR_getcwd 183 -#define NR_capget 184 -#define NR_capset 185 -#define NR_sigaltstack 186 -#define NR_sendfile 187 -#define NR_getpmsg 188 /* some people actually want streams */ -#define NR_putpmsg 189 /* some people actually want streams */ -#define NR_vfork 190 - -typedef long ssize_t; -typedef unsigned long size_t; - -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} - -static const char *addr_of_char(unsigned char ch) -{ - static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - return byte + ch; -} - -static void console_tx_byte(unsigned char ch) -{ - write(STDOUT_FILENO, addr_of_char(ch), 1); -} - -static void console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - console_tx_byte(digit); -} - -static void console_tx_char(unsigned char byte) -{ - console_tx_byte(byte); -} - -static void console_tx_hex8(unsigned char value) -{ - console_tx_nibble((value >> 4U) & 0x0fU); - console_tx_nibble(value & 0x0fU); -} - -static void console_tx_hex16(unsigned short value) -{ - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_hex32(unsigned short value) -{ - console_tx_nibble((value >> 28U) & 0x0FU); - console_tx_nibble((value >> 24U) & 0x0FU); - console_tx_nibble((value >> 20U) & 0x0FU); - console_tx_nibble((value >> 16U) & 0x0FU); - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_string(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - console_tx_byte(ch); - } -} - -static void print_debug_char(unsigned char byte) { console_tx_char(byte); } -static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_debug(const char *str) { console_tx_string(str); } - -static void goto_test(void) -{ - int i; - print_debug("goto_test\n"); - - i = 0; - goto bottom; - { - top: - print_debug("i = "); - print_debug_hex8(i); - print_debug("\n"); - - i = i + 1; - } - bottom: - if (i < 10) { - goto top; - } -} - -struct socket_desc { - short up; - short down; - short across; -}; - -static void main(void) -{ - static const struct socket_desc cpu_socketsA[] = { - { .up = 2, .down = -1, .across = 1 }, /* Node 0 */ - { .up = 3, .down = -1, .across = 0 }, /* Node 1 */ - { .up = -1, .down = 0, .across = 3 }, /* Node 2 */ - { .up = -1, .down = 1, .across = 2 } /* Node 3 */ - }; - static const struct socket_desc cpu_socketsB[4] = { - { 2, -1, 1 }, /* Node 0 */ - { 3, -1, 0 }, /* Node 1 */ - { -1, 0, 3 }, /* Node 2 */ - { -1, 1, 2 } /* Node 3 */ - }; - int i; - print_debug("cpu_socketA\n"); - for(i = 0; i < sizeof(cpu_socketsA)/sizeof(cpu_socketsA[0]); i++) { - print_debug(".up="); - print_debug_hex16(cpu_socketsA[i].up); - print_debug(" .down="); - print_debug_hex16(cpu_socketsA[i].down); - print_debug(" .across="); - print_debug_hex16(cpu_socketsA[i].across); - print_debug("\n"); - } - print_debug("\ncpu_socketB\n"); - for(i = 0; i < sizeof(cpu_socketsB)/sizeof(cpu_socketsB[0]); i++) { - print_debug(".up="); - print_debug_hex16(cpu_socketsB[i].up); - print_debug(" .down="); - print_debug_hex16(cpu_socketsB[i].down); - print_debug(" .across="); - print_debug_hex16(cpu_socketsB[i].across); - print_debug("\n"); - } - _exit(0); -} diff --git a/util/romcc/tests/simple_test4.c b/util/romcc/tests/simple_test4.c deleted file mode 100644 index bd3f52a822..0000000000 --- a/util/romcc/tests/simple_test4.c +++ /dev/null @@ -1,509 +0,0 @@ -#define HAVE_STRING_SUPPORT 1 -#define HAVE_CAST_SUPPORT 1 -#define HAVE_STATIC_ARRAY_SUPPORT 1 -#define HAVE_POINTER_SUPPORT 1 -#define HAVE_CONSTANT_PROPOGATION 0 -#define CALCULATE_DRB_REG 1 - -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} - -void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} - -unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where) -{ - return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3); -} - -static unsigned char pcibios_read_config_byte( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inb(0xCFC + (where & 3)); -} - -static unsigned short pcibios_read_config_word( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inw(0xCFC + (where & 2)); -} - -static unsigned int pcibios_read_config_dword( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inl(0xCFC); -} - - -static void pcibios_write_config_byte( - unsigned char bus, unsigned devfn, unsigned where, unsigned char value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); -} - -static void pcibios_write_config_word( - unsigned char bus, unsigned devfn, unsigned where, unsigned short value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); -} - -static void pcibios_write_config_dword( - unsigned char bus, unsigned devfn, unsigned where, unsigned int value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outl(value, 0xCFC); -} - -int log2(int value) -{ - /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 - * when the value presented to it is zero. - * Otherwise __builtin_bsr returns the zero based index of - * the highest bit set. - */ - return __builtin_bsr(value); -} - - -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 -#endif - -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif - -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 -#endif - -#define UART_LCS CONFIG_TTYS0_LCS - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - -void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} - -void __console_tx_char(unsigned char byte) -{ - uart_tx_byte(byte); -} -void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_char(digit); -} -void __console_tx_hex8(unsigned char byte) -{ - __console_tx_nibble(byte >> 4); - __console_tx_nibble(byte & 0x0f); -} - -void __console_tx_hex32(unsigned char value) -{ - __console_tx_nibble((value >> 28) & 0x0f); - __console_tx_nibble((value >> 24) & 0x0f); - __console_tx_nibble((value >> 20) & 0x0f); - __console_tx_nibble((value >> 16) & 0x0f); - __console_tx_nibble((value >> 12) & 0x0f); - __console_tx_nibble((value >> 8) & 0x0f); - __console_tx_nibble((value >> 4) & 0x0f); - __console_tx_nibble(value & 0x0f); -} - -#if HAVE_STRING_SUPPORT -void __console_tx_string(char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_char(ch); - } -} -#else -void __console_tx_string(char *str) -{ -} -#endif - - -void print_emerg_char(unsigned char byte) { __console_tx_char(byte); } -void print_emerg_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_emerg_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_emerg(char *str) { __console_tx_string(str); } - -void print_alert_char(unsigned char byte) { __console_tx_char(byte); } -void print_alert_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_alert_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_alert(char *str) { __console_tx_string(str); } - -void print_crit_char(unsigned char byte) { __console_tx_char(byte); } -void print_crit_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_crit_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_crit(char *str) { __console_tx_string(str); } - -void print_err_char(unsigned char byte) { __console_tx_char(byte); } -void print_err_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_err_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_err(char *str) { __console_tx_string(str); } - -void print_warning_char(unsigned char byte) { __console_tx_char(byte); } -void print_warning_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_warning_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_warning(char *str) { __console_tx_string(str); } - -void print_notice_char(unsigned char byte) { __console_tx_char(byte); } -void print_notice_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_notice_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_notice(char *str) { __console_tx_string(str); } - -void print_info_char(unsigned char byte) { __console_tx_char(byte); } -void print_info_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_info_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_info(char *str) { __console_tx_string(str); } - -void print_debug_char(unsigned char byte) { __console_tx_char(byte); } -void print_debug_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_debug(char *str) { __console_tx_string(str); } - -void print_spew_char(unsigned char byte) { __console_tx_char(byte); } -void print_spew_hex8(unsigned char value) { __console_tx_hex8(value); } -void print_spew_hex32(unsigned int value) { __console_tx_hex32(value); } -void print_spew(char *str) { __console_tx_string(str); } - -#define PIIX4_DEVFN 0x90 -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - - -#define PM_BUS 0 -#define PM_DEVFN (PIIX4_DEVFN+3) - -#if HAVE_CONSTANT_PROPOGATION -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 - -static void smbus_wait_until_ready(void) -{ - while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - }while((byte &1) == 1); - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char host_status_register; - unsigned char byte; - int result; - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - - result = byte; - if (host_status_register != 0x02) { - result = -1; - } - return result; -} - -#else /* !HAVE_CONSTANT_PROPOGATION */ - -#define SMBUS_IO_HSTSTAT 0x1000 -#define SMBUS_IO_HSTCTL 0x1002 -#define SMBUS_IO_HSTCMD 0x1003 -#define SMBUS_IO_HSTADD 0x1004 -#define SMBUS_IO_HSTDAT0 0x1005 -#define SMBUS_IO_HSTDAT1 0x1006 -#define SMBUS_IO_HSTBLKDAT 0x1007 - - -static void smbus_wait_until_ready(void) -{ - while((inb(SMBUS_IO_HSTSTAT) & 1) == 1) { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_HSTSTAT); - }while((byte &1) == 1); - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_HSTSTAT); - } -} - -short smbus_read_byte(unsigned char device, unsigned char address) -{ - unsigned char host_status_register; - short result; - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_HSTCTL) & (~1), SMBUS_IO_HSTCTL); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_HSTADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_HSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_HSTCTL) & 0xE3) | 8, SMBUS_IO_HSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_HSTSTAT), SMBUS_IO_HSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_HSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_HSTCTL) | 0x40), SMBUS_IO_HSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_HSTSTAT); - - /* read results of transaction */ - result = inb(SMBUS_IO_HSTDAT0); - - if (host_status_register != 0x02) { - result = -1; - } - return result; -} -#endif /* HAVE_CONSTANT_PROPOGATION */ - -#define I440GX_BUS 0 -#define I440GX_DEVFN ((0x00 << 3) + 0) - - -static void spd_set_drb(void) -{ - /* - * Effects: Uses serial presence detect to set the - * DRB registers which holds the ending memory address assigned - * to each DIMM. - */ - unsigned end_of_memory; - unsigned char device; - unsigned char drb_reg; - - end_of_memory = 0; /* in multiples of 8MiB */ - device = SMBUS_MEM_DEVICE_START; -#if !CALCULATE_DRB_REG - drb_reg = 0x60; -#endif - while (device <= SMBUS_MEM_DEVICE_END) { - unsigned side1_bits, side2_bits; - int byte, byte2; - - side1_bits = side2_bits = -1; - - /* rows */ - byte = smbus_read_byte(device, 3); - if (byte >= 0) { - side1_bits += byte & 0xf; - - /* columns */ - byte = smbus_read_byte(device, 4); - side1_bits += byte & 0xf; - - /* banks */ - byte = smbus_read_byte(device, 17); - side1_bits += log2(byte); - - /* Get the module data width and convert it to a power of two */ - /* low byte */ - byte = smbus_read_byte(device, 6); - - /* high byte */ - byte2 = smbus_read_byte(device, 7); -#if HAVE_CAST_SUPPORT - side1_bits += log2((((unsigned long)byte2 << 8)| byte)); -#else - side1_bits += log2((((byte2 << 8) | byte)); -#endif - - /* now I have the ram size in bits as a power of two (less 1) */ - /* Make it mulitples of 8MB */ - side1_bits -= 25; - - /* side two */ - - /* number of physical banks */ - byte = smbus_read_byte(device, 5); - if (byte > 1) { - /* for now only handle the symmetrical case */ - side2_bits = side1_bits; - } - } - - /* Compute the end address for the DRB register */ - /* Only process dimms < 2GB (2^8 * 8MB) */ - if (side1_bits < 8) { - end_of_memory += (1 << side1_bits); - } -#if CALCULATE_DRB_REG - drb_reg = ((device - SMBUS_MEM_DEVICE_START) << 1) + 0x60; -#endif - -#if HAVE_STRING_SUPPORT - print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n"); -#endif - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg, end_of_memory); - - if (side2_bits < 8 ) { - end_of_memory += (1 << side2_bits); - } -#if HAVE_STRING_SUPPORT - print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n"); -#endif - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg +1, end_of_memory); - -#if !CALCULATE_DRB_REG - drb_reg += 2; -#endif - device += SMBUS_MEM_DEVICE_INC; - } -} diff --git a/util/romcc/tests/simple_test40.c b/util/romcc/tests/simple_test40.c deleted file mode 100644 index 02a3d83e16..0000000000 --- a/util/romcc/tests/simple_test40.c +++ /dev/null @@ -1,6 +0,0 @@ -static void main(void) -{ - int i = 1; - return; - i++; -} diff --git a/util/romcc/tests/simple_test41.c b/util/romcc/tests/simple_test41.c deleted file mode 100644 index 9beee3ec2a..0000000000 --- a/util/romcc/tests/simple_test41.c +++ /dev/null @@ -1,14 +0,0 @@ -static void main(void) -{ - unsigned long a,b,c, d; - volatile unsigned long *val = (volatile unsigned long *)0x1234; - a = val[0]; - b = val[1]; - c = a*b; - val[2] = c; - d = val[3]; - a = c / d; - b = c % d; - val[4] = a; - val[5] = b; -} diff --git a/util/romcc/tests/simple_test43.c b/util/romcc/tests/simple_test43.c deleted file mode 100644 index 464f26f918..0000000000 --- a/util/romcc/tests/simple_test43.c +++ /dev/null @@ -1,47 +0,0 @@ -static void spd_set_memclk(void) -{ - - unsigned min; - unsigned device; - - - min = 0x250; - - - for(device = 0x80; device <= 0x81; device += 1) - { - unsigned cur; - int latency; - unsigned long loops; - - cur = 5 | 0xa0; - latency = __builtin_inw(0xab); - - if (latency > 0x250) { - loops = 1000000; - while(--loops) - ; - if (!loops) { - goto end; - } - - loops = 1000000; - while(--loops) - ; - end: - ; - - } - loops = 1000000; - while(--loops) - ; - - if (latency > 0x250) { - ; - } - - if (cur > 0x250) { - } - } - -} diff --git a/util/romcc/tests/simple_test45.c b/util/romcc/tests/simple_test45.c deleted file mode 100644 index 5e8d742fa8..0000000000 --- a/util/romcc/tests/simple_test45.c +++ /dev/null @@ -1,41 +0,0 @@ -static void spd_set_memclk(void) -{ - unsigned min_cycle_time; - unsigned device; - int new_cycle_time, new_latency; - int index; - int latency; - - min_cycle_time = 0x50; - device = 0x50; - new_cycle_time = 0xa0; - new_latency = 5; - - - latency = 0; - for(index = 0; index < 3; index++, latency++) { - unsigned long loops; - loops = 1000000; - do { - unsigned short val; - val = __builtin_inw(0x10e0); - } while(--loops); - if (!loops) { - continue; - } - - __builtin_outb(device, 0xe4); - __builtin_outb(index, 0xe8); - - loops = 1000000; - while(--loops) - ; - } - if (new_latency > 4){ - return; - } - - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } -} diff --git a/util/romcc/tests/simple_test46.c b/util/romcc/tests/simple_test46.c deleted file mode 100644 index 2d3764e458..0000000000 --- a/util/romcc/tests/simple_test46.c +++ /dev/null @@ -1,41 +0,0 @@ -static void spd_set_memclk(void) -{ - static const int indices[] = { 26, 23, 9 }; - int new_cycle_time, new_latency; - int index; - unsigned min_cycle_time, min_latency; - unsigned device; - - min_cycle_time = 0x50; - min_latency = 2; - device = 0x50; - new_cycle_time = 0xa0; - new_latency = 5; - - for(index = 0; index < 3; index++) { - unsigned long loops; - unsigned long address; - address = indices[index]; - loops = 1000000; - do { - } while(--loops); - if (loops < 0) { - continue; - } - - __builtin_outb(device, 0x10e4); - __builtin_outb(address, 0x10e8); - - loops = 1000000; - if ((loops?0:-1) < 0) { - continue; - } - } - - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - if (new_latency > min_latency) { - min_latency = new_latency; - } -} diff --git a/util/romcc/tests/simple_test47.c b/util/romcc/tests/simple_test47.c deleted file mode 100644 index 2a822d5f84..0000000000 --- a/util/romcc/tests/simple_test47.c +++ /dev/null @@ -1,42 +0,0 @@ -static void spd_set_memclk(void) -{ - unsigned min_cycle_time, min_latency; - unsigned device; - int new_cycle_time, new_latency; - int index; - int latency; - - min_cycle_time = 0x50; - min_latency = 2; - device = 0x50; - new_latency = 5; - new_cycle_time = 0xa0; - latency = 23; - - for(index = 0; index < 3; index++, latency++) { - unsigned long loops; - unsigned address = index; - - loops = 1000000; - do { - } while(--loops); - if (loops) { - continue; - } - - __builtin_outb(device, 0x10e4); - - __builtin_outb(address & 0xFF, 0x10e8); - - loops = 1000000; - while(--loops) - ; - } - - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - if (new_latency > min_latency) { - min_latency = new_latency; - } -} diff --git a/util/romcc/tests/simple_test48.c b/util/romcc/tests/simple_test48.c deleted file mode 100644 index cf9ee8ab0f..0000000000 --- a/util/romcc/tests/simple_test48.c +++ /dev/null @@ -1,13 +0,0 @@ - -static void main(void) -{ - int i; - i = __builtin_inb(0x1234); - goto next; - int j; - j = __builtin_inb(0xabcd); - __builtin_outb(j, 0xef90); - next: - __builtin_outb(i, 0x5678); - -} diff --git a/util/romcc/tests/simple_test49.c b/util/romcc/tests/simple_test49.c deleted file mode 100644 index b18b4cb4b9..0000000000 --- a/util/romcc/tests/simple_test49.c +++ /dev/null @@ -1,15 +0,0 @@ - -static void main(void) -{ - int i; - i = __builtin_inb(0x1234); - if (i == 23) { - for(;;) { - int j; - j = __builtin_inb(0xabcd); - __builtin_outb(j, 0xef90); - } - } - __builtin_outb(i, 0x5678); - -} diff --git a/util/romcc/tests/simple_test5.c b/util/romcc/tests/simple_test5.c deleted file mode 100644 index e744f8f81e..0000000000 --- a/util/romcc/tests/simple_test5.c +++ /dev/null @@ -1,309 +0,0 @@ -#define HAVE_STRING_SUPPORT 0 -#define HAVE_CAST_SUPPORT 0 -#define HAVE_STATIC_ARRAY_SUPPORT 0 -#define HAVE_POINTER_SUPPORT 0 -#define HAVE_CONSTANT_PROPOGATION 0 - -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} - -void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} - -unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where) -{ - return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3); -} - -static unsigned char pcibios_read_config_byte( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inb(0xCFC + (where & 3)); -} - -static unsigned short pcibios_read_config_word( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inw(0xCFC + (where & 2)); -} - -static unsigned int pcibios_read_config_dword( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inl(0xCFC); -} - - -static void pcibios_write_config_byte( - unsigned char bus, unsigned devfn, unsigned where, unsigned char value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); -} - -static void pcibios_write_config_word( - unsigned char bus, unsigned devfn, unsigned where, unsigned short value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); -} - -static void pcibios_write_config_dword( - unsigned char bus, unsigned devfn, unsigned where, unsigned int value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outl(value, 0xCFC); -} - -int log2(int value) -{ - /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 - * when the value presented to it is zero. - * Otherwise __builtin_bsr returns the zero based index of - * the highest bit set. - */ - return __builtin_bsr(value); -} - -#define PIIX4_DEVFN 0x90 -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - - -#define PM_BUS 0 -#define PM_DEVFN (PIIX4_DEVFN+3) - -#if HAVE_CONSTANT_PROPOGATION -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 - -static void smbus_wait_until_ready(void) -{ - while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - }while((byte &1) == 1); - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char host_status_register; - unsigned char byte; - int result; - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - - result = byte; - if (host_status_register != 0x02) { - result = -1; - } - return result; -} - -#else /* !HAVE_CONSTANT_PROPOGATION */ - -#define SMBUS_IO_HSTSTAT 0x1000 -#define SMBUS_IO_HSTCTL 0x1002 -#define SMBUS_IO_HSTCMD 0x1003 -#define SMBUS_IO_HSTADD 0x1004 -#define SMBUS_IO_HSTDAT0 0x1005 -#define SMBUS_IO_HSTDAT1 0x1006 -#define SMBUS_IO_HSTBLKDAT 0x1007 - - -static void smbus_wait_until_ready(void) -{ - while((inb(SMBUS_IO_HSTSTAT) & 1) == 1) { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_HSTSTAT); - }while((byte &1) == 1); - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_HSTSTAT); - } -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char host_status_register; - int result; - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_HSTCTL) & (~1), SMBUS_IO_HSTCTL); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_HSTADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_HSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_HSTCTL) & 0xE3) | 8, SMBUS_IO_HSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_HSTSTAT), SMBUS_IO_HSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_HSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_HSTCTL) | 0x40), SMBUS_IO_HSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_HSTSTAT); - - /* read results of transaction */ - result = inb(SMBUS_IO_HSTDAT0); - - if (host_status_register != 0x02) { - result = -1; - } - return result; -} -#endif /* HAVE_CONSTANT_PROPOGATION */ - - -#define I440GX_BUS 0 -#define I440GX_DEVFN ((0x00 << 3) + 0) - -void sdram_no_memory(void) -{ -#if HAVE_STRING_SUPPORT - print_err("No memory!!\n"); -#endif - while(1) ; -} - -static void spd_enable_refresh(void) -{ - /* - * Effects: Uses serial presence detect to set the - * refresh rate in the DRAMC register. - * see spd_set_dramc for the other values. - * FIXME: Check for illegal/unsupported ram configurations and abort - */ -#if HAVE_STATIC_ARRAY_SUPPORT - static const unsigned char refresh_rates[] = { - 0x01, /* Normal 15.625 us -> 15.6 us */ - 0x05, /* Reduced(.25X) 3.9 us -> 7.8 us */ - 0x05, /* Reduced(.5X) 7.8 us -> 7.8 us */ - 0x02, /* Extended(2x) 31.3 us -> 31.2 us */ - 0x03, /* Extended(4x) 62.5 us -> 62.4 us */ - 0x04, /* Extended(8x) 125 us -> 124.8 us */ - }; -#endif - /* Find the first dimm and assume the rest are the same */ - int status; - int byte; - unsigned device; - unsigned refresh_rate; - byte = -1; - status = -1; - device = SMBUS_MEM_DEVICE_START; - while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) { - byte = smbus_read_byte(device, 12); - device += SMBUS_MEM_DEVICE_INC; - } - if (byte < 0) { - /* We couldn't find anything we must have no memory */ - sdram_no_memory(); - } - byte &= 0x7f; - /* Default refresh rate be conservative */ - refresh_rate = 5; - /* see if the ram refresh is a supported one */ - if (byte < 6) { -#if HAVE_STATIC_ARRAY_SUPPORT - refresh_rate = refresh_rates[byte]; -#endif - } - byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); - byte &= 0xf8; - byte |= refresh_rate; - pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, byte); -} - -void sdram_enable_refresh(void) -{ - spd_enable_refresh(); -} diff --git a/util/romcc/tests/simple_test50.c b/util/romcc/tests/simple_test50.c deleted file mode 100644 index f8d29b716f..0000000000 --- a/util/romcc/tests/simple_test50.c +++ /dev/null @@ -1,43 +0,0 @@ -typedef __builtin_div_t div_t; -typedef __builtin_ldiv_t ldiv_t; -typedef __builtin_udiv_t udiv_t; -typedef __builtin_uldiv_t uldiv_t; - -static div_t div(int numer, int denom) -{ - return __builtin_div(numer, denom); -} -static ldiv_t ldiv(long numer, long denom) -{ - return __builtin_ldiv(numer, denom); -} -static udiv_t udiv(unsigned numer, unsigned denom) -{ - return __builtin_udiv(numer, denom); -} -static uldiv_t uldiv(unsigned long numer, unsigned long denom) -{ - return __builtin_uldiv(numer, denom); -} - -static void main(void) -{ - volatile long *sval = (volatile long *)0x1234; - volatile unsigned long *uval = (volatile unsigned long *)0x5678; - long int a, b, c; - unsigned long e, f, g; - ldiv_t lresult; - uldiv_t ulresult; - - a = sval[0]; - b = sval[1]; - lresult = ldiv(a,b); - sval[2] = lresult.quot; - sval[3] = lresult.rem; - - e = uval[0]; - f = uval[1]; - ulresult = uldiv(e, f); - uval[2] = ulresult.quot; - uval[3] = ulresult.rem; -} diff --git a/util/romcc/tests/simple_test51.c b/util/romcc/tests/simple_test51.c deleted file mode 100644 index 424ed7a0d1..0000000000 --- a/util/romcc/tests/simple_test51.c +++ /dev/null @@ -1,11 +0,0 @@ -static void main(void) -{ - unsigned long a,b,c, d; - volatile unsigned long *val = (volatile unsigned long *)0x1234; - a = val[0]; - b = val[1]; - d = val[2]; - c = a*b; - val[3] = c; - a = c / d; -} diff --git a/util/romcc/tests/simple_test52.c b/util/romcc/tests/simple_test52.c deleted file mode 100644 index 3349de245c..0000000000 --- a/util/romcc/tests/simple_test52.c +++ /dev/null @@ -1,5 +0,0 @@ -static void main(void) -{ - if (__builtin_inb(0x1b)) { - } -} diff --git a/util/romcc/tests/simple_test53.c b/util/romcc/tests/simple_test53.c deleted file mode 100644 index a27f98618d..0000000000 --- a/util/romcc/tests/simple_test53.c +++ /dev/null @@ -1,10 +0,0 @@ -static void main(void) -{ - unsigned dev; - dev = __builtin_inl(0xcd); - if (dev == (0xffffffffU)) { - do { - __builtin_hlt(); - } while(1); - } -} diff --git a/util/romcc/tests/simple_test54.c b/util/romcc/tests/simple_test54.c deleted file mode 100644 index b7dee66bcf..0000000000 --- a/util/romcc/tests/simple_test54.c +++ /dev/null @@ -1,771 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} - -static struct syscall_result syscall0(unsigned long nr) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr)); - return syscall_return(res); -} - -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - -static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2)); - return syscall_return(res); - -} - - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); - return syscall_return(res); - -} - -static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, unsigned long arg5) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), - "S" (arg4), "D" (arg5)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_fork 2 -#define NR_read 3 -#define NR_write 4 -#define NR_open 5 -#define NR_close 6 -#define NR_waitpid 7 -#define NR_creat 8 -#define NR_link 9 -#define NR_unlink 10 -#define NR_execve 11 -#define NR_chdir 12 -#define NR_time 13 -#define NR_mknod 14 -#define NR_chmod 15 -#define NR_lchown 16 -#define NR_break 17 -#define NR_oldstat 18 -#define NR_lseek 19 -#define NR_getpid 20 -#define NR_mount 21 -#define NR_umount 22 -#define NR_setuid 23 -#define NR_getuid 24 -#define NR_stime 25 -#define NR_ptrace 26 -#define NR_alarm 27 -#define NR_oldfstat 28 -#define NR_pause 29 -#define NR_utime 30 -#define NR_stty 31 -#define NR_gtty 32 -#define NR_access 33 -#define NR_nice 34 -#define NR_ftime 35 -#define NR_sync 36 -#define NR_kill 37 -#define NR_rename 38 -#define NR_mkdir 39 -#define NR_rmdir 40 -#define NR_dup 41 -#define NR_pipe 42 -#define NR_times 43 -#define NR_prof 44 -#define NR_brk 45 -#define NR_setgid 46 -#define NR_getgid 47 -#define NR_signal 48 -#define NR_geteuid 49 -#define NR_getegid 50 -#define NR_acct 51 -#define NR_umount2 52 -#define NR_lock 53 -#define NR_ioctl 54 -#define NR_fcntl 55 -#define NR_mpx 56 -#define NR_setpgid 57 -#define NR_ulimit 58 -#define NR_oldolduname 59 -#define NR_umask 60 -#define NR_chroot 61 -#define NR_ustat 62 -#define NR_dup2 63 -#define NR_getppid 64 -#define NR_getpgrp 65 -#define NR_setsid 66 -#define NR_sigaction 67 -#define NR_sgetmask 68 -#define NR_ssetmask 69 -#define NR_setreuid 70 -#define NR_setregid 71 -#define NR_sigsuspend 72 -#define NR_sigpending 73 -#define NR_sethostname 74 -#define NR_setrlimit 75 -#define NR_getrlimit 76 -#define NR_getrusage 77 -#define NR_gettimeofday 78 -#define NR_settimeofday 79 -#define NR_getgroups 80 -#define NR_setgroups 81 -#define NR_select 82 -#define NR_symlink 83 -#define NR_oldlstat 84 -#define NR_readlink 85 -#define NR_uselib 86 -#define NR_swapon 87 -#define NR_reboot 88 -#define NR_readdir 89 -#define NR_mmap 90 -#define NR_munmap 91 -#define NR_truncate 92 -#define NR_ftruncate 93 -#define NR_fchmod 94 -#define NR_fchown 95 -#define NR_getpriority 96 -#define NR_setpriority 97 -#define NR_profil 98 -#define NR_statfs 99 -#define NR_fstatfs 100 -#define NR_ioperm 101 -#define NR_socketcall 102 -#define NR_syslog 103 -#define NR_setitimer 104 -#define NR_getitimer 105 -#define NR_stat 106 -#define NR_lstat 107 -#define NR_fstat 108 -#define NR_olduname 109 -#define NR_iopl 110 -#define NR_vhangup 111 -#define NR_idle 112 -#define NR_vm86old 113 -#define NR_wait4 114 -#define NR_swapoff 115 -#define NR_sysinfo 116 -#define NR_ipc 117 -#define NR_fsync 118 -#define NR_sigreturn 119 -#define NR_clone 120 -#define NR_setdomainname 121 -#define NR_uname 122 -#define NR_modify_ldt 123 -#define NR_adjtimex 124 -#define NR_mprotect 125 -#define NR_sigprocmask 126 -#define NR_create_module 127 -#define NR_init_module 128 -#define NR_delete_module 129 -#define NR_get_kernel_syms 130 -#define NR_quotactl 131 -#define NR_getpgid 132 -#define NR_fchdir 133 -#define NR_bdflush 134 -#define NR_sysfs 135 -#define NR_personality 136 -#define NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define NR_setfsuid 138 -#define NR_setfsgid 139 -#define NR__llseek 140 -#define NR_getdents 141 -#define NR__newselect 142 -#define NR_flock 143 -#define NR_msync 144 -#define NR_readv 145 -#define NR_writev 146 -#define NR_getsid 147 -#define NR_fdatasync 148 -#define NR__sysctl 149 -#define NR_mlock 150 -#define NR_munlock 151 -#define NR_mlockall 152 -#define NR_munlockall 153 -#define NR_sched_setparam 154 -#define NR_sched_getparam 155 -#define NR_sched_setscheduler 156 -#define NR_sched_getscheduler 157 -#define NR_sched_yield 158 -#define NR_sched_get_priority_max 159 -#define NR_sched_get_priority_min 160 -#define NR_sched_rr_get_interval 161 -#define NR_nanosleep 162 -#define NR_mremap 163 -#define NR_setresuid 164 -#define NR_getresuid 165 -#define NR_vm86 166 -#define NR_query_module 167 -#define NR_poll 168 -#define NR_nfsservctl 169 -#define NR_setresgid 170 -#define NR_getresgid 171 -#define NR_prctl 172 -#define NR_rt_sigreturn 173 -#define NR_rt_sigaction 174 -#define NR_rt_sigprocmask 175 -#define NR_rt_sigpending 176 -#define NR_rt_sigtimedwait 177 -#define NR_rt_sigqueueinfo 178 -#define NR_rt_sigsuspend 179 -#define NR_pread 180 -#define NR_pwrite 181 -#define NR_chown 182 -#define NR_getcwd 183 -#define NR_capget 184 -#define NR_capset 185 -#define NR_sigaltstack 186 -#define NR_sendfile 187 -#define NR_getpmsg 188 /* some people actually want streams */ -#define NR_putpmsg 189 /* some people actually want streams */ -#define NR_vfork 190 - -typedef long ssize_t; -typedef unsigned long size_t; - -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} - -static const char *addr_of_char(unsigned char ch) -{ - static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - return byte + ch; -} - -static void console_tx_byte(unsigned char ch) -{ - write(STDOUT_FILENO, addr_of_char(ch), 1); -} - -static void console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - console_tx_byte(digit); -} - -static void console_tx_char(unsigned char byte) -{ - console_tx_byte(byte); -} - -static void console_tx_hex8(unsigned char value) -{ - console_tx_nibble((value >> 4U) & 0x0fU); - console_tx_nibble(value & 0x0fU); -} - -static void console_tx_hex16(unsigned short value) -{ - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_hex32(unsigned short value) -{ - console_tx_nibble((value >> 28U) & 0x0FU); - console_tx_nibble((value >> 24U) & 0x0FU); - console_tx_nibble((value >> 20U) & 0x0FU); - console_tx_nibble((value >> 16U) & 0x0FU); - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_string(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - console_tx_byte(ch); - } -} - -static void print_emerg_char(unsigned char byte) { console_tx_char(byte); } -static void print_emerg_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_emerg_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_emerg_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_emerg(const char *str) { console_tx_string(str); } - -static void print_debug_char(unsigned char byte) { console_tx_char(byte); } -static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_debug(const char *str) { console_tx_string(str); } - - -int log2(int value) -{ - /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 - * when the value presented to it is zero. - * Otherwise __builtin_bsr returns the zero based index of - * the highest bit set. - */ - return __builtin_bsr(value); -} - - -static void die(const char *str) -{ - print_emerg(str); - do { - asm(" "); - } while(1); - -} - -static int smbus_read_byte(unsigned device, unsigned address) -{ - static const unsigned char dimm[] = { -0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01, -0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40, -0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - -0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01, -0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40, -0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }; - return dimm[(device << 8) + address]; -} - -#define SMBUS_MEM_DEVICE_START 0x00 -#define SMBUS_MEM_DEVICE_END 0x01 -#define SMBUS_MEM_DEVICE_INC 1 - -/* Function 2 */ -#define DRAM_CONFIG_HIGH 0x94 -#define DCH_MEMCLK_SHIFT 20 -#define DCH_MEMCLK_MASK 7 -#define DCH_MEMCLK_100MHZ 0 -#define DCH_MEMCLK_133MHZ 2 -#define DCH_MEMCLK_166MHZ 5 -#define DCH_MEMCLK_200MHZ 7 - -/* Function 3 */ -#define NORTHBRIDGE_CAP 0xE8 -#define NBCAP_128Bit 0x0001 -#define NBCAP_MP 0x0002 -#define NBCAP_BIG_MP 0x0004 -#define NBCAP_ECC 0x0004 -#define NBCAP_CHIPKILL_ECC 0x0010 -#define NBCAP_MEMCLK_SHIFT 5 -#define NBCAP_MEMCLK_MASK 3 -#define NBCAP_MEMCLK_100MHZ 3 -#define NBCAP_MEMCLK_133MHZ 2 -#define NBCAP_MEMCLK_166MHZ 1 -#define NBCAP_MEMCLK_200MHZ 0 -#define NBCAP_MEMCTRL 0x0100 - -typedef unsigned char uint8_t; -typedef unsigned int uint32_t; - -static unsigned spd_to_dimm(unsigned device) -{ - return (device - SMBUS_MEM_DEVICE_START); -} - -static void disable_dimm(unsigned index) -{ - print_debug("disabling dimm"); - print_debug_hex8(index); - print_debug("\r\n"); -#if 0 - pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0); - pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+1)<<2), 0); -#endif -} - - -struct mem_param { - uint8_t cycle_time; - uint32_t dch_memclk; -}; - -static const struct mem_param *get_mem_param(unsigned min_cycle_time) -{ - static const struct mem_param speed[] = { - { - .cycle_time = 0xa0, - .dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT, - }, - { - .cycle_time = 0x75, - .dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT, - }, - { - .cycle_time = 0x60, - .dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT, - }, - { - .cycle_time = 0x50, - .dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT, - }, - { - .cycle_time = 0x00, - }, - }; - const struct mem_param *param; - for(param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } - return param; -} - -#if 1 -static void debug(int c) -{ - print_debug_char(c); - print_debug_char('\r'); - print_debug_char('\n'); -} -#endif -static const struct mem_param *spd_set_memclk(void) -{ - /* Compute the minimum cycle time for these dimms */ - const struct mem_param *param; - unsigned min_cycle_time, min_latency; - unsigned device; - uint32_t value; - - static const int latency_indices[] = { 26, 23, 9 }; - static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ - }; - - -#if 0 - value = pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP); -#else - value = 0x50; -#endif - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - min_latency = 2; - -#if 1 - print_debug("min_cycle_time: "); - print_debug_hex8(min_cycle_time); - print_debug(" min_latency: "); - print_debug_hex8(min_latency); - print_debug("\r\n"); -#endif - - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. - */ - for(device = SMBUS_MEM_DEVICE_START; - device <= SMBUS_MEM_DEVICE_END; - device += SMBUS_MEM_DEVICE_INC) - { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - - debug('A'); - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: - * bit 0 == CAS Latency = 1.0 - * bit 1 == CAS Latency = 1.5 - * bit 2 == CAS Latency = 2.0 - * bit 3 == CAS Latency = 2.5 - * bit 4 == CAS Latency = 3.0 - * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD - * bit 7 == TBD - */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = smbus_read_byte(device, 18); - if (latencies <= 0) continue; - - debug('B'); - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for(index = 0; index < 3; index++, latency++) { - int value; - debug('C'); - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { - continue; - } - debug('D'); - value = smbus_read_byte(device, latency_indices[index]); - if (value < 0) continue; - - debug('E'); - /* Only increase the latency if we decreas the clock */ - if ((value >= min_cycle_time) && (value < new_cycle_time)) { - new_cycle_time = value; - new_latency = latency; -#if 1 - print_debug("device: "); - print_debug_hex8(device); - print_debug(" new_cycle_time: "); - print_debug_hex8(new_cycle_time); - print_debug(" new_latency: "); - print_debug_hex8(new_latency); - print_debug("\r\n"); -#endif - } - debug('G'); - } - debug('H'); -#if 1 - print_debug("device: "); - print_debug_hex8(device); - print_debug(" new_cycle_time: "); - print_debug_hex8(new_cycle_time); - print_debug(" new_latency: "); - print_debug_hex8(new_latency); - print_debug("\r\n"); -#endif - if (new_latency > 4){ - continue; - } - debug('I'); - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } -#if 1 - print_debug("device: "); - print_debug_hex8(device); - print_debug(" min_cycle_time: "); - print_debug_hex8(min_cycle_time); - print_debug(" min_latency: "); - print_debug_hex8(min_latency); - print_debug("\r\n"); -#endif - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - for(device = SMBUS_MEM_DEVICE_START; - device <= SMBUS_MEM_DEVICE_END; - device += SMBUS_MEM_DEVICE_INC) - { - int latencies; - int latency; - int index; - int value; - int dimm; - latencies = smbus_read_byte(device, 18); - if (latencies <= 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for(index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { - continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; - } - - /* Read the min_cycle_time for this latency */ - value = smbus_read_byte(device, latency_indices[index]); - - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - disable_dimm(spd_to_dimm(device)); - } -#if 1 - print_debug("min_cycle_time: "); - print_debug_hex8(min_cycle_time); - print_debug(" min_latency: "); - print_debug_hex8(min_latency); - print_debug("\r\n"); -#endif - /* Now that I know the minimum cycle time lookup the memory parameters */ - param = get_mem_param(min_cycle_time); - -#if 0 - /* Update DRAM Config High with our selected memory speed */ - value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH); - value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT); - value |= param->dch_memclk; - pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH, value); - - static const unsigned latencies[] = { 1, 5, 2 }; - /* Update DRAM Timing Low wiht our selected cas latency */ - value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW); - value &= ~7; - value |= latencies[min_latency - 2]; - pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, value); -#endif - - return param; -} - -static void main(void) -{ - const struct mem_param *param; - param = spd_set_memclk(); - _exit(0); -} diff --git a/util/romcc/tests/simple_test55.c b/util/romcc/tests/simple_test55.c deleted file mode 100644 index d5cc2e894c..0000000000 --- a/util/romcc/tests/simple_test55.c +++ /dev/null @@ -1,24 +0,0 @@ -static void main(void) -{ - static const int sdivisor = 20; - const int *pdivisor; - unsigned rdpreamble; - unsigned divisor; - pdivisor = &sdivisor; - divisor = *pdivisor; - rdpreamble = 0; - - if (divisor == 20) { - rdpreamble = 18; - } - else { - if (divisor == 15) { - rdpreamble = 16; - } - else { - if (divisor == 12) { - rdpreamble = 15; - } - } - } -} diff --git a/util/romcc/tests/simple_test56.c b/util/romcc/tests/simple_test56.c deleted file mode 100644 index 570b4eeec3..0000000000 --- a/util/romcc/tests/simple_test56.c +++ /dev/null @@ -1,43 +0,0 @@ - -static void spd_enable_refresh(void) -{ - /* - * Effects: Uses serial presence detect to set the - * refresh rate in the DRAMC register. - * see spd_set_dramc for the other values. - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - static const unsigned char refresh_rates[] = { - 0x01, /* Normal 15.625 us -> 15.6 us */ - 0x05, /* Reduced(.25X) 3.9 us -> 7.8 us */ - 0x05, /* Reduced(.5X) 7.8 us -> 7.8 us */ - 0x02, /* Extended(2x) 31.3 us -> 31.2 us */ - 0x03, /* Extended(4x) 62.5 us -> 62.4 us */ - 0x04, /* Extended(8x) 125 us -> 124.8 us */ - }; - /* Find the first dimm and assume the rest are the same */ - int byte; - unsigned device; - unsigned refresh_rate; - byte = -1; - device = 0x50; - while ((byte < 0) && (device <= 0x57)) { - byte = __builtin_inl(device); - device += 1; - } - if (byte < 0) { - /* We couldn't find anything we must have no memory */ - while(1); - } - byte &= 0x7f; - /* Default refresh rate be conservative */ - refresh_rate = 5; - /* see if the ram refresh is a supported one */ - if (byte < 6) { - refresh_rate = refresh_rates[byte]; - } - byte = __builtin_inb(0x57); - byte &= 0xf8; - byte |= refresh_rate; - __builtin_outb(byte, 0x57); -} diff --git a/util/romcc/tests/simple_test57.c b/util/romcc/tests/simple_test57.c deleted file mode 100644 index 47e2397f17..0000000000 --- a/util/romcc/tests/simple_test57.c +++ /dev/null @@ -1,5 +0,0 @@ -static void main(void) -{ - for(;;) { - } -} diff --git a/util/romcc/tests/simple_test58.c b/util/romcc/tests/simple_test58.c deleted file mode 100644 index a5cd52171c..0000000000 --- a/util/romcc/tests/simple_test58.c +++ /dev/null @@ -1,9 +0,0 @@ -static void main(void) -{ - const char *str; - unsigned char ch; - str = "one\r\n"; - while((ch = *str++) != '\0') { - __builtin_outb(ch, 0x3f0); - } -} diff --git a/util/romcc/tests/simple_test59.c b/util/romcc/tests/simple_test59.c deleted file mode 100644 index a54c0435d3..0000000000 --- a/util/romcc/tests/simple_test59.c +++ /dev/null @@ -1,420 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} - -static struct syscall_result syscall0(unsigned long nr) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr)); - return syscall_return(res); -} - -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - -static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2)); - return syscall_return(res); - -} - - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); - return syscall_return(res); - -} - -static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, unsigned long arg5) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), - "S" (arg4), "D" (arg5)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_fork 2 -#define NR_read 3 -#define NR_write 4 -#define NR_open 5 -#define NR_close 6 -#define NR_waitpid 7 -#define NR_creat 8 -#define NR_link 9 -#define NR_unlink 10 -#define NR_execve 11 -#define NR_chdir 12 -#define NR_time 13 -#define NR_mknod 14 -#define NR_chmod 15 -#define NR_lchown 16 -#define NR_break 17 -#define NR_oldstat 18 -#define NR_lseek 19 -#define NR_getpid 20 -#define NR_mount 21 -#define NR_umount 22 -#define NR_setuid 23 -#define NR_getuid 24 -#define NR_stime 25 -#define NR_ptrace 26 -#define NR_alarm 27 -#define NR_oldfstat 28 -#define NR_pause 29 -#define NR_utime 30 -#define NR_stty 31 -#define NR_gtty 32 -#define NR_access 33 -#define NR_nice 34 -#define NR_ftime 35 -#define NR_sync 36 -#define NR_kill 37 -#define NR_rename 38 -#define NR_mkdir 39 -#define NR_rmdir 40 -#define NR_dup 41 -#define NR_pipe 42 -#define NR_times 43 -#define NR_prof 44 -#define NR_brk 45 -#define NR_setgid 46 -#define NR_getgid 47 -#define NR_signal 48 -#define NR_geteuid 49 -#define NR_getegid 50 -#define NR_acct 51 -#define NR_umount2 52 -#define NR_lock 53 -#define NR_ioctl 54 -#define NR_fcntl 55 -#define NR_mpx 56 -#define NR_setpgid 57 -#define NR_ulimit 58 -#define NR_oldolduname 59 -#define NR_umask 60 -#define NR_chroot 61 -#define NR_ustat 62 -#define NR_dup2 63 -#define NR_getppid 64 -#define NR_getpgrp 65 -#define NR_setsid 66 -#define NR_sigaction 67 -#define NR_sgetmask 68 -#define NR_ssetmask 69 -#define NR_setreuid 70 -#define NR_setregid 71 -#define NR_sigsuspend 72 -#define NR_sigpending 73 -#define NR_sethostname 74 -#define NR_setrlimit 75 -#define NR_getrlimit 76 -#define NR_getrusage 77 -#define NR_gettimeofday 78 -#define NR_settimeofday 79 -#define NR_getgroups 80 -#define NR_setgroups 81 -#define NR_select 82 -#define NR_symlink 83 -#define NR_oldlstat 84 -#define NR_readlink 85 -#define NR_uselib 86 -#define NR_swapon 87 -#define NR_reboot 88 -#define NR_readdir 89 -#define NR_mmap 90 -#define NR_munmap 91 -#define NR_truncate 92 -#define NR_ftruncate 93 -#define NR_fchmod 94 -#define NR_fchown 95 -#define NR_getpriority 96 -#define NR_setpriority 97 -#define NR_profil 98 -#define NR_statfs 99 -#define NR_fstatfs 100 -#define NR_ioperm 101 -#define NR_socketcall 102 -#define NR_syslog 103 -#define NR_setitimer 104 -#define NR_getitimer 105 -#define NR_stat 106 -#define NR_lstat 107 -#define NR_fstat 108 -#define NR_olduname 109 -#define NR_iopl 110 -#define NR_vhangup 111 -#define NR_idle 112 -#define NR_vm86old 113 -#define NR_wait4 114 -#define NR_swapoff 115 -#define NR_sysinfo 116 -#define NR_ipc 117 -#define NR_fsync 118 -#define NR_sigreturn 119 -#define NR_clone 120 -#define NR_setdomainname 121 -#define NR_uname 122 -#define NR_modify_ldt 123 -#define NR_adjtimex 124 -#define NR_mprotect 125 -#define NR_sigprocmask 126 -#define NR_create_module 127 -#define NR_init_module 128 -#define NR_delete_module 129 -#define NR_get_kernel_syms 130 -#define NR_quotactl 131 -#define NR_getpgid 132 -#define NR_fchdir 133 -#define NR_bdflush 134 -#define NR_sysfs 135 -#define NR_personality 136 -#define NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define NR_setfsuid 138 -#define NR_setfsgid 139 -#define NR__llseek 140 -#define NR_getdents 141 -#define NR__newselect 142 -#define NR_flock 143 -#define NR_msync 144 -#define NR_readv 145 -#define NR_writev 146 -#define NR_getsid 147 -#define NR_fdatasync 148 -#define NR__sysctl 149 -#define NR_mlock 150 -#define NR_munlock 151 -#define NR_mlockall 152 -#define NR_munlockall 153 -#define NR_sched_setparam 154 -#define NR_sched_getparam 155 -#define NR_sched_setscheduler 156 -#define NR_sched_getscheduler 157 -#define NR_sched_yield 158 -#define NR_sched_get_priority_max 159 -#define NR_sched_get_priority_min 160 -#define NR_sched_rr_get_interval 161 -#define NR_nanosleep 162 -#define NR_mremap 163 -#define NR_setresuid 164 -#define NR_getresuid 165 -#define NR_vm86 166 -#define NR_query_module 167 -#define NR_poll 168 -#define NR_nfsservctl 169 -#define NR_setresgid 170 -#define NR_getresgid 171 -#define NR_prctl 172 -#define NR_rt_sigreturn 173 -#define NR_rt_sigaction 174 -#define NR_rt_sigprocmask 175 -#define NR_rt_sigpending 176 -#define NR_rt_sigtimedwait 177 -#define NR_rt_sigqueueinfo 178 -#define NR_rt_sigsuspend 179 -#define NR_pread 180 -#define NR_pwrite 181 -#define NR_chown 182 -#define NR_getcwd 183 -#define NR_capget 184 -#define NR_capset 185 -#define NR_sigaltstack 186 -#define NR_sendfile 187 -#define NR_getpmsg 188 /* some people actually want streams */ -#define NR_putpmsg 189 /* some people actually want streams */ -#define NR_vfork 190 - -typedef long ssize_t; -typedef unsigned long size_t; - -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} - -static const char *addr_of_char(unsigned char ch) -{ - static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - return byte + ch; -} - -static void console_tx_byte(unsigned char ch) -{ - write(STDOUT_FILENO, addr_of_char(ch), 1); -} - -static void console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - console_tx_byte(digit); -} - -static void console_tx_char(unsigned char byte) -{ - console_tx_byte(byte); -} - -static void console_tx_hex8(unsigned char value) -{ - console_tx_nibble((value >> 4U) & 0x0fU); - console_tx_nibble(value & 0x0fU); -} - -static void console_tx_hex16(unsigned short value) -{ - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_hex32(unsigned short value) -{ - console_tx_nibble((value >> 28U) & 0x0FU); - console_tx_nibble((value >> 24U) & 0x0FU); - console_tx_nibble((value >> 20U) & 0x0FU); - console_tx_nibble((value >> 16U) & 0x0FU); - console_tx_nibble((value >> 12U) & 0x0FU); - console_tx_nibble((value >> 8U) & 0x0FU); - console_tx_nibble((value >> 4U) & 0x0FU); - console_tx_nibble(value & 0x0FU); -} - -static void console_tx_string(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - console_tx_byte(ch); - } -} - -static void print_emerg_char(unsigned char byte) { console_tx_char(byte); } -static void print_emerg_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_emerg_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_emerg_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_emerg(const char *str) { console_tx_string(str); } - -static void print_debug_char(unsigned char byte) { console_tx_char(byte); } -static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); } -static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); } -static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); } -static void print_debug(const char *str) { console_tx_string(str); } - - -static void main(void) -{ - static const int value[] = { 1 }; - const char *str; - if (value[1]) { - print_debug("A\r\n"); - str = "Unbuffered\r\n"; - } else { - print_debug("B\r\n"); - str = "Registered\r\n"; - } - print_debug(str); - _exit(0); -} diff --git a/util/romcc/tests/simple_test6.c b/util/romcc/tests/simple_test6.c deleted file mode 100644 index 8aee0cdf41..0000000000 --- a/util/romcc/tests/simple_test6.c +++ /dev/null @@ -1,269 +0,0 @@ -#define HAVE_CONSTANT_PROPOGATION 1 - -void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -void outw(unsigned short value, unsigned short port) -{ - __builtin_outw(value, port); -} - -void outl(unsigned int value, unsigned short port) -{ - __builtin_outl(value, port); -} - -unsigned char inb(unsigned short port) -{ - return __builtin_inb(port); -} - -unsigned char inw(unsigned short port) -{ - return __builtin_inw(port); -} - -unsigned char inl(unsigned short port) -{ - return __builtin_inl(port); -} - -static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where) -{ - return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3); -} - -static unsigned char pcibios_read_config_byte( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inb(0xCFC + (where & 3)); -} - -static unsigned short pcibios_read_config_word( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inw(0xCFC + (where & 2)); -} - -static unsigned int pcibios_read_config_dword( - unsigned char bus, unsigned devfn, unsigned where) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - return inl(0xCFC); -} - - -static void pcibios_write_config_byte( - unsigned char bus, unsigned devfn, unsigned where, unsigned char value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); -} - -static void pcibios_write_config_word( - unsigned char bus, unsigned devfn, unsigned where, unsigned short value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); -} - -static void pcibios_write_config_dword( - unsigned char bus, unsigned devfn, unsigned where, unsigned int value) -{ - outl(config_cmd(bus, devfn, where), 0xCF8); - outl(value, 0xCFC); -} - -int log2(int value) -{ - /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 - * when the value presented to it is zero. - * Otherwise __builtin_bsr returns the zero based index of - * the highest bit set. - */ - return __builtin_bsr(value); -} - -#define PIIX4_DEVFN 0x90 -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - - -#define PM_BUS 0 -#define PM_DEVFN (PIIX4_DEVFN+3) - -#if HAVE_CONSTANT_PROPOGATION -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 - -static void smbus_wait_until_ready(void) -{ - while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - }while((byte &1) == 1); - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char host_status_register; - unsigned char byte; - int result; - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - - result = byte; - if (host_status_register != 0x02) { - result = -1; - } - return result; -} - -#else /* !HAVE_CONSTANT_PROPOGATION */ - -#define SMBUS_IO_HSTSTAT 0x1000 -#define SMBUS_IO_HSTCTL 0x1002 -#define SMBUS_IO_HSTCMD 0x1003 -#define SMBUS_IO_HSTADD 0x1004 -#define SMBUS_IO_HSTDAT0 0x1005 -#define SMBUS_IO_HSTDAT1 0x1006 -#define SMBUS_IO_HSTBLKDAT 0x1007 - - -static void smbus_wait_until_ready(void) -{ - while((inb(SMBUS_IO_HSTSTAT) & '\1') == '\1') { - /* nop */ - } -} - -static void smbus_wait_until_done(void) -{ - unsigned char byte; - do { - byte = inb(SMBUS_IO_HSTSTAT); - }while((byte &1) == 1); - while( (byte & ~1) == 0) { - byte = inb(SMBUS_IO_HSTSTAT); - } -} - -short smbus_read_byte(unsigned char device, unsigned char address) -{ - unsigned char host_status_register; - short result; - - smbus_wait_until_ready(); /* 2 */ - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_HSTCTL) & (~1), SMBUS_IO_HSTCTL); /* 3 */ - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_HSTADD); /* 1 + 3 */ - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_HSTCMD); /* 1 + 3 */ - /* set up for a byte data read */ - outb((inb(SMBUS_IO_HSTCTL) & 0xE3) | 8, SMBUS_IO_HSTCTL); /* 3 */ - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_HSTSTAT), SMBUS_IO_HSTSTAT); /* 3 */ - - /* clear the data byte...*/ - outb(0, SMBUS_IO_HSTDAT0); /* 3 */ - - /* start the command */ - outb((inb(SMBUS_IO_HSTCTL) | 0x40), SMBUS_IO_HSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_HSTSTAT); - - /* read results of transaction */ - result = inb(SMBUS_IO_HSTDAT0); - - if (host_status_register != 0x02) { - result = -1; - } - return result; -} -#endif /* HAVE_CONSTANT_PROPOGATION */ - - -static void test(void) -{ - short byte; - unsigned device; - unsigned char i, j, k, l, m, n, o; - i = 1; - j = 2; - k = 3; - l = 4; - m = 5; - n = 6; - o = 7; - device = inb(SMBUS_MEM_DEVICE_START); - byte = smbus_read_byte(device, 3); - outb(i, 0xab); - outb(j, 0xab); - outb(k, 0xab); - outb(l, 0x1234); -#if 1 - outb(m, 0xab); -#endif -#if 1 - outb(n, 0xab); -#endif -#if 0 - outb(o, 0xab); -#endif -} diff --git a/util/romcc/tests/simple_test60.c b/util/romcc/tests/simple_test60.c deleted file mode 100644 index 860bf3240d..0000000000 --- a/util/romcc/tests/simple_test60.c +++ /dev/null @@ -1,32 +0,0 @@ -struct mem_param { - unsigned char cycle_time; - unsigned char divisor; - unsigned char tRC; - unsigned char tRFC; - unsigned dch_memclk; - unsigned short dch_tref4k, dch_tref8k; - unsigned char dtl_twr; - char name[9]; -}; - -static void test(void) -{ - static const struct mem_param param0 = { - .name = "166Mhz\r\n", - .cycle_time = 0x60, - .divisor = (6<<1), - .tRC = 0x3C, - .tRFC = 0x48, - .dch_memclk = 5 << 20, - .dch_tref4k = 0x02, - .dch_tref8k = 0x0A, - .dtl_twr = 3, - }; - int value; - unsigned clocks; - const struct mem_param *param; - param = ¶m0; - value = 0x48; -#warning "this generated word loads instead of byte loads" - clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1); -} diff --git a/util/romcc/tests/simple_test61.c b/util/romcc/tests/simple_test61.c deleted file mode 100644 index c0446e22aa..0000000000 --- a/util/romcc/tests/simple_test61.c +++ /dev/null @@ -1,26 +0,0 @@ -static void spd_set_nbxcfg(void) -{ - /* - * Effects: Uses serial presence detect to set the - * ECC support flags in the NBXCFG register - * FIXME: Check for illegal/unsupported ram configurations and abort - */ - unsigned device; - - for(device = 0x50; device <= 0x53; device += 1) { - int byte; - - byte = 0; /* Disable ECC */ - /* 0 == None, 1 == Parity, 2 == ECC */ - if (byte != 2) continue; - - /* set the device I'm talking to */ - __builtin_outb(device, 0x1004); - - /* poll for transaction completion */ - byte = __builtin_inb(0x10); - while(byte == 0) { - byte = __builtin_inb(0x10); - } - } -} diff --git a/util/romcc/tests/simple_test62.c b/util/romcc/tests/simple_test62.c deleted file mode 100644 index 8fed660c5a..0000000000 --- a/util/romcc/tests/simple_test62.c +++ /dev/null @@ -1,7 +0,0 @@ -static const int foo = 1; - -static void main(void) -{ - int x; - x = foo; -} diff --git a/util/romcc/tests/simple_test63.c b/util/romcc/tests/simple_test63.c deleted file mode 100644 index b7df0808a7..0000000000 --- a/util/romcc/tests/simple_test63.c +++ /dev/null @@ -1,8 +0,0 @@ -static const int foo[] = { 1, 2 }; - -static void main(void) -{ - int x, y; - x = foo[0]; - y = foo[1]; -} diff --git a/util/romcc/tests/simple_test64.c b/util/romcc/tests/simple_test64.c deleted file mode 100644 index 389b1c1e32..0000000000 --- a/util/romcc/tests/simple_test64.c +++ /dev/null @@ -1,12 +0,0 @@ -static void main(void) -{ - static const int foo = 2; - switch(foo) { - case 1: - break; - case 2: - break; - default: - break; - } -} diff --git a/util/romcc/tests/simple_test65.c b/util/romcc/tests/simple_test65.c deleted file mode 100644 index 9921e2e9cc..0000000000 --- a/util/romcc/tests/simple_test65.c +++ /dev/null @@ -1,10 +0,0 @@ -enum tag { - X=1, - Y=2, -}; -static void main(void) -{ - enum tag foo; - foo = Y; - -} diff --git a/util/romcc/tests/simple_test66.c b/util/romcc/tests/simple_test66.c deleted file mode 100644 index afc0255345..0000000000 --- a/util/romcc/tests/simple_test66.c +++ /dev/null @@ -1,25 +0,0 @@ -typedef unsigned char uint8_t; -static unsigned int generate_row(uint8_t row, uint8_t maxnodes) -{ - - unsigned int ret=0x00010101; - static const unsigned int rows_2p[2][2] = { - { 0x00050101, 0x00010404 }, - { 0x00010404, 0x00050101 } - }; - if(maxnodes>2) { - maxnodes=2; - } - if (row < maxnodes) { - ret=rows_2p[0][row]; - } - return ret; -} - -static void setup_node(void) -{ - unsigned char row; - for(row=0; row< 2; row++) { - __builtin_outl(generate_row(row, 2), 0x1234); - } -} diff --git a/util/romcc/tests/simple_test67.c b/util/romcc/tests/simple_test67.c deleted file mode 100644 index 70d7170292..0000000000 --- a/util/romcc/tests/simple_test67.c +++ /dev/null @@ -1,24 +0,0 @@ -static void main(void) -{ - unsigned int dch, dcl; -/* HERE I AM async_lat */ - unsigned async_lat; - int dimms; - dimms = 1; - async_lat = 0; - dch = 0x1234; - dcl = __builtin_inl(0x5678); - if (!(dcl & (1 << 8))) { - if (dimms == 4) { - async_lat = 9; - } - else { - async_lat = 8; - } - } - else { - async_lat = 6; - } - dch |= async_lat; - __builtin_outl(dch, 0x9abc); -} diff --git a/util/romcc/tests/simple_test68.c b/util/romcc/tests/simple_test68.c deleted file mode 100644 index dd29658fdc..0000000000 --- a/util/romcc/tests/simple_test68.c +++ /dev/null @@ -1,21 +0,0 @@ -static void main(void) -{ - static const int cpu[] = { 0, 1, 2, 3 }; - int i; - for(i = 0; i < sizeof(cpu)/sizeof(cpu[0]); i++) { - static const unsigned int register_values[] = { - 0x0000c144, 0x0000f8f8, 0x00000000, - 0x0000c14C, 0x0000f8f8, 0x00000001, - 0x0000c154, 0x0000f8f8, 0x00000002, - 0x0000c15C, 0x0000f8f8, 0x00000003, - 0x0000c164, 0x0000f8f8, 0x00000004, - 0x0000c16C, 0x0000f8f8, 0x00000005, - 0x0000c174, 0x0000f8f8, 0x00000006, - 0x0000c17C, 0x0000f8f8, 0x00000007, - }; - int j; - int max = sizeof(register_values)/sizeof(register_values[0]); - for(j = 0; j < max; j += 3) { - } - } -} diff --git a/util/romcc/tests/simple_test69.c b/util/romcc/tests/simple_test69.c deleted file mode 100644 index c01338fc62..0000000000 --- a/util/romcc/tests/simple_test69.c +++ /dev/null @@ -1,22 +0,0 @@ -static void outb(unsigned char value, unsigned short port) -{ - __builtin_outb(value, port); -} - -static void pnp_write_config(void) -{ - unsigned char port; - unsigned char value; - unsigned char reg; - port = 0x2e; - value = 0x03; - reg = 0x07; - outb(reg, port); - outb(value, port +1); - outb(value -1, port +2); -} - -static void main(void) -{ - pnp_write_config(); -} diff --git a/util/romcc/tests/simple_test7.c b/util/romcc/tests/simple_test7.c deleted file mode 100644 index a2065463a3..0000000000 --- a/util/romcc/tests/simple_test7.c +++ /dev/null @@ -1,12 +0,0 @@ -void main(void) -{ - int i; - i = 0; - do { - int j; - __builtin_outb(i, 0xab); - j = i++; - __builtin_outb(j, 0xdc); - } while(i <= 9); - -} diff --git a/util/romcc/tests/simple_test70.c b/util/romcc/tests/simple_test70.c deleted file mode 100644 index ae7b2b172e..0000000000 --- a/util/romcc/tests/simple_test70.c +++ /dev/null @@ -1,22 +0,0 @@ -static void main(void) -{ - int i; - int dest; - - goto start; - foo: - __builtin_outl(dest, 0x5678); - if (dest == 2) goto middle; - goto head; - -start: - dest = 1; - goto foo; - head: - for(i = 0; i < 10; i++) { - dest = 2; - goto foo; - middle: - __builtin_outl(i, 0x1234); - } -} diff --git a/util/romcc/tests/simple_test71.c b/util/romcc/tests/simple_test71.c deleted file mode 100644 index 52ffc8d42c..0000000000 --- a/util/romcc/tests/simple_test71.c +++ /dev/null @@ -1,19 +0,0 @@ -static void foo(void) -{ - __builtin_outl(22, 0x5678); -} -static void main(void) -{ - int i; - - foo(); - foo(); - for(i = 0; i < 10; i++) { - foo(); -#if 0 - foo(); -#endif - __builtin_outl(i, 0x1234); - } - -} diff --git a/util/romcc/tests/simple_test72.c b/util/romcc/tests/simple_test72.c deleted file mode 100644 index 2dda23a5c3..0000000000 --- a/util/romcc/tests/simple_test72.c +++ /dev/null @@ -1,163 +0,0 @@ -static const char *addr_of_char(unsigned char ch) -{ - static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - return byte + ch; -} - - -static void print_debug_char(int c) -{ - asm volatile( - "int $0x80" - : - : "a" (4), "b" (1), "c" (addr_of_char(c)), "d" (1) - ); - -} -static void print_debug_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - print_debug_char(digit); -} -static void print_debug_hex8(unsigned char value) -{ - print_debug_nibble((value >> 4U) & 0x0fU); - print_debug_nibble(value & 0x0fU); -} - -static int smbus_read_byte(unsigned device, unsigned address) -{ - static const unsigned char dimm[] = { -0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01, -0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40, -0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - -0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01, -0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40, -0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }; - return dimm[(device << 8) + address]; -} - -static void spd_set_memclk(void) -{ - /* Compute the minimum cycle time for these dimms */ - unsigned min_cycle_time, min_latency; - unsigned device; - unsigned value; - - value = 0x50; - min_cycle_time= 0x75; - min_latency = 2; - device = 0; - - - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. - */ - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: - * bit 0 == CAS Latency = 1.0 - * bit 1 == CAS Latency = 1.5 - * bit 2 == CAS Latency = 2.0 - * bit 3 == CAS Latency = 2.5 - * bit 4 == CAS Latency = 3.0 - * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD - * bit 7 == TBD - */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = smbus_read_byte(device, 18); - - /* Compute the lowest cas latency supported */ - latency = __builtin_bsr(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for(index = 0; index < 1; index++, latency++) - { - int value; - - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { - continue; - } - value = smbus_read_byte(device, index); - - /* Only increase the latency if we decreas the clock */ - if ((value >= min_cycle_time) && (value < new_cycle_time)) { - new_cycle_time = value; - new_latency = latency; - print_debug_hex8(device); - } - } -} diff --git a/util/romcc/tests/simple_test73.c b/util/romcc/tests/simple_test73.c deleted file mode 100644 index da69cf5e7d..0000000000 --- a/util/romcc/tests/simple_test73.c +++ /dev/null @@ -1,174 +0,0 @@ -static const char *addr_of_char(unsigned char ch) -{ - static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, - }; - return byte + ch; -} - -static void console_tx_byte(unsigned char ch) -{ - asm volatile( - "int $0x80" - : - : "a" (4), "b" (1), "c" (addr_of_char(ch)), "d" (1)); -} - -static void console_tx_string(const char *str) -{ - unsigned char ch; - while((ch = *str++) != '\0') { - console_tx_byte(ch); - } -} - - - -static int smbus_read_byte(unsigned device, unsigned address) -{ - static const unsigned char dimm[] = { -0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01, -0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40, -0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - -0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01, -0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40, -0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - }; - return dimm[(device << 8) + address]; -} - -#define SMBUS_MEM_DEVICE_START 0x00 -#define SMBUS_MEM_DEVICE_END 0x00 -#define SMBUS_MEM_DEVICE_INC 1 - - -static void spd_set_memclk(void) -{ - /* Compute the minimum cycle time for these dimms */ - unsigned min_cycle_time, min_latency; - unsigned device; - unsigned value; - - value = 0x50; - min_cycle_time = 0x75; - min_latency = 2; - device = 0; - - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. - */ - for(device = SMBUS_MEM_DEVICE_START; - device <= SMBUS_MEM_DEVICE_END; - device += SMBUS_MEM_DEVICE_INC) - { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: - * bit 0 == CAS Latency = 1.0 - * bit 1 == CAS Latency = 1.5 - * bit 2 == CAS Latency = 2.0 - * bit 3 == CAS Latency = 2.5 - * bit 4 == CAS Latency = 3.0 - * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD - * bit 7 == TBD - */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = smbus_read_byte(device, 18); - - /* Compute the lowest cas latency supported */ - latency = __builtin_bsr(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for(index = 0; index < 3; index++, latency++) { - int value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { - continue; - } - value = smbus_read_byte(device, index); - if (value < 0) continue; - - /* Only increase the latency if we decreas the clock */ - if ((value >= min_cycle_time) && (value < new_cycle_time)) { - new_cycle_time = value; - new_latency = latency; - console_tx_byte(device); - - } - } - console_tx_string("Transmitting this string causes problems\n"); - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } -} diff --git a/util/romcc/tests/simple_test74.c b/util/romcc/tests/simple_test74.c deleted file mode 100644 index fff1a16e3f..0000000000 --- a/util/romcc/tests/simple_test74.c +++ /dev/null @@ -1,88 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} - -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_write 4 - -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -typedef long ssize_t; -typedef unsigned long size_t; - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} - -static void console_tx_string(const char *str) -{ - unsigned char ch; - while(1) { - - } - for(;1;) { - } - do { - } while(1); - if (1) { - }else { - } -} - - -static void main(void) -{ - static const char msg[] = "hello world\r\n"; - write(STDOUT_FILENO, msg, sizeof(msg)); - _exit(0); -} diff --git a/util/romcc/tests/simple_test75.c b/util/romcc/tests/simple_test75.c deleted file mode 100644 index ae28a3ce1a..0000000000 --- a/util/romcc/tests/simple_test75.c +++ /dev/null @@ -1,21 +0,0 @@ -static void goto_test(void) -{ - int i; - - i = 0; - goto bottom; - { - top: - i = i + 1; - } - bottom: - if (i < 10) { - goto top; - } - ; -} - -static void main(void) -{ - goto_test(); -} diff --git a/util/romcc/tests/simple_test76.c b/util/romcc/tests/simple_test76.c deleted file mode 100644 index 74b1cf1657..0000000000 --- a/util/romcc/tests/simple_test76.c +++ /dev/null @@ -1,69 +0,0 @@ -struct syscall_result { - long val; - int errno; -}; - -static struct syscall_result syscall_return(long result) -{ - struct syscall_result res; - if (((unsigned long)result) >= ((unsigned long)-125)) { - res.errno = - result; - res.val = -1; - } else { - res.errno = 0; - res.val = result; - } - return res; -} -static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1)); - return syscall_return(res); - -} - -static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, - unsigned long arg3) -{ - long res; - asm volatile( - "int $0x80" - : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); - return syscall_return(res); - -} - -#define NR_exit 1 -#define NR_write 4 -/* Standard file descriptors */ -#define STDIN_FILENO 0 /* Standard input */ -#define STDOUT_FILENO 1 /* Standard output */ -#define STDERR_FILENO 2 /* Standard error output */ - -typedef long ssize_t; -typedef unsigned long size_t; - -static ssize_t write(int fd, const void *buf, size_t count) -{ - struct syscall_result res; - res = syscall3(NR_write, fd, (unsigned long)buf, count); - return res.val; -} - -static void _exit(int status) -{ - struct syscall_result res; - res = syscall1(NR_exit, status); -} - -static void main(void) -{ - static const char msg[] = "hello world\r\n"; - write(STDOUT_FILENO, msg, sizeof(msg)); - _exit(0); -} diff --git a/util/romcc/tests/simple_test77.c b/util/romcc/tests/simple_test77.c deleted file mode 100644 index 74be92e39b..0000000000 --- a/util/romcc/tests/simple_test77.c +++ /dev/null @@ -1,5 +0,0 @@ -static void main(void) -{ - do { - } while(1); -} diff --git a/util/romcc/tests/simple_test78.c b/util/romcc/tests/simple_test78.c deleted file mode 100644 index 5e6b27b4bf..0000000000 --- a/util/romcc/tests/simple_test78.c +++ /dev/null @@ -1,7 +0,0 @@ -static void main(void) -{ - int x = 25; - do { - } while(1); - *((volatile int *)5) = x; -} diff --git a/util/romcc/tests/simple_test79.c b/util/romcc/tests/simple_test79.c deleted file mode 100644 index 2f501ca840..0000000000 --- a/util/romcc/tests/simple_test79.c +++ /dev/null @@ -1,5 +0,0 @@ -static void main(void) -{ - do { - } while(0); -} diff --git a/util/romcc/tests/simple_test8.c b/util/romcc/tests/simple_test8.c deleted file mode 100644 index 0b6b853e19..0000000000 --- a/util/romcc/tests/simple_test8.c +++ /dev/null @@ -1,12 +0,0 @@ - - -void main(void) -{ - static const char msg[] = "hello world\r\n"; - char *str; - char ch; - str = msg; - while(1) { - ch = *str++; - } -} diff --git a/util/romcc/tests/simple_test80.c b/util/romcc/tests/simple_test80.c deleted file mode 100644 index 50a3a2a7c2..0000000000 --- a/util/romcc/tests/simple_test80.c +++ /dev/null @@ -1,12 +0,0 @@ -typedef __builtin_msr_t msr_t; - -static msr_t rdmsr(unsigned long index) -{ - return __builtin_rdmsr(index); -} - -static void main(void) -{ - msr_t msr; - msr = rdmsr(0x12345678); -} diff --git a/util/romcc/tests/simple_test81.c b/util/romcc/tests/simple_test81.c deleted file mode 100644 index 1f647aae8d..0000000000 --- a/util/romcc/tests/simple_test81.c +++ /dev/null @@ -1,8 +0,0 @@ -static void main(void) -{ - int i; - i = __builtin_inb(0x1234); - int j; - j = __builtin_inb(0xabcd); - -} diff --git a/util/romcc/tests/simple_test82.c b/util/romcc/tests/simple_test82.c deleted file mode 100644 index a9b7673c4e..0000000000 --- a/util/romcc/tests/simple_test82.c +++ /dev/null @@ -1,16 +0,0 @@ - - -struct result { - int a, b, c, d; -}; - -static struct result main(int a, int b, int c, int d) -{ - struct result result; - result.a = d; - result.b = c; - result.c = b; - result.d = a; - - return result; -} diff --git a/util/romcc/tests/simple_test83.c b/util/romcc/tests/simple_test83.c deleted file mode 100644 index cf9f817fe2..0000000000 --- a/util/romcc/tests/simple_test83.c +++ /dev/null @@ -1,16 +0,0 @@ - - -struct result { - int a, b, c, d; -}; - -static struct result main(int a, int b, int c, int d) -{ - struct result result; - result.a = d + 1; - result.b = c + 1; - result.c = b + 1; - result.d = a + 1; - - return result; -} diff --git a/util/romcc/tests/simple_test84.c b/util/romcc/tests/simple_test84.c deleted file mode 100644 index bc98bf3419..0000000000 --- a/util/romcc/tests/simple_test84.c +++ /dev/null @@ -1,28 +0,0 @@ -struct stuff { - signed int a : 5; - signed int b : 6; - signed int c : 2; - unsigned int d : 3; -}; - -static void main(void) -{ - struct stuff var; - volatile int a, b, c, d; - a = 1; - b = 2; - c = 3; - d = 7; - - var.a = a; - var.b = b; - var.c = c; - var.d = d; - - a = var.a; - b = var.b; - c = var.c; - d = var.d; - - asm(" " :: "r"(a), "r"(b), "r"(c), "r"(d)); -} diff --git a/util/romcc/tests/simple_test85.c b/util/romcc/tests/simple_test85.c deleted file mode 100644 index f223e2e3a5..0000000000 --- a/util/romcc/tests/simple_test85.c +++ /dev/null @@ -1,51 +0,0 @@ -struct sub4 { - unsigned a; - unsigned b; - unsigned c; - unsigned d; - unsigned e; - unsigned f; - unsigned g; -}; -struct sub3 { - unsigned a; - unsigned b; - unsigned c; - unsigned d; - unsigned e; - unsigned f; - struct sub4 s4; -}; -struct sub2 { - unsigned a; - unsigned b; - unsigned c; - unsigned d; - unsigned e; - struct sub3 s3; -}; -struct sub1 { - unsigned a; - unsigned b; - struct sub2 s2; -}; - -struct stuff { - signed int a; - signed int b; - signed int c; - unsigned int d; - struct sub1 s1; -}; - - -static void main(void) -{ - struct stuff *var; - unsigned int *foo; - - var = (struct stuff *)(0x12345678); - foo = &var->d; - foo = &((*var).d); - foo = &var->s1.s2.s3.s4.g; -} diff --git a/util/romcc/tests/simple_test86.c b/util/romcc/tests/simple_test86.c deleted file mode 100644 index d9d4c6584b..0000000000 --- a/util/romcc/tests/simple_test86.c +++ /dev/null @@ -1,5 +0,0 @@ -static void main(void) -{ - asm("cpuid" - ::: "eax", "ebx", "ecx", "edx"); -} diff --git a/util/romcc/tests/simple_test87.c b/util/romcc/tests/simple_test87.c deleted file mode 100644 index 6a1148c46a..0000000000 --- a/util/romcc/tests/simple_test87.c +++ /dev/null @@ -1,4 +0,0 @@ -static void main(void) -{ - char *x = ""; -} diff --git a/util/romcc/tests/simple_test9.c b/util/romcc/tests/simple_test9.c deleted file mode 100644 index e8df1b9afb..0000000000 --- a/util/romcc/tests/simple_test9.c +++ /dev/null @@ -1,12 +0,0 @@ - - -void main(void) -{ - static const char msg[] = "hello world\r\n"; - char *str; - char ch; - str = msg; - do { - ch = *str++; - } while(ch); -} |